identcpu.c revision 1.114
1/* $OpenBSD: identcpu.c,v 1.114 2020/03/17 03:09:04 dlg Exp $ */ 2/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ 3 4/* 5 * Copyright (c) 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Frank van der Linden for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/sysctl.h> 42 43#include "vmm.h" 44 45#include <machine/cpu.h> 46#include <machine/cpufunc.h> 47 48void replacesmap(void); 49void replacemeltdown(void); 50uint64_t cpu_freq(struct cpu_info *); 51void tsc_timecounter_init(struct cpu_info *, uint64_t); 52#if NVMM > 0 53void cpu_check_vmm_cap(struct cpu_info *); 54#endif /* NVMM > 0 */ 55 56/* sysctl wants this. */ 57char cpu_model[48]; 58int cpuspeed; 59 60int amd64_has_xcrypt; 61#ifdef CRYPTO 62int amd64_has_pclmul; 63int amd64_has_aesni; 64#endif 65int has_rdrand; 66int has_rdseed; 67 68#include "pvbus.h" 69#if NPVBUS > 0 70#include <dev/pv/pvvar.h> 71#endif 72 73const struct { 74 u_int32_t bit; 75 char str[12]; 76} cpu_cpuid_features[] = { 77 { CPUID_FPU, "FPU" }, 78 { CPUID_VME, "VME" }, 79 { CPUID_DE, "DE" }, 80 { CPUID_PSE, "PSE" }, 81 { CPUID_TSC, "TSC" }, 82 { CPUID_MSR, "MSR" }, 83 { CPUID_PAE, "PAE" }, 84 { CPUID_MCE, "MCE" }, 85 { CPUID_CX8, "CX8" }, 86 { CPUID_APIC, "APIC" }, 87 { CPUID_SEP, "SEP" }, 88 { CPUID_MTRR, "MTRR" }, 89 { CPUID_PGE, "PGE" }, 90 { CPUID_MCA, "MCA" }, 91 { CPUID_CMOV, "CMOV" }, 92 { CPUID_PAT, "PAT" }, 93 { CPUID_PSE36, "PSE36" }, 94 { CPUID_PSN, "PSN" }, 95 { CPUID_CFLUSH, "CFLUSH" }, 96 { CPUID_DS, "DS" }, 97 { CPUID_ACPI, "ACPI" }, 98 { CPUID_MMX, "MMX" }, 99 { CPUID_FXSR, "FXSR" }, 100 { CPUID_SSE, "SSE" }, 101 { CPUID_SSE2, "SSE2" }, 102 { CPUID_SS, "SS" }, 103 { CPUID_HTT, "HTT" }, 104 { CPUID_TM, "TM" }, 105 { CPUID_PBE, "PBE" } 106}, cpu_ecpuid_features[] = { 107 { CPUID_MPC, "MPC" }, 108 { CPUID_NXE, "NXE" }, 109 { CPUID_MMXX, "MMXX" }, 110 { CPUID_FFXSR, "FFXSR" }, 111 { CPUID_PAGE1GB, "PAGE1GB" }, 112 { CPUID_RDTSCP, "RDTSCP" }, 113 { CPUID_LONG, "LONG" }, 114 { CPUID_3DNOW2, "3DNOW2" }, 115 { CPUID_3DNOW, "3DNOW" } 116}, cpu_cpuid_ecxfeatures[] = { 117 { CPUIDECX_SSE3, "SSE3" }, 118 { CPUIDECX_PCLMUL, "PCLMUL" }, 119 { CPUIDECX_DTES64, "DTES64" }, 120 { CPUIDECX_MWAIT, "MWAIT" }, 121 { CPUIDECX_DSCPL, "DS-CPL" }, 122 { CPUIDECX_VMX, "VMX" }, 123 { CPUIDECX_SMX, "SMX" }, 124 { CPUIDECX_EST, "EST" }, 125 { CPUIDECX_TM2, "TM2" }, 126 { CPUIDECX_SSSE3, "SSSE3" }, 127 { CPUIDECX_CNXTID, "CNXT-ID" }, 128 { CPUIDECX_SDBG, "SDBG" }, 129 { CPUIDECX_FMA3, "FMA3" }, 130 { CPUIDECX_CX16, "CX16" }, 131 { CPUIDECX_XTPR, "xTPR" }, 132 { CPUIDECX_PDCM, "PDCM" }, 133 { CPUIDECX_PCID, "PCID" }, 134 { CPUIDECX_DCA, "DCA" }, 135 { CPUIDECX_SSE41, "SSE4.1" }, 136 { CPUIDECX_SSE42, "SSE4.2" }, 137 { CPUIDECX_X2APIC, "x2APIC" }, 138 { CPUIDECX_MOVBE, "MOVBE" }, 139 { CPUIDECX_POPCNT, "POPCNT" }, 140 { CPUIDECX_DEADLINE, "DEADLINE" }, 141 { CPUIDECX_AES, "AES" }, 142 { CPUIDECX_XSAVE, "XSAVE" }, 143 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 144 { CPUIDECX_AVX, "AVX" }, 145 { CPUIDECX_F16C, "F16C" }, 146 { CPUIDECX_RDRAND, "RDRAND" }, 147 { CPUIDECX_HV, "HV" }, 148}, cpu_ecpuid_ecxfeatures[] = { 149 { CPUIDECX_LAHF, "LAHF" }, 150 { CPUIDECX_CMPLEG, "CMPLEG" }, 151 { CPUIDECX_SVM, "SVM" }, 152 { CPUIDECX_EAPICSP, "EAPICSP"}, 153 { CPUIDECX_AMCR8, "AMCR8"}, 154 { CPUIDECX_ABM, "ABM" }, 155 { CPUIDECX_SSE4A, "SSE4A" }, 156 { CPUIDECX_MASSE, "MASSE" }, 157 { CPUIDECX_3DNOWP, "3DNOWP" }, 158 { CPUIDECX_OSVW, "OSVW" }, 159 { CPUIDECX_IBS, "IBS" }, 160 { CPUIDECX_XOP, "XOP" }, 161 { CPUIDECX_SKINIT, "SKINIT" }, 162 { CPUIDECX_LWP, "WDT" }, 163 { CPUIDECX_FMA4, "FMA4" }, 164 { CPUIDECX_TCE, "TCE" }, 165 { CPUIDECX_NODEID, "NODEID" }, 166 { CPUIDECX_TBM, "TBM" }, 167 { CPUIDECX_TOPEXT, "TOPEXT" }, 168 { CPUIDECX_CPCTR, "CPCTR" }, 169 { CPUIDECX_DBKP, "DBKP" }, 170 { CPUIDECX_PERFTSC, "PERFTSC" }, 171 { CPUIDECX_PCTRL3, "PCTRL3" }, 172 { CPUIDECX_MWAITX, "MWAITX" }, 173}, cpu_seff0_ebxfeatures[] = { 174 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 175 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 176 { SEFF0EBX_SGX, "SGX" }, 177 { SEFF0EBX_BMI1, "BMI1" }, 178 { SEFF0EBX_HLE, "HLE" }, 179 { SEFF0EBX_AVX2, "AVX2" }, 180 { SEFF0EBX_SMEP, "SMEP" }, 181 { SEFF0EBX_BMI2, "BMI2" }, 182 { SEFF0EBX_ERMS, "ERMS" }, 183 { SEFF0EBX_INVPCID, "INVPCID" }, 184 { SEFF0EBX_RTM, "RTM" }, 185 { SEFF0EBX_PQM, "PQM" }, 186 { SEFF0EBX_MPX, "MPX" }, 187 { SEFF0EBX_AVX512F, "AVX512F" }, 188 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 189 { SEFF0EBX_RDSEED, "RDSEED" }, 190 { SEFF0EBX_ADX, "ADX" }, 191 { SEFF0EBX_SMAP, "SMAP" }, 192 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 193 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 194 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 195 { SEFF0EBX_CLWB, "CLWB" }, 196 { SEFF0EBX_PT, "PT" }, 197 { SEFF0EBX_AVX512PF, "AVX512PF" }, 198 { SEFF0EBX_AVX512ER, "AVX512ER" }, 199 { SEFF0EBX_AVX512CD, "AVX512CD" }, 200 { SEFF0EBX_SHA, "SHA" }, 201 { SEFF0EBX_AVX512BW, "AVX512BW" }, 202 { SEFF0EBX_AVX512VL, "AVX512VL" }, 203}, cpu_seff0_ecxfeatures[] = { 204 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 205 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 206 { SEFF0ECX_UMIP, "UMIP" }, 207 { SEFF0ECX_PKU, "PKU" }, 208}, cpu_seff0_edxfeatures[] = { 209 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 210 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 211 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, 212 { SEFF0EDX_TSXFA, "TSXFA" }, 213 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 214 { SEFF0EDX_STIBP, "STIBP" }, 215 { SEFF0EDX_L1DF, "L1DF" }, 216 /* SEFF0EDX_ARCH_CAP (not printed) */ 217 { SEFF0EDX_SSBD, "SSBD" }, 218}, cpu_tpm_eaxfeatures[] = { 219 { TPM_SENSOR, "SENSOR" }, 220 { TPM_ARAT, "ARAT" }, 221}, cpu_cpuid_perf_eax[] = { 222 { CPUIDEAX_VERID, "PERF" }, 223}, cpu_cpuid_apmi_edx[] = { 224 { CPUIDEDX_ITSC, "ITSC" }, 225}, cpu_amdspec_ebxfeatures[] = { 226 { CPUIDEBX_IBPB, "IBPB" }, 227 { CPUIDEBX_IBRS, "IBRS" }, 228 { CPUIDEBX_STIBP, "STIBP" }, 229 { CPUIDEBX_SSBD, "SSBD" }, 230 { CPUIDEBX_VIRT_SSBD, "VIRTSSBD" }, 231 { CPUIDEBX_SSBD_NOTREQ, "SSBDNR" }, 232}, cpu_xsave_extfeatures[] = { 233 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 234 { XSAVE_XSAVEC, "XSAVEC" }, 235 { XSAVE_XGETBV1, "XGETBV1" }, 236 { XSAVE_XSAVES, "XSAVES" }, 237}; 238 239int 240cpu_amd64speed(int *freq) 241{ 242 *freq = cpuspeed; 243 return (0); 244} 245 246#ifndef SMALL_KERNEL 247void intelcore_update_sensor(void *args); 248/* 249 * Temperature read on the CPU is relative to the maximum 250 * temperature supported by the CPU, Tj(Max). 251 * Refer to: 252 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 253 * Section 35 and 254 * http://www.intel.com/content/dam/www/public/us/en/documents/ 255 * white-papers/cpu-monitoring-dts-peci-paper.pdf 256 * 257 * The temperature on Intel CPUs can be between 70 and 105 degC, since 258 * Westmere we can read the TJmax from the die. For older CPUs we have 259 * to guess or use undocumented MSRs. Then we subtract the temperature 260 * portion of thermal status from max to get current temperature. 261 */ 262void 263intelcore_update_sensor(void *args) 264{ 265 struct cpu_info *ci = (struct cpu_info *) args; 266 u_int64_t msr; 267 int max = 100; 268 269 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 270 if (ci->ci_model == 0x0e && 271 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 272 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 273 max = 85; 274 275 /* 276 * Newer CPUs can tell you what their max temperature is. 277 * See: '64-ia-32-architectures-software-developer- 278 * vol-3c-part-3-manual.pdf' 279 */ 280 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 281 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 282 ci->ci_model != 0x35 && ci->ci_model != 0x36) 283 max = MSR_TEMPERATURE_TARGET_TJMAX( 284 rdmsr(MSR_TEMPERATURE_TARGET)); 285 286 msr = rdmsr(MSR_THERM_STATUS); 287 if (msr & MSR_THERM_STATUS_VALID_BIT) { 288 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 289 /* micro degrees */ 290 ci->ci_sensor.value *= 1000000; 291 /* kelvin */ 292 ci->ci_sensor.value += 273150000; 293 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 294 } else { 295 ci->ci_sensor.value = 0; 296 ci->ci_sensor.flags |= SENSOR_FINVALID; 297 } 298} 299 300#endif 301 302void (*setperf_setup)(struct cpu_info *); 303 304void via_nano_setup(struct cpu_info *ci); 305 306void cpu_topology(struct cpu_info *ci); 307 308void 309via_nano_setup(struct cpu_info *ci) 310{ 311 u_int32_t regs[4], val; 312 u_int64_t msreg; 313 int model = (ci->ci_signature >> 4) & 15; 314 315 if (model >= 9) { 316 CPUID(0xC0000000, regs[0], regs[1], regs[2], regs[3]); 317 val = regs[0]; 318 if (val >= 0xC0000001) { 319 CPUID(0xC0000001, regs[0], regs[1], regs[2], regs[3]); 320 val = regs[3]; 321 } else 322 val = 0; 323 324 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 325 printf("%s:", ci->ci_dev->dv_xname); 326 327 /* Enable RNG if present and disabled */ 328 if (val & C3_CPUID_HAS_RNG) { 329 extern int viac3_rnd_present; 330 331 if (!(val & C3_CPUID_DO_RNG)) { 332 msreg = rdmsr(0x110B); 333 msreg |= 0x40; 334 wrmsr(0x110B, msreg); 335 } 336 viac3_rnd_present = 1; 337 printf(" RNG"); 338 } 339 340 /* Enable AES engine if present and disabled */ 341 if (val & C3_CPUID_HAS_ACE) { 342#ifdef CRYPTO 343 if (!(val & C3_CPUID_DO_ACE)) { 344 msreg = rdmsr(0x1107); 345 msreg |= (0x01 << 28); 346 wrmsr(0x1107, msreg); 347 } 348 amd64_has_xcrypt |= C3_HAS_AES; 349#endif /* CRYPTO */ 350 printf(" AES"); 351 } 352 353 /* Enable ACE2 engine if present and disabled */ 354 if (val & C3_CPUID_HAS_ACE2) { 355#ifdef CRYPTO 356 if (!(val & C3_CPUID_DO_ACE2)) { 357 msreg = rdmsr(0x1107); 358 msreg |= (0x01 << 28); 359 wrmsr(0x1107, msreg); 360 } 361 amd64_has_xcrypt |= C3_HAS_AESCTR; 362#endif /* CRYPTO */ 363 printf(" AES-CTR"); 364 } 365 366 /* Enable SHA engine if present and disabled */ 367 if (val & C3_CPUID_HAS_PHE) { 368#ifdef CRYPTO 369 if (!(val & C3_CPUID_DO_PHE)) { 370 msreg = rdmsr(0x1107); 371 msreg |= (0x01 << 28/**/); 372 wrmsr(0x1107, msreg); 373 } 374 amd64_has_xcrypt |= C3_HAS_SHA; 375#endif /* CRYPTO */ 376 printf(" SHA1 SHA256"); 377 } 378 379 /* Enable MM engine if present and disabled */ 380 if (val & C3_CPUID_HAS_PMM) { 381#ifdef CRYPTO 382 if (!(val & C3_CPUID_DO_PMM)) { 383 msreg = rdmsr(0x1107); 384 msreg |= (0x01 << 28/**/); 385 wrmsr(0x1107, msreg); 386 } 387 amd64_has_xcrypt |= C3_HAS_MM; 388#endif /* CRYPTO */ 389 printf(" RSA"); 390 } 391 392 printf("\n"); 393 } 394} 395 396#ifndef SMALL_KERNEL 397void via_update_sensor(void *args); 398void 399via_update_sensor(void *args) 400{ 401 struct cpu_info *ci = (struct cpu_info *) args; 402 u_int64_t msr; 403 404 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 405 ci->ci_sensor.value = (msr & 0xffffff); 406 /* micro degrees */ 407 ci->ci_sensor.value *= 1000000; 408 ci->ci_sensor.value += 273150000; 409 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 410} 411#endif 412 413uint64_t 414cpu_freq_ctr(struct cpu_info *ci) 415{ 416 uint64_t count, last_count, msr; 417 418 if ((ci->ci_flags & CPUF_CONST_TSC) == 0 || 419 (cpu_perf_eax & CPUIDEAX_VERID) <= 1 || 420 CPUIDEDX_NUM_FC(cpu_perf_edx) <= 1) 421 return (0); 422 423 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 424 if (msr & MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK)) { 425 /* some hypervisor is dicking us around */ 426 return (0); 427 } 428 429 msr |= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_1); 430 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 431 432 msr = rdmsr(MSR_PERF_GLOBAL_CTRL) | MSR_PERF_GLOBAL_CTR1_EN; 433 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 434 435 last_count = rdmsr(MSR_PERF_FIXED_CTR1); 436 delay(100000); 437 count = rdmsr(MSR_PERF_FIXED_CTR1); 438 439 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 440 msr &= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK); 441 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 442 443 msr = rdmsr(MSR_PERF_GLOBAL_CTRL); 444 msr &= ~MSR_PERF_GLOBAL_CTR1_EN; 445 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 446 447 return ((count - last_count) * 10); 448} 449 450uint64_t 451cpu_freq(struct cpu_info *ci) 452{ 453 uint64_t last_count, count; 454 455 count = cpu_freq_ctr(ci); 456 if (count != 0) 457 return (count); 458 459 last_count = rdtsc(); 460 delay(100000); 461 count = rdtsc(); 462 463 return ((count - last_count) * 10); 464} 465 466void 467identifycpu(struct cpu_info *ci) 468{ 469 uint64_t freq = 0; 470 u_int32_t dummy, val; 471 char mycpu_model[48]; 472 int i; 473 char *brandstr_from, *brandstr_to; 474 int skipspace; 475 476 CPUID(1, ci->ci_signature, val, dummy, ci->ci_feature_flags); 477 CPUID(0x80000000, ci->ci_pnfeatset, dummy, dummy, dummy); 478 if (ci->ci_pnfeatset >= 0x80000001) { 479 CPUID(0x80000001, ci->ci_efeature_eax, dummy, 480 ci->ci_efeature_ecx, ci->ci_feature_eflags); 481 /* Other bits may clash */ 482 ci->ci_feature_flags |= (ci->ci_feature_eflags & CPUID_NXE); 483 if (ci->ci_flags & CPUF_PRIMARY) 484 ecpu_ecxfeature = ci->ci_efeature_ecx; 485 /* Let cpu_feature be the common bits */ 486 cpu_feature &= ci->ci_feature_flags; 487 } 488 489 CPUID(0x80000002, ci->ci_brand[0], 490 ci->ci_brand[1], ci->ci_brand[2], ci->ci_brand[3]); 491 CPUID(0x80000003, ci->ci_brand[4], 492 ci->ci_brand[5], ci->ci_brand[6], ci->ci_brand[7]); 493 CPUID(0x80000004, ci->ci_brand[8], 494 ci->ci_brand[9], ci->ci_brand[10], ci->ci_brand[11]); 495 strlcpy(mycpu_model, (char *)ci->ci_brand, sizeof(mycpu_model)); 496 497 /* Remove leading, trailing and duplicated spaces from mycpu_model */ 498 brandstr_from = brandstr_to = mycpu_model; 499 skipspace = 1; 500 while (*brandstr_from != '\0') { 501 if (!skipspace || *brandstr_from != ' ') { 502 skipspace = 0; 503 *(brandstr_to++) = *brandstr_from; 504 } 505 if (*brandstr_from == ' ') 506 skipspace = 1; 507 brandstr_from++; 508 } 509 if (skipspace && brandstr_to > mycpu_model) 510 brandstr_to--; 511 *brandstr_to = '\0'; 512 513 if (mycpu_model[0] == 0) 514 strlcpy(mycpu_model, "Opteron or Athlon 64", 515 sizeof(mycpu_model)); 516 517 /* If primary cpu, fill in the global cpu_model used by sysctl */ 518 if (ci->ci_flags & CPUF_PRIMARY) 519 strlcpy(cpu_model, mycpu_model, sizeof(cpu_model)); 520 521 ci->ci_family = (ci->ci_signature >> 8) & 0x0f; 522 ci->ci_model = (ci->ci_signature >> 4) & 0x0f; 523 if (ci->ci_family == 0x6 || ci->ci_family == 0xf) { 524 ci->ci_family += (ci->ci_signature >> 20) & 0xff; 525 ci->ci_model += ((ci->ci_signature >> 16) & 0x0f) << 4; 526 } 527 528 if (ci->ci_feature_flags && ci->ci_feature_flags & CPUID_TSC) { 529 /* Has TSC, check if it's constant */ 530 if (!strcmp(cpu_vendor, "GenuineIntel")) { 531 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 532 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 533 ci->ci_flags |= CPUF_CONST_TSC; 534 } 535 } else if (!strcmp(cpu_vendor, "CentaurHauls")) { 536 /* VIA */ 537 if (ci->ci_model >= 0x0f) { 538 ci->ci_flags |= CPUF_CONST_TSC; 539 } 540 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 541 if (cpu_apmi_edx & CPUIDEDX_ITSC) { 542 /* Invariant TSC indicates constant TSC on 543 * AMD. 544 */ 545 ci->ci_flags |= CPUF_CONST_TSC; 546 } 547 } 548 549 /* Check if it's an invariant TSC */ 550 if (cpu_apmi_edx & CPUIDEDX_ITSC) 551 ci->ci_flags |= CPUF_INVAR_TSC; 552 } 553 554 freq = cpu_freq(ci); 555 556 amd_cpu_cacheinfo(ci); 557 558 printf("%s: %s", ci->ci_dev->dv_xname, mycpu_model); 559 560 if (freq != 0) 561 printf(", %llu.%02llu MHz", (freq + 4999) / 1000000, 562 ((freq + 4999) / 10000) % 100); 563 564 if (ci->ci_flags & CPUF_PRIMARY) { 565 cpuspeed = (freq + 4999) / 1000000; 566 cpu_cpuspeed = cpu_amd64speed; 567 } 568 569 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 570 ci->ci_signature & 0x0f); 571 572 printf("\n%s: ", ci->ci_dev->dv_xname); 573 574 for (i = 0; i < nitems(cpu_cpuid_features); i++) 575 if (ci->ci_feature_flags & cpu_cpuid_features[i].bit) 576 printf("%s%s", i? "," : "", cpu_cpuid_features[i].str); 577 for (i = 0; i < nitems(cpu_cpuid_ecxfeatures); i++) 578 if (cpu_ecxfeature & cpu_cpuid_ecxfeatures[i].bit) 579 printf(",%s", cpu_cpuid_ecxfeatures[i].str); 580 for (i = 0; i < nitems(cpu_ecpuid_features); i++) 581 if (ci->ci_feature_eflags & cpu_ecpuid_features[i].bit) 582 printf(",%s", cpu_ecpuid_features[i].str); 583 for (i = 0; i < nitems(cpu_ecpuid_ecxfeatures); i++) 584 if (ecpu_ecxfeature & cpu_ecpuid_ecxfeatures[i].bit) 585 printf(",%s", cpu_ecpuid_ecxfeatures[i].str); 586 for (i = 0; i < nitems(cpu_cpuid_perf_eax); i++) 587 if (cpu_perf_eax & cpu_cpuid_perf_eax[i].bit) 588 printf(",%s", cpu_cpuid_perf_eax[i].str); 589 for (i = 0; i < nitems(cpu_cpuid_apmi_edx); i++) 590 if (cpu_apmi_edx & cpu_cpuid_apmi_edx[i].bit) 591 printf(",%s", cpu_cpuid_apmi_edx[i].str); 592 593 if (cpuid_level >= 0x07) { 594 /* "Structured Extended Feature Flags" */ 595 CPUID_LEAF(0x7, 0, dummy, ci->ci_feature_sefflags_ebx, 596 ci->ci_feature_sefflags_ecx, ci->ci_feature_sefflags_edx); 597 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 598 if (ci->ci_feature_sefflags_ebx & 599 cpu_seff0_ebxfeatures[i].bit) 600 printf(",%s", cpu_seff0_ebxfeatures[i].str); 601 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 602 if (ci->ci_feature_sefflags_ecx & 603 cpu_seff0_ecxfeatures[i].bit) 604 printf(",%s", cpu_seff0_ecxfeatures[i].str); 605 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 606 if (ci->ci_feature_sefflags_edx & 607 cpu_seff0_edxfeatures[i].bit) 608 printf(",%s", cpu_seff0_edxfeatures[i].str); 609 } 610 611 if (!strcmp(cpu_vendor, "GenuineIntel") && cpuid_level >= 0x06) { 612 CPUID(0x06, ci->ci_feature_tpmflags, dummy, dummy, dummy); 613 for (i = 0; i < nitems(cpu_tpm_eaxfeatures); i++) 614 if (ci->ci_feature_tpmflags & 615 cpu_tpm_eaxfeatures[i].bit) 616 printf(",%s", cpu_tpm_eaxfeatures[i].str); 617 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 618 if (ci->ci_family >= 0x12) 619 ci->ci_feature_tpmflags |= TPM_ARAT; 620 } 621 622 /* AMD speculation control features */ 623 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 624 if (ci->ci_pnfeatset >= 0x80000008) { 625 CPUID(0x80000008, dummy, ci->ci_feature_amdspec_ebx, 626 dummy, dummy); 627 for (i = 0; i < nitems(cpu_amdspec_ebxfeatures); i++) 628 if (ci->ci_feature_amdspec_ebx & 629 cpu_amdspec_ebxfeatures[i].bit) 630 printf(",%s", 631 cpu_amdspec_ebxfeatures[i].str); 632 } 633 } 634 635 /* xsave subfeatures */ 636 if (cpuid_level >= 0xd) { 637 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 638 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 639 if (val & cpu_xsave_extfeatures[i].bit) 640 printf(",%s", cpu_xsave_extfeatures[i].str); 641 } 642 643 if (cpu_meltdown) 644 printf(",MELTDOWN"); 645 646 printf("\n"); 647 648 replacemeltdown(); 649 x86_print_cacheinfo(ci); 650 651 /* 652 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 653 * for Managing Speculation on AMD Processors" 654 * 655 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 656 * serializing instruction. 657 * 658 * This MSR is available on all AMD families >= 10h, except 11h 659 * where LFENCE is always serializing. 660 */ 661 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 662 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 663 uint64_t msr; 664 665 msr = rdmsr(MSR_DE_CFG); 666 if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { 667 msr |= DE_CFG_SERIALIZE_LFENCE; 668 wrmsr(MSR_DE_CFG, msr); 669 } 670 } 671 } 672 673 /* 674 * Attempt to disable Silicon Debug and lock the configuration 675 * if it's enabled and unlocked. 676 */ 677 if (!strcmp(cpu_vendor, "GenuineIntel") && 678 (cpu_ecxfeature & CPUIDECX_SDBG)) { 679 uint64_t msr; 680 681 msr = rdmsr(IA32_DEBUG_INTERFACE); 682 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 683 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 684 msr &= IA32_DEBUG_INTERFACE_MASK; 685 msr |= IA32_DEBUG_INTERFACE_LOCK; 686 wrmsr(IA32_DEBUG_INTERFACE, msr); 687 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 688 printf("%s: cannot disable silicon debug\n", 689 ci->ci_dev->dv_xname); 690 } 691 692 if (ci->ci_flags & CPUF_PRIMARY) { 693#ifndef SMALL_KERNEL 694 if (!strcmp(cpu_vendor, "AuthenticAMD") && 695 ci->ci_pnfeatset >= 0x80000007) { 696 CPUID(0x80000007, dummy, dummy, dummy, val); 697 698 if (val & 0x06) { 699 if ((ci->ci_signature & 0xF00) == 0xF00) 700 setperf_setup = k8_powernow_init; 701 } 702 if (ci->ci_family >= 0x10) 703 setperf_setup = k1x_init; 704 } 705 706 if (cpu_ecxfeature & CPUIDECX_EST) 707 setperf_setup = est_init; 708#endif 709 710 if (cpu_ecxfeature & CPUIDECX_RDRAND) 711 has_rdrand = 1; 712 713 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 714 has_rdseed = 1; 715 716 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 717 replacesmap(); 718 } 719#ifndef SMALL_KERNEL 720 if (!strncmp(mycpu_model, "Intel", 5)) { 721 u_int32_t cflushsz; 722 723 CPUID(0x01, dummy, cflushsz, dummy, dummy); 724 /* cflush cacheline size is equal to bits 15-8 of ebx * 8 */ 725 ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8; 726 } 727 728 if (CPU_IS_PRIMARY(ci) && (ci->ci_feature_tpmflags & TPM_SENSOR)) { 729 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 730 sizeof(ci->ci_sensordev.xname)); 731 ci->ci_sensor.type = SENSOR_TEMP; 732 sensor_task_register(ci, intelcore_update_sensor, 5); 733 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 734 sensordev_install(&ci->ci_sensordev); 735 } 736#endif 737 738#ifdef CRYPTO 739 if (ci->ci_flags & CPUF_PRIMARY) { 740 if (cpu_ecxfeature & CPUIDECX_PCLMUL) 741 amd64_has_pclmul = 1; 742 743 if (cpu_ecxfeature & CPUIDECX_AES) 744 amd64_has_aesni = 1; 745 } 746#endif 747 748 if (!strcmp(cpu_vendor, "AuthenticAMD")) 749 amd64_errata(ci); 750 751 if (CPU_IS_PRIMARY(ci) && !strcmp(cpu_vendor, "CentaurHauls")) { 752 ci->cpu_setup = via_nano_setup; 753#ifndef SMALL_KERNEL 754 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 755 sizeof(ci->ci_sensordev.xname)); 756 ci->ci_sensor.type = SENSOR_TEMP; 757 sensor_task_register(ci, via_update_sensor, 5); 758 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 759 sensordev_install(&ci->ci_sensordev); 760#endif 761 } 762 763 tsc_timecounter_init(ci, freq); 764 765 cpu_topology(ci); 766#if NVMM > 0 767 cpu_check_vmm_cap(ci); 768#endif /* NVMM > 0 */ 769} 770 771#ifndef SMALL_KERNEL 772/* 773 * Base 2 logarithm of an int. returns 0 for 0 (yeye, I know). 774 */ 775static int 776log2(unsigned int i) 777{ 778 int ret = 0; 779 780 while (i >>= 1) 781 ret++; 782 783 return (ret); 784} 785 786static int 787mask_width(u_int x) 788{ 789 int bit; 790 int mask; 791 int powerof2; 792 793 powerof2 = ((x - 1) & x) == 0; 794 mask = (x << (1 - powerof2)) - 1; 795 796 /* fls */ 797 if (mask == 0) 798 return (0); 799 for (bit = 1; mask != 1; bit++) 800 mask = (unsigned int)mask >> 1; 801 802 return (bit); 803} 804#endif 805 806/* 807 * Build up cpu topology for given cpu, must run on the core itself. 808 */ 809void 810cpu_topology(struct cpu_info *ci) 811{ 812#ifndef SMALL_KERNEL 813 u_int32_t eax, ebx, ecx, edx; 814 u_int32_t apicid, max_apicid = 0, max_coreid = 0; 815 u_int32_t smt_bits = 0, core_bits, pkg_bits = 0; 816 u_int32_t smt_mask = 0, core_mask, pkg_mask = 0; 817 818 /* We need at least apicid at CPUID 1 */ 819 if (cpuid_level < 1) 820 goto no_topology; 821 822 /* Initial apicid */ 823 CPUID(1, eax, ebx, ecx, edx); 824 apicid = (ebx >> 24) & 0xff; 825 826 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 827 uint32_t nthreads = 1; /* per core */ 828 uint32_t thread_id; /* within a package */ 829 830 /* We need at least apicid at CPUID 0x80000008 */ 831 if (ci->ci_pnfeatset < 0x80000008) 832 goto no_topology; 833 834 CPUID(0x80000008, eax, ebx, ecx, edx); 835 core_bits = (ecx >> 12) & 0xf; 836 837 if (ci->ci_pnfeatset >= 0x8000001e) { 838 CPUID(0x8000001e, eax, ebx, ecx, edx); 839 nthreads = ((ebx >> 8) & 0xf) + 1; 840 } 841 842 /* Shift the core_bits off to get at the pkg bits */ 843 ci->ci_pkg_id = apicid >> core_bits; 844 845 /* Get rid of the package bits */ 846 core_mask = (1 << core_bits) - 1; 847 thread_id = apicid & core_mask; 848 849 /* Cut logical thread_id into core id, and smt id in a core */ 850 ci->ci_core_id = thread_id / nthreads; 851 ci->ci_smt_id = thread_id % nthreads; 852 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 853 /* We only support leaf 1/4 detection */ 854 if (cpuid_level < 4) 855 goto no_topology; 856 /* Get max_apicid */ 857 CPUID(1, eax, ebx, ecx, edx); 858 max_apicid = (ebx >> 16) & 0xff; 859 /* Get max_coreid */ 860 CPUID_LEAF(4, 0, eax, ebx, ecx, edx); 861 max_coreid = ((eax >> 26) & 0x3f) + 1; 862 /* SMT */ 863 smt_bits = mask_width(max_apicid / max_coreid); 864 smt_mask = (1 << smt_bits) - 1; 865 /* Core */ 866 core_bits = log2(max_coreid); 867 core_mask = (1 << (core_bits + smt_bits)) - 1; 868 core_mask ^= smt_mask; 869 /* Pkg */ 870 pkg_bits = core_bits + smt_bits; 871 pkg_mask = -1 << core_bits; 872 873 ci->ci_smt_id = apicid & smt_mask; 874 ci->ci_core_id = (apicid & core_mask) >> smt_bits; 875 ci->ci_pkg_id = (apicid & pkg_mask) >> pkg_bits; 876 } else 877 goto no_topology; 878#ifdef DEBUG 879 printf("cpu%d: smt %u, core %u, pkg %u " 880 "(apicid 0x%x, max_apicid 0x%x, max_coreid 0x%x, smt_bits 0x%x, smt_mask 0x%x, " 881 "core_bits 0x%x, core_mask 0x%x, pkg_bits 0x%x, pkg_mask 0x%x)\n", 882 ci->ci_cpuid, ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id, 883 apicid, max_apicid, max_coreid, smt_bits, smt_mask, core_bits, 884 core_mask, pkg_bits, pkg_mask); 885#else 886 printf("cpu%d: smt %u, core %u, package %u\n", ci->ci_cpuid, 887 ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id); 888 889#endif 890 return; 891 /* We can't map, so consider ci_core_id as ci_cpuid */ 892no_topology: 893#endif 894 ci->ci_smt_id = 0; 895 ci->ci_core_id = ci->ci_cpuid; 896 ci->ci_pkg_id = 0; 897} 898 899#if NVMM > 0 900/* 901 * cpu_check_vmm_cap 902 * 903 * Checks for VMM capabilities for 'ci'. Initializes certain per-cpu VMM 904 * state in 'ci' if virtualization extensions are found. 905 * 906 * Parameters: 907 * ci: the cpu being checked 908 */ 909void 910cpu_check_vmm_cap(struct cpu_info *ci) 911{ 912 uint64_t msr; 913 uint32_t cap, dummy, edx; 914 915 /* 916 * Check for workable VMX 917 */ 918 if (cpu_ecxfeature & CPUIDECX_VMX) { 919 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 920 921 if (!(msr & IA32_FEATURE_CONTROL_LOCK)) 922 ci->ci_vmm_flags |= CI_VMM_VMX; 923 else { 924 if (msr & IA32_FEATURE_CONTROL_VMX_EN) 925 ci->ci_vmm_flags |= CI_VMM_VMX; 926 else 927 ci->ci_vmm_flags |= CI_VMM_DIS; 928 } 929 } 930 931 /* 932 * Check for EPT (Intel Nested Paging) and other secondary 933 * controls 934 */ 935 if (ci->ci_vmm_flags & CI_VMM_VMX) { 936 /* Secondary controls available? */ 937 /* XXX should we check true procbased ctls here if avail? */ 938 msr = rdmsr(IA32_VMX_PROCBASED_CTLS); 939 if (msr & (IA32_VMX_ACTIVATE_SECONDARY_CONTROLS) << 32) { 940 msr = rdmsr(IA32_VMX_PROCBASED2_CTLS); 941 /* EPT available? */ 942 if (msr & (IA32_VMX_ENABLE_EPT) << 32) 943 ci->ci_vmm_flags |= CI_VMM_EPT; 944 /* VM Functions available? */ 945 if (msr & (IA32_VMX_ENABLE_VM_FUNCTIONS) << 32) { 946 ci->ci_vmm_cap.vcc_vmx.vmx_vm_func = 947 rdmsr(IA32_VMX_VMFUNC); 948 } 949 } 950 } 951 952 /* 953 * Check startup config (VMX) 954 */ 955 if (ci->ci_vmm_flags & CI_VMM_VMX) { 956 /* CR0 fixed and flexible bits */ 957 msr = rdmsr(IA32_VMX_CR0_FIXED0); 958 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed0 = msr; 959 msr = rdmsr(IA32_VMX_CR0_FIXED1); 960 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed1 = msr; 961 962 /* CR4 fixed and flexible bits */ 963 msr = rdmsr(IA32_VMX_CR4_FIXED0); 964 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed0 = msr; 965 msr = rdmsr(IA32_VMX_CR4_FIXED1); 966 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed1 = msr; 967 968 /* VMXON region revision ID (bits 30:0 of IA32_VMX_BASIC) */ 969 msr = rdmsr(IA32_VMX_BASIC); 970 ci->ci_vmm_cap.vcc_vmx.vmx_vmxon_revision = 971 (uint32_t)(msr & 0x7FFFFFFF); 972 973 /* MSR save / load table size */ 974 msr = rdmsr(IA32_VMX_MISC); 975 ci->ci_vmm_cap.vcc_vmx.vmx_msr_table_size = 976 (uint32_t)(msr & IA32_VMX_MSR_LIST_SIZE_MASK) >> 25; 977 978 /* CR3 target count size */ 979 ci->ci_vmm_cap.vcc_vmx.vmx_cr3_tgt_count = 980 (uint32_t)(msr & IA32_VMX_CR3_TGT_SIZE_MASK) >> 16; 981 } 982 983 /* 984 * Check for workable SVM 985 */ 986 if (ecpu_ecxfeature & CPUIDECX_SVM) { 987 msr = rdmsr(MSR_AMD_VM_CR); 988 989 if (!(msr & AMD_SVMDIS)) 990 ci->ci_vmm_flags |= CI_VMM_SVM; 991 992 CPUID(CPUID_AMD_SVM_CAP, dummy, 993 ci->ci_vmm_cap.vcc_svm.svm_max_asid, dummy, edx); 994 995 if (ci->ci_vmm_cap.vcc_svm.svm_max_asid > 0xFFF) 996 ci->ci_vmm_cap.vcc_svm.svm_max_asid = 0xFFF; 997 998 if (edx & AMD_SVM_FLUSH_BY_ASID_CAP) 999 ci->ci_vmm_cap.vcc_svm.svm_flush_by_asid = 1; 1000 1001 if (edx & AMD_SVM_VMCB_CLEAN_CAP) 1002 ci->ci_vmm_cap.vcc_svm.svm_vmcb_clean = 1; 1003 } 1004 1005 /* 1006 * Check for SVM Nested Paging 1007 */ 1008 if ((ci->ci_vmm_flags & CI_VMM_SVM) && 1009 ci->ci_pnfeatset >= CPUID_AMD_SVM_CAP) { 1010 CPUID(CPUID_AMD_SVM_CAP, dummy, dummy, dummy, cap); 1011 if (cap & AMD_SVM_NESTED_PAGING_CAP) 1012 ci->ci_vmm_flags |= CI_VMM_RVI; 1013 } 1014 1015 /* 1016 * Check "L1 flush on VM entry" (Intel L1TF vuln) semantics 1017 * Full details can be found here: 1018 * https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault 1019 */ 1020 if (!strcmp(cpu_vendor, "GenuineIntel")) { 1021 if (ci->ci_feature_sefflags_edx & SEFF0EDX_L1DF) 1022 ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr = 1; 1023 else 1024 ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr = 0; 1025 1026 /* 1027 * Certain CPUs may have the vulnerability remedied in 1028 * hardware (RDCL_NO), or we may be nested in an VMM that 1029 * is doing flushes (SKIP_L1DFL_VMENTRY) using the MSR. 1030 * In either case no mitigation at all is necessary. 1031 */ 1032 if (ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP) { 1033 msr = rdmsr(MSR_ARCH_CAPABILITIES); 1034 if ((msr & ARCH_CAPABILITIES_RDCL_NO) || 1035 ((msr & ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY) && 1036 ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr)) 1037 ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr = 1038 VMX_SKIP_L1D_FLUSH; 1039 } 1040 } 1041} 1042#endif /* NVMM > 0 */ 1043