identcpu.c revision 1.103
1/* $OpenBSD: identcpu.c,v 1.103 2018/07/23 23:25:02 brynet Exp $ */ 2/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ 3 4/* 5 * Copyright (c) 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Frank van der Linden for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/sysctl.h> 42 43#include "vmm.h" 44 45#include <machine/cpu.h> 46#include <machine/cpufunc.h> 47 48void replacesmap(void); 49void replacemeltdown(void); 50uint64_t cpu_freq(struct cpu_info *); 51void tsc_timecounter_init(struct cpu_info *, uint64_t); 52#if NVMM > 0 53void cpu_check_vmm_cap(struct cpu_info *); 54#endif /* NVMM > 0 */ 55 56/* sysctl wants this. */ 57char cpu_model[48]; 58int cpuspeed; 59 60int amd64_has_xcrypt; 61#ifdef CRYPTO 62int amd64_has_pclmul; 63int amd64_has_aesni; 64#endif 65int has_rdrand; 66int has_rdseed; 67 68#include "pvbus.h" 69#if NPVBUS > 0 70#include <dev/pv/pvvar.h> 71#endif 72 73const struct { 74 u_int32_t bit; 75 char str[12]; 76} cpu_cpuid_features[] = { 77 { CPUID_FPU, "FPU" }, 78 { CPUID_VME, "VME" }, 79 { CPUID_DE, "DE" }, 80 { CPUID_PSE, "PSE" }, 81 { CPUID_TSC, "TSC" }, 82 { CPUID_MSR, "MSR" }, 83 { CPUID_PAE, "PAE" }, 84 { CPUID_MCE, "MCE" }, 85 { CPUID_CX8, "CX8" }, 86 { CPUID_APIC, "APIC" }, 87 { CPUID_SEP, "SEP" }, 88 { CPUID_MTRR, "MTRR" }, 89 { CPUID_PGE, "PGE" }, 90 { CPUID_MCA, "MCA" }, 91 { CPUID_CMOV, "CMOV" }, 92 { CPUID_PAT, "PAT" }, 93 { CPUID_PSE36, "PSE36" }, 94 { CPUID_PSN, "PSN" }, 95 { CPUID_CFLUSH, "CFLUSH" }, 96 { CPUID_DS, "DS" }, 97 { CPUID_ACPI, "ACPI" }, 98 { CPUID_MMX, "MMX" }, 99 { CPUID_FXSR, "FXSR" }, 100 { CPUID_SSE, "SSE" }, 101 { CPUID_SSE2, "SSE2" }, 102 { CPUID_SS, "SS" }, 103 { CPUID_HTT, "HTT" }, 104 { CPUID_TM, "TM" }, 105 { CPUID_PBE, "PBE" } 106}, cpu_ecpuid_features[] = { 107 { CPUID_MPC, "MPC" }, 108 { CPUID_NXE, "NXE" }, 109 { CPUID_MMXX, "MMXX" }, 110 { CPUID_FFXSR, "FFXSR" }, 111 { CPUID_PAGE1GB, "PAGE1GB" }, 112 { CPUID_RDTSCP, "RDTSCP" }, 113 { CPUID_LONG, "LONG" }, 114 { CPUID_3DNOW2, "3DNOW2" }, 115 { CPUID_3DNOW, "3DNOW" } 116}, cpu_cpuid_ecxfeatures[] = { 117 { CPUIDECX_SSE3, "SSE3" }, 118 { CPUIDECX_PCLMUL, "PCLMUL" }, 119 { CPUIDECX_DTES64, "DTES64" }, 120 { CPUIDECX_MWAIT, "MWAIT" }, 121 { CPUIDECX_DSCPL, "DS-CPL" }, 122 { CPUIDECX_VMX, "VMX" }, 123 { CPUIDECX_SMX, "SMX" }, 124 { CPUIDECX_EST, "EST" }, 125 { CPUIDECX_TM2, "TM2" }, 126 { CPUIDECX_SSSE3, "SSSE3" }, 127 { CPUIDECX_CNXTID, "CNXT-ID" }, 128 { CPUIDECX_SDBG, "SDBG" }, 129 { CPUIDECX_FMA3, "FMA3" }, 130 { CPUIDECX_CX16, "CX16" }, 131 { CPUIDECX_XTPR, "xTPR" }, 132 { CPUIDECX_PDCM, "PDCM" }, 133 { CPUIDECX_PCID, "PCID" }, 134 { CPUIDECX_DCA, "DCA" }, 135 { CPUIDECX_SSE41, "SSE4.1" }, 136 { CPUIDECX_SSE42, "SSE4.2" }, 137 { CPUIDECX_X2APIC, "x2APIC" }, 138 { CPUIDECX_MOVBE, "MOVBE" }, 139 { CPUIDECX_POPCNT, "POPCNT" }, 140 { CPUIDECX_DEADLINE, "DEADLINE" }, 141 { CPUIDECX_AES, "AES" }, 142 { CPUIDECX_XSAVE, "XSAVE" }, 143 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 144 { CPUIDECX_AVX, "AVX" }, 145 { CPUIDECX_F16C, "F16C" }, 146 { CPUIDECX_RDRAND, "RDRAND" }, 147 { CPUIDECX_HV, "HV" }, 148}, cpu_ecpuid_ecxfeatures[] = { 149 { CPUIDECX_LAHF, "LAHF" }, 150 { CPUIDECX_CMPLEG, "CMPLEG" }, 151 { CPUIDECX_SVM, "SVM" }, 152 { CPUIDECX_EAPICSP, "EAPICSP"}, 153 { CPUIDECX_AMCR8, "AMCR8"}, 154 { CPUIDECX_ABM, "ABM" }, 155 { CPUIDECX_SSE4A, "SSE4A" }, 156 { CPUIDECX_MASSE, "MASSE" }, 157 { CPUIDECX_3DNOWP, "3DNOWP" }, 158 { CPUIDECX_OSVW, "OSVW" }, 159 { CPUIDECX_IBS, "IBS" }, 160 { CPUIDECX_XOP, "XOP" }, 161 { CPUIDECX_SKINIT, "SKINIT" }, 162 { CPUIDECX_LWP, "WDT" }, 163 { CPUIDECX_FMA4, "FMA4" }, 164 { CPUIDECX_TCE, "TCE" }, 165 { CPUIDECX_NODEID, "NODEID" }, 166 { CPUIDECX_TBM, "TBM" }, 167 { CPUIDECX_TOPEXT, "TOPEXT" }, 168 { CPUIDECX_CPCTR, "CPCTR" }, 169 { CPUIDECX_DBKP, "DBKP" }, 170 { CPUIDECX_PERFTSC, "PERFTSC" }, 171 { CPUIDECX_PCTRL3, "PCTRL3" }, 172 { CPUIDECX_MWAITX, "MWAITX" }, 173}, cpu_seff0_ebxfeatures[] = { 174 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 175 { SEFF0EBX_SGX, "SGX" }, 176 { SEFF0EBX_BMI1, "BMI1" }, 177 { SEFF0EBX_HLE, "HLE" }, 178 { SEFF0EBX_AVX2, "AVX2" }, 179 { SEFF0EBX_SMEP, "SMEP" }, 180 { SEFF0EBX_BMI2, "BMI2" }, 181 { SEFF0EBX_ERMS, "ERMS" }, 182 { SEFF0EBX_INVPCID, "INVPCID" }, 183 { SEFF0EBX_RTM, "RTM" }, 184 { SEFF0EBX_PQM, "PQM" }, 185 { SEFF0EBX_MPX, "MPX" }, 186 { SEFF0EBX_AVX512F, "AVX512F" }, 187 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 188 { SEFF0EBX_RDSEED, "RDSEED" }, 189 { SEFF0EBX_ADX, "ADX" }, 190 { SEFF0EBX_SMAP, "SMAP" }, 191 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 192 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 193 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 194 { SEFF0EBX_CLWB, "CLWB" }, 195 { SEFF0EBX_PT, "PT" }, 196 { SEFF0EBX_AVX512PF, "AVX512PF" }, 197 { SEFF0EBX_AVX512ER, "AVX512ER" }, 198 { SEFF0EBX_AVX512CD, "AVX512CD" }, 199 { SEFF0EBX_SHA, "SHA" }, 200 { SEFF0EBX_AVX512BW, "AVX512BW" }, 201 { SEFF0EBX_AVX512VL, "AVX512VL" }, 202}, cpu_seff0_ecxfeatures[] = { 203 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 204 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 205 { SEFF0ECX_UMIP, "UMIP" }, 206 { SEFF0ECX_PKU, "PKU" }, 207}, cpu_seff0_edxfeatures[] = { 208 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 209 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 210 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 211 { SEFF0EDX_STIBP, "STIBP" }, 212 /* SEFF0EDX_ARCH_CAP (not printed) */ 213}, cpu_tpm_eaxfeatures[] = { 214 { TPM_SENSOR, "SENSOR" }, 215 { TPM_ARAT, "ARAT" }, 216}, cpu_cpuid_perf_eax[] = { 217 { CPUIDEAX_VERID, "PERF" }, 218}, cpu_cpuid_apmi_edx[] = { 219 { CPUIDEDX_ITSC, "ITSC" }, 220}, cpu_amdspec_ebxfeatures[] = { 221 { CPUIDEBX_IBPB, "IBPB" }, 222 { CPUIDEBX_IBRS, "IBRS" }, 223 { CPUIDEBX_STIBP, "STIBP" }, 224 { CPUIDEBX_SSBD, "SSBD" }, 225 { CPUIDEBX_VIRT_SSBD, "VIRTSSBD" }, 226 { CPUIDEBX_SSBD_NOTREQ, "SSBDNR" }, 227}, cpu_xsave_extfeatures[] = { 228 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 229 { XSAVE_XSAVEC, "XSAVEC" }, 230 { XSAVE_XGETBV1, "XGETBV1" }, 231 { XSAVE_XSAVES, "XSAVES" }, 232}; 233 234int 235cpu_amd64speed(int *freq) 236{ 237 *freq = cpuspeed; 238 return (0); 239} 240 241#ifndef SMALL_KERNEL 242void intelcore_update_sensor(void *args); 243/* 244 * Temperature read on the CPU is relative to the maximum 245 * temperature supported by the CPU, Tj(Max). 246 * Refer to: 247 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 248 * Section 35 and 249 * http://www.intel.com/content/dam/www/public/us/en/documents/ 250 * white-papers/cpu-monitoring-dts-peci-paper.pdf 251 * 252 * The temperature on Intel CPUs can be between 70 and 105 degC, since 253 * Westmere we can read the TJmax from the die. For older CPUs we have 254 * to guess or use undocumented MSRs. Then we subtract the temperature 255 * portion of thermal status from max to get current temperature. 256 */ 257void 258intelcore_update_sensor(void *args) 259{ 260 struct cpu_info *ci = (struct cpu_info *) args; 261 u_int64_t msr; 262 int max = 100; 263 264 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 265 if (ci->ci_model == 0x0e && 266 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 267 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 268 max = 85; 269 270 /* 271 * Newer CPUs can tell you what their max temperature is. 272 * See: '64-ia-32-architectures-software-developer- 273 * vol-3c-part-3-manual.pdf' 274 */ 275 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 276 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 277 ci->ci_model != 0x35 && ci->ci_model != 0x36) 278 max = MSR_TEMPERATURE_TARGET_TJMAX( 279 rdmsr(MSR_TEMPERATURE_TARGET)); 280 281 msr = rdmsr(MSR_THERM_STATUS); 282 if (msr & MSR_THERM_STATUS_VALID_BIT) { 283 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 284 /* micro degrees */ 285 ci->ci_sensor.value *= 1000000; 286 /* kelvin */ 287 ci->ci_sensor.value += 273150000; 288 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 289 } else { 290 ci->ci_sensor.value = 0; 291 ci->ci_sensor.flags |= SENSOR_FINVALID; 292 } 293} 294 295#endif 296 297void (*setperf_setup)(struct cpu_info *); 298 299void via_nano_setup(struct cpu_info *ci); 300 301void cpu_topology(struct cpu_info *ci); 302 303void 304via_nano_setup(struct cpu_info *ci) 305{ 306 u_int32_t regs[4], val; 307 u_int64_t msreg; 308 int model = (ci->ci_signature >> 4) & 15; 309 310 if (model >= 9) { 311 CPUID(0xC0000000, regs[0], regs[1], regs[2], regs[3]); 312 val = regs[0]; 313 if (val >= 0xC0000001) { 314 CPUID(0xC0000001, regs[0], regs[1], regs[2], regs[3]); 315 val = regs[3]; 316 } else 317 val = 0; 318 319 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 320 printf("%s:", ci->ci_dev->dv_xname); 321 322 /* Enable RNG if present and disabled */ 323 if (val & C3_CPUID_HAS_RNG) { 324 extern int viac3_rnd_present; 325 326 if (!(val & C3_CPUID_DO_RNG)) { 327 msreg = rdmsr(0x110B); 328 msreg |= 0x40; 329 wrmsr(0x110B, msreg); 330 } 331 viac3_rnd_present = 1; 332 printf(" RNG"); 333 } 334 335 /* Enable AES engine if present and disabled */ 336 if (val & C3_CPUID_HAS_ACE) { 337#ifdef CRYPTO 338 if (!(val & C3_CPUID_DO_ACE)) { 339 msreg = rdmsr(0x1107); 340 msreg |= (0x01 << 28); 341 wrmsr(0x1107, msreg); 342 } 343 amd64_has_xcrypt |= C3_HAS_AES; 344#endif /* CRYPTO */ 345 printf(" AES"); 346 } 347 348 /* Enable ACE2 engine if present and disabled */ 349 if (val & C3_CPUID_HAS_ACE2) { 350#ifdef CRYPTO 351 if (!(val & C3_CPUID_DO_ACE2)) { 352 msreg = rdmsr(0x1107); 353 msreg |= (0x01 << 28); 354 wrmsr(0x1107, msreg); 355 } 356 amd64_has_xcrypt |= C3_HAS_AESCTR; 357#endif /* CRYPTO */ 358 printf(" AES-CTR"); 359 } 360 361 /* Enable SHA engine if present and disabled */ 362 if (val & C3_CPUID_HAS_PHE) { 363#ifdef CRYPTO 364 if (!(val & C3_CPUID_DO_PHE)) { 365 msreg = rdmsr(0x1107); 366 msreg |= (0x01 << 28/**/); 367 wrmsr(0x1107, msreg); 368 } 369 amd64_has_xcrypt |= C3_HAS_SHA; 370#endif /* CRYPTO */ 371 printf(" SHA1 SHA256"); 372 } 373 374 /* Enable MM engine if present and disabled */ 375 if (val & C3_CPUID_HAS_PMM) { 376#ifdef CRYPTO 377 if (!(val & C3_CPUID_DO_PMM)) { 378 msreg = rdmsr(0x1107); 379 msreg |= (0x01 << 28/**/); 380 wrmsr(0x1107, msreg); 381 } 382 amd64_has_xcrypt |= C3_HAS_MM; 383#endif /* CRYPTO */ 384 printf(" RSA"); 385 } 386 387 printf("\n"); 388 } 389} 390 391#ifndef SMALL_KERNEL 392void via_update_sensor(void *args); 393void 394via_update_sensor(void *args) 395{ 396 struct cpu_info *ci = (struct cpu_info *) args; 397 u_int64_t msr; 398 399 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 400 ci->ci_sensor.value = (msr & 0xffffff); 401 /* micro degrees */ 402 ci->ci_sensor.value *= 1000000; 403 ci->ci_sensor.value += 273150000; 404 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 405} 406#endif 407 408uint64_t 409cpu_freq_ctr(struct cpu_info *ci) 410{ 411 uint64_t count, last_count, msr; 412 413 if ((ci->ci_flags & CPUF_CONST_TSC) == 0 || 414 (cpu_perf_eax & CPUIDEAX_VERID) <= 1 || 415 CPUIDEDX_NUM_FC(cpu_perf_edx) <= 1) 416 return (0); 417 418 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 419 if (msr & MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK)) { 420 /* some hypervisor is dicking us around */ 421 return (0); 422 } 423 424 msr |= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_1); 425 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 426 427 msr = rdmsr(MSR_PERF_GLOBAL_CTRL) | MSR_PERF_GLOBAL_CTR1_EN; 428 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 429 430 last_count = rdmsr(MSR_PERF_FIXED_CTR1); 431 delay(100000); 432 count = rdmsr(MSR_PERF_FIXED_CTR1); 433 434 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 435 msr &= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK); 436 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 437 438 msr = rdmsr(MSR_PERF_GLOBAL_CTRL); 439 msr &= ~MSR_PERF_GLOBAL_CTR1_EN; 440 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 441 442 return ((count - last_count) * 10); 443} 444 445uint64_t 446cpu_freq(struct cpu_info *ci) 447{ 448 uint64_t last_count, count; 449 450 count = cpu_freq_ctr(ci); 451 if (count != 0) 452 return (count); 453 454 last_count = rdtsc(); 455 delay(100000); 456 count = rdtsc(); 457 458 return ((count - last_count) * 10); 459} 460 461void 462identifycpu(struct cpu_info *ci) 463{ 464 uint64_t freq = 0; 465 u_int32_t dummy, val; 466 char mycpu_model[48]; 467 int i; 468 char *brandstr_from, *brandstr_to; 469 int skipspace; 470 471 CPUID(1, ci->ci_signature, val, dummy, ci->ci_feature_flags); 472 CPUID(0x80000000, ci->ci_pnfeatset, dummy, dummy, dummy); 473 if (ci->ci_pnfeatset >= 0x80000001) { 474 CPUID(0x80000001, ci->ci_efeature_eax, dummy, 475 ci->ci_efeature_ecx, ci->ci_feature_eflags); 476 /* Other bits may clash */ 477 ci->ci_feature_flags |= (ci->ci_feature_eflags & CPUID_NXE); 478 if (ci->ci_flags & CPUF_PRIMARY) 479 ecpu_ecxfeature = ci->ci_efeature_ecx; 480 /* Let cpu_feature be the common bits */ 481 cpu_feature &= ci->ci_feature_flags; 482 } 483 484 CPUID(0x80000002, ci->ci_brand[0], 485 ci->ci_brand[1], ci->ci_brand[2], ci->ci_brand[3]); 486 CPUID(0x80000003, ci->ci_brand[4], 487 ci->ci_brand[5], ci->ci_brand[6], ci->ci_brand[7]); 488 CPUID(0x80000004, ci->ci_brand[8], 489 ci->ci_brand[9], ci->ci_brand[10], ci->ci_brand[11]); 490 strlcpy(mycpu_model, (char *)ci->ci_brand, sizeof(mycpu_model)); 491 492 /* Remove leading, trailing and duplicated spaces from mycpu_model */ 493 brandstr_from = brandstr_to = mycpu_model; 494 skipspace = 1; 495 while (*brandstr_from != '\0') { 496 if (!skipspace || *brandstr_from != ' ') { 497 skipspace = 0; 498 *(brandstr_to++) = *brandstr_from; 499 } 500 if (*brandstr_from == ' ') 501 skipspace = 1; 502 brandstr_from++; 503 } 504 if (skipspace && brandstr_to > mycpu_model) 505 brandstr_to--; 506 *brandstr_to = '\0'; 507 508 if (mycpu_model[0] == 0) 509 strlcpy(mycpu_model, "Opteron or Athlon 64", 510 sizeof(mycpu_model)); 511 512 /* If primary cpu, fill in the global cpu_model used by sysctl */ 513 if (ci->ci_flags & CPUF_PRIMARY) 514 strlcpy(cpu_model, mycpu_model, sizeof(cpu_model)); 515 516 ci->ci_family = (ci->ci_signature >> 8) & 0x0f; 517 ci->ci_model = (ci->ci_signature >> 4) & 0x0f; 518 if (ci->ci_family == 0x6 || ci->ci_family == 0xf) { 519 ci->ci_family += (ci->ci_signature >> 20) & 0xff; 520 ci->ci_model += ((ci->ci_signature >> 16) & 0x0f) << 4; 521 } 522 523 if (ci->ci_feature_flags && ci->ci_feature_flags & CPUID_TSC) { 524 /* Has TSC, check if it's constant */ 525 if (!strcmp(cpu_vendor, "GenuineIntel")) { 526 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 527 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 528 ci->ci_flags |= CPUF_CONST_TSC; 529 } 530 } else if (!strcmp(cpu_vendor, "CentaurHauls")) { 531 /* VIA */ 532 if (ci->ci_model >= 0x0f) { 533 ci->ci_flags |= CPUF_CONST_TSC; 534 } 535 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 536 if (cpu_apmi_edx & CPUIDEDX_ITSC) { 537 /* Invariant TSC indicates constant TSC on 538 * AMD. 539 */ 540 ci->ci_flags |= CPUF_CONST_TSC; 541 } 542 } 543 544 /* Check if it's an invariant TSC */ 545 if (cpu_apmi_edx & CPUIDEDX_ITSC) 546 ci->ci_flags |= CPUF_INVAR_TSC; 547 } 548 549 freq = cpu_freq(ci); 550 551 amd_cpu_cacheinfo(ci); 552 553 printf("%s: %s", ci->ci_dev->dv_xname, mycpu_model); 554 555 if (freq != 0) 556 printf(", %llu.%02llu MHz", (freq + 4999) / 1000000, 557 ((freq + 4999) / 10000) % 100); 558 559 if (ci->ci_flags & CPUF_PRIMARY) { 560 cpuspeed = (freq + 4999) / 1000000; 561 cpu_cpuspeed = cpu_amd64speed; 562 } 563 564 printf("\n%s: ", ci->ci_dev->dv_xname); 565 566 for (i = 0; i < nitems(cpu_cpuid_features); i++) 567 if (ci->ci_feature_flags & cpu_cpuid_features[i].bit) 568 printf("%s%s", i? "," : "", cpu_cpuid_features[i].str); 569 for (i = 0; i < nitems(cpu_cpuid_ecxfeatures); i++) 570 if (cpu_ecxfeature & cpu_cpuid_ecxfeatures[i].bit) 571 printf(",%s", cpu_cpuid_ecxfeatures[i].str); 572 for (i = 0; i < nitems(cpu_ecpuid_features); i++) 573 if (ci->ci_feature_eflags & cpu_ecpuid_features[i].bit) 574 printf(",%s", cpu_ecpuid_features[i].str); 575 for (i = 0; i < nitems(cpu_ecpuid_ecxfeatures); i++) 576 if (ecpu_ecxfeature & cpu_ecpuid_ecxfeatures[i].bit) 577 printf(",%s", cpu_ecpuid_ecxfeatures[i].str); 578 for (i = 0; i < nitems(cpu_cpuid_perf_eax); i++) 579 if (cpu_perf_eax & cpu_cpuid_perf_eax[i].bit) 580 printf(",%s", cpu_cpuid_perf_eax[i].str); 581 for (i = 0; i < nitems(cpu_cpuid_apmi_edx); i++) 582 if (cpu_apmi_edx & cpu_cpuid_apmi_edx[i].bit) 583 printf(",%s", cpu_cpuid_apmi_edx[i].str); 584 585 if (cpuid_level >= 0x07) { 586 /* "Structured Extended Feature Flags" */ 587 CPUID_LEAF(0x7, 0, dummy, ci->ci_feature_sefflags_ebx, 588 ci->ci_feature_sefflags_ecx, ci->ci_feature_sefflags_edx); 589 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 590 if (ci->ci_feature_sefflags_ebx & 591 cpu_seff0_ebxfeatures[i].bit) 592 printf(",%s", cpu_seff0_ebxfeatures[i].str); 593 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 594 if (ci->ci_feature_sefflags_ecx & 595 cpu_seff0_ecxfeatures[i].bit) 596 printf(",%s", cpu_seff0_ecxfeatures[i].str); 597 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 598 if (ci->ci_feature_sefflags_edx & 599 cpu_seff0_edxfeatures[i].bit) 600 printf(",%s", cpu_seff0_edxfeatures[i].str); 601 } 602 603 if (!strcmp(cpu_vendor, "GenuineIntel") && cpuid_level >= 0x06) { 604 CPUID(0x06, ci->ci_feature_tpmflags, dummy, dummy, dummy); 605 for (i = 0; i < nitems(cpu_tpm_eaxfeatures); i++) 606 if (ci->ci_feature_tpmflags & 607 cpu_tpm_eaxfeatures[i].bit) 608 printf(",%s", cpu_tpm_eaxfeatures[i].str); 609 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 610 if (ci->ci_family >= 0x12) 611 ci->ci_feature_tpmflags |= TPM_ARAT; 612 } 613 614 /* AMD speculation control features */ 615 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 616 if (ci->ci_pnfeatset >= 0x80000008) { 617 CPUID(0x80000008, dummy, ci->ci_feature_amdspec_ebx, 618 dummy, dummy); 619 for (i = 0; i < nitems(cpu_amdspec_ebxfeatures); i++) 620 if (ci->ci_feature_amdspec_ebx & 621 cpu_amdspec_ebxfeatures[i].bit) 622 printf(",%s", 623 cpu_amdspec_ebxfeatures[i].str); 624 } 625 } 626 627 /* xsave subfeatures */ 628 if (cpuid_level >= 0xd) { 629 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 630 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 631 if (val & cpu_xsave_extfeatures[i].bit) 632 printf(",%s", cpu_xsave_extfeatures[i].str); 633 } 634 635 if (cpu_meltdown) 636 printf(",MELTDOWN"); 637 else 638 replacemeltdown(); 639 640 printf("\n"); 641 642 x86_print_cacheinfo(ci); 643 644 /* 645 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 646 * for Managing Speculation on AMD Processors" 647 * 648 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 649 * serializing instruction. 650 * 651 * This MSR is available on all AMD families >= 10h, except 11h 652 * where LFENCE is always serializing. 653 */ 654 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 655 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 656 uint64_t msr; 657 658 msr = rdmsr(MSR_DE_CFG); 659 msr |= DE_CFG_SERIALIZE_LFENCE; 660 wrmsr(MSR_DE_CFG, msr); 661 } 662 } 663 664 /* 665 * Attempt to disable Silicon Debug and lock the configuration 666 * if it's enabled and unlocked. 667 */ 668 if (!strcmp(cpu_vendor, "GenuineIntel") && 669 (cpu_ecxfeature & CPUIDECX_SDBG)) { 670 uint64_t msr; 671 672 msr = rdmsr(IA32_DEBUG_INTERFACE); 673 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 674 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 675 msr &= IA32_DEBUG_INTERFACE_MASK; 676 msr |= IA32_DEBUG_INTERFACE_LOCK; 677 wrmsr(IA32_DEBUG_INTERFACE, msr); 678 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 679 printf("%s: cannot disable silicon debug\n", 680 ci->ci_dev->dv_xname); 681 } 682 683 if (ci->ci_flags & CPUF_PRIMARY) { 684#ifndef SMALL_KERNEL 685 if (!strcmp(cpu_vendor, "AuthenticAMD") && 686 ci->ci_pnfeatset >= 0x80000007) { 687 CPUID(0x80000007, dummy, dummy, dummy, val); 688 689 if (val & 0x06) { 690 if ((ci->ci_signature & 0xF00) == 0xF00) 691 setperf_setup = k8_powernow_init; 692 } 693 if (ci->ci_family >= 0x10) 694 setperf_setup = k1x_init; 695 } 696 697 if (cpu_ecxfeature & CPUIDECX_EST) 698 setperf_setup = est_init; 699#endif 700 701 if (cpu_ecxfeature & CPUIDECX_RDRAND) 702 has_rdrand = 1; 703 704 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 705 has_rdseed = 1; 706 707 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 708 replacesmap(); 709 } 710#ifndef SMALL_KERNEL 711 if (!strncmp(mycpu_model, "Intel", 5)) { 712 u_int32_t cflushsz; 713 714 CPUID(0x01, dummy, cflushsz, dummy, dummy); 715 /* cflush cacheline size is equal to bits 15-8 of ebx * 8 */ 716 ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8; 717 } 718 719 if (CPU_IS_PRIMARY(ci) && (ci->ci_feature_tpmflags & TPM_SENSOR)) { 720 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 721 sizeof(ci->ci_sensordev.xname)); 722 ci->ci_sensor.type = SENSOR_TEMP; 723 sensor_task_register(ci, intelcore_update_sensor, 5); 724 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 725 sensordev_install(&ci->ci_sensordev); 726 } 727#endif 728 729#ifdef CRYPTO 730 if (ci->ci_flags & CPUF_PRIMARY) { 731 if (cpu_ecxfeature & CPUIDECX_PCLMUL) 732 amd64_has_pclmul = 1; 733 734 if (cpu_ecxfeature & CPUIDECX_AES) 735 amd64_has_aesni = 1; 736 } 737#endif 738 739 if (!strcmp(cpu_vendor, "AuthenticAMD")) 740 amd64_errata(ci); 741 742 if (CPU_IS_PRIMARY(ci) && !strcmp(cpu_vendor, "CentaurHauls")) { 743 ci->cpu_setup = via_nano_setup; 744#ifndef SMALL_KERNEL 745 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 746 sizeof(ci->ci_sensordev.xname)); 747 ci->ci_sensor.type = SENSOR_TEMP; 748 sensor_task_register(ci, via_update_sensor, 5); 749 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 750 sensordev_install(&ci->ci_sensordev); 751#endif 752 } 753 754 tsc_timecounter_init(ci, freq); 755 756 cpu_topology(ci); 757#if NVMM > 0 758 cpu_check_vmm_cap(ci); 759#endif /* NVMM > 0 */ 760} 761 762#ifndef SMALL_KERNEL 763/* 764 * Base 2 logarithm of an int. returns 0 for 0 (yeye, I know). 765 */ 766static int 767log2(unsigned int i) 768{ 769 int ret = 0; 770 771 while (i >>= 1) 772 ret++; 773 774 return (ret); 775} 776 777static int 778mask_width(u_int x) 779{ 780 int bit; 781 int mask; 782 int powerof2; 783 784 powerof2 = ((x - 1) & x) == 0; 785 mask = (x << (1 - powerof2)) - 1; 786 787 /* fls */ 788 if (mask == 0) 789 return (0); 790 for (bit = 1; mask != 1; bit++) 791 mask = (unsigned int)mask >> 1; 792 793 return (bit); 794} 795#endif 796 797/* 798 * Build up cpu topology for given cpu, must run on the core itself. 799 */ 800void 801cpu_topology(struct cpu_info *ci) 802{ 803#ifndef SMALL_KERNEL 804 u_int32_t eax, ebx, ecx, edx; 805 u_int32_t apicid, max_apicid = 0, max_coreid = 0; 806 u_int32_t smt_bits = 0, core_bits, pkg_bits = 0; 807 u_int32_t smt_mask = 0, core_mask, pkg_mask = 0; 808 809 /* We need at least apicid at CPUID 1 */ 810 if (cpuid_level < 1) 811 goto no_topology; 812 813 /* Initial apicid */ 814 CPUID(1, eax, ebx, ecx, edx); 815 apicid = (ebx >> 24) & 0xff; 816 817 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 818 /* We need at least apicid at CPUID 0x80000008 */ 819 if (ci->ci_pnfeatset < 0x80000008) 820 goto no_topology; 821 822 if (ci->ci_pnfeatset >= 0x8000001e) { 823 struct cpu_info *ci_other; 824 CPU_INFO_ITERATOR cii; 825 826 CPUID(0x8000001e, eax, ebx, ecx, edx); 827 ci->ci_core_id = ebx & 0xff; 828 ci->ci_pkg_id = ecx & 0xff; 829 ci->ci_smt_id = 0; 830 CPU_INFO_FOREACH(cii, ci_other) { 831 if (ci != ci_other && 832 ci_other->ci_core_id == ci->ci_core_id) 833 ci->ci_smt_id++; 834 } 835 } else { 836 CPUID(0x80000008, eax, ebx, ecx, edx); 837 core_bits = (ecx >> 12) & 0xf; 838 if (core_bits == 0) 839 goto no_topology; 840 /* So coreidsize 2 gives 3, 3 gives 7... */ 841 core_mask = (1 << core_bits) - 1; 842 /* Core id is the least significant considering mask */ 843 ci->ci_core_id = apicid & core_mask; 844 /* Pkg id is the upper remaining bits */ 845 ci->ci_pkg_id = apicid & ~core_mask; 846 ci->ci_pkg_id >>= core_bits; 847 } 848 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 849 /* We only support leaf 1/4 detection */ 850 if (cpuid_level < 4) 851 goto no_topology; 852 /* Get max_apicid */ 853 CPUID(1, eax, ebx, ecx, edx); 854 max_apicid = (ebx >> 16) & 0xff; 855 /* Get max_coreid */ 856 CPUID_LEAF(4, 0, eax, ebx, ecx, edx); 857 max_coreid = ((eax >> 26) & 0x3f) + 1; 858 /* SMT */ 859 smt_bits = mask_width(max_apicid / max_coreid); 860 smt_mask = (1 << smt_bits) - 1; 861 /* Core */ 862 core_bits = log2(max_coreid); 863 core_mask = (1 << (core_bits + smt_bits)) - 1; 864 core_mask ^= smt_mask; 865 /* Pkg */ 866 pkg_bits = core_bits + smt_bits; 867 pkg_mask = -1 << core_bits; 868 869 ci->ci_smt_id = apicid & smt_mask; 870 ci->ci_core_id = (apicid & core_mask) >> smt_bits; 871 ci->ci_pkg_id = (apicid & pkg_mask) >> pkg_bits; 872 } else 873 goto no_topology; 874#ifdef DEBUG 875 printf("cpu%d: smt %u, core %u, pkg %u " 876 "(apicid 0x%x, max_apicid 0x%x, max_coreid 0x%x, smt_bits 0x%x, smt_mask 0x%x, " 877 "core_bits 0x%x, core_mask 0x%x, pkg_bits 0x%x, pkg_mask 0x%x)\n", 878 ci->ci_cpuid, ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id, 879 apicid, max_apicid, max_coreid, smt_bits, smt_mask, core_bits, 880 core_mask, pkg_bits, pkg_mask); 881#else 882 printf("cpu%d: smt %u, core %u, package %u\n", ci->ci_cpuid, 883 ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id); 884 885#endif 886 return; 887 /* We can't map, so consider ci_core_id as ci_cpuid */ 888no_topology: 889#endif 890 ci->ci_smt_id = 0; 891 ci->ci_core_id = ci->ci_cpuid; 892 ci->ci_pkg_id = 0; 893} 894 895#if NVMM > 0 896/* 897 * cpu_check_vmm_cap 898 * 899 * Checks for VMM capabilities for 'ci'. Initializes certain per-cpu VMM 900 * state in 'ci' if virtualization extensions are found. 901 * 902 * Parameters: 903 * ci: the cpu being checked 904 */ 905void 906cpu_check_vmm_cap(struct cpu_info *ci) 907{ 908 uint64_t msr; 909 uint32_t cap, dummy, edx; 910 911 /* 912 * Check for workable VMX 913 */ 914 if (cpu_ecxfeature & CPUIDECX_VMX) { 915 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 916 917 if (!(msr & IA32_FEATURE_CONTROL_LOCK)) 918 ci->ci_vmm_flags |= CI_VMM_VMX; 919 else { 920 if (msr & IA32_FEATURE_CONTROL_VMX_EN) 921 ci->ci_vmm_flags |= CI_VMM_VMX; 922 else 923 ci->ci_vmm_flags |= CI_VMM_DIS; 924 } 925 } 926 927 /* 928 * Check for EPT (Intel Nested Paging) and other secondary 929 * controls 930 */ 931 if (ci->ci_vmm_flags & CI_VMM_VMX) { 932 /* Secondary controls available? */ 933 /* XXX should we check true procbased ctls here if avail? */ 934 msr = rdmsr(IA32_VMX_PROCBASED_CTLS); 935 if (msr & (IA32_VMX_ACTIVATE_SECONDARY_CONTROLS) << 32) { 936 msr = rdmsr(IA32_VMX_PROCBASED2_CTLS); 937 /* EPT available? */ 938 if (msr & (IA32_VMX_ENABLE_EPT) << 32) 939 ci->ci_vmm_flags |= CI_VMM_EPT; 940 /* VM Functions available? */ 941 if (msr & (IA32_VMX_ENABLE_VM_FUNCTIONS) << 32) { 942 ci->ci_vmm_cap.vcc_vmx.vmx_vm_func = 943 rdmsr(IA32_VMX_VMFUNC); 944 } 945 } 946 } 947 948 /* 949 * Check startup config (VMX) 950 */ 951 if (ci->ci_vmm_flags & CI_VMM_VMX) { 952 /* CR0 fixed and flexible bits */ 953 msr = rdmsr(IA32_VMX_CR0_FIXED0); 954 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed0 = msr; 955 msr = rdmsr(IA32_VMX_CR0_FIXED1); 956 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed1 = msr; 957 958 /* CR4 fixed and flexible bits */ 959 msr = rdmsr(IA32_VMX_CR4_FIXED0); 960 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed0 = msr; 961 msr = rdmsr(IA32_VMX_CR4_FIXED1); 962 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed1 = msr; 963 964 /* VMXON region revision ID (bits 30:0 of IA32_VMX_BASIC) */ 965 msr = rdmsr(IA32_VMX_BASIC); 966 ci->ci_vmm_cap.vcc_vmx.vmx_vmxon_revision = 967 (uint32_t)(msr & 0x7FFFFFFF); 968 969 /* MSR save / load table size */ 970 msr = rdmsr(IA32_VMX_MISC); 971 ci->ci_vmm_cap.vcc_vmx.vmx_msr_table_size = 972 (uint32_t)(msr & IA32_VMX_MSR_LIST_SIZE_MASK) >> 25; 973 974 /* CR3 target count size */ 975 ci->ci_vmm_cap.vcc_vmx.vmx_cr3_tgt_count = 976 (uint32_t)(msr & IA32_VMX_CR3_TGT_SIZE_MASK) >> 16; 977 } 978 979 /* 980 * Check for workable SVM 981 */ 982 if (ecpu_ecxfeature & CPUIDECX_SVM) { 983 msr = rdmsr(MSR_AMD_VM_CR); 984 985 if (!(msr & AMD_SVMDIS)) 986 ci->ci_vmm_flags |= CI_VMM_SVM; 987 988 CPUID(CPUID_AMD_SVM_CAP, dummy, 989 ci->ci_vmm_cap.vcc_svm.svm_max_asid, dummy, edx); 990 991 if (ci->ci_vmm_cap.vcc_svm.svm_max_asid > 0xFFF) 992 ci->ci_vmm_cap.vcc_svm.svm_max_asid = 0xFFF; 993 994 if (edx & AMD_SVM_FLUSH_BY_ASID_CAP) 995 ci->ci_vmm_cap.vcc_svm.svm_flush_by_asid = 1; 996 997 if (edx & AMD_SVM_VMCB_CLEAN_CAP) 998 ci->ci_vmm_cap.vcc_svm.svm_vmcb_clean = 1; 999 } 1000 1001 /* 1002 * Check for SVM Nested Paging 1003 */ 1004 if ((ci->ci_vmm_flags & CI_VMM_SVM) && 1005 ci->ci_pnfeatset >= CPUID_AMD_SVM_CAP) { 1006 CPUID(CPUID_AMD_SVM_CAP, dummy, dummy, dummy, cap); 1007 if (cap & AMD_SVM_NESTED_PAGING_CAP) 1008 ci->ci_vmm_flags |= CI_VMM_RVI; 1009 } 1010} 1011#endif /* NVMM > 0 */ 1012