identcpu.c revision 1.101
1/* $OpenBSD: identcpu.c,v 1.101 2018/07/11 20:07:55 guenther Exp $ */ 2/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ 3 4/* 5 * Copyright (c) 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Frank van der Linden for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/sysctl.h> 42 43#include "vmm.h" 44 45#include <machine/cpu.h> 46#include <machine/cpufunc.h> 47 48void replacesmap(void); 49uint64_t cpu_freq(struct cpu_info *); 50void tsc_timecounter_init(struct cpu_info *, uint64_t); 51#if NVMM > 0 52void cpu_check_vmm_cap(struct cpu_info *); 53#endif /* NVMM > 0 */ 54 55/* sysctl wants this. */ 56char cpu_model[48]; 57int cpuspeed; 58 59int amd64_has_xcrypt; 60#ifdef CRYPTO 61int amd64_has_pclmul; 62int amd64_has_aesni; 63#endif 64int has_rdrand; 65int has_rdseed; 66 67#include "pvbus.h" 68#if NPVBUS > 0 69#include <dev/pv/pvvar.h> 70#endif 71 72const struct { 73 u_int32_t bit; 74 char str[12]; 75} cpu_cpuid_features[] = { 76 { CPUID_FPU, "FPU" }, 77 { CPUID_VME, "VME" }, 78 { CPUID_DE, "DE" }, 79 { CPUID_PSE, "PSE" }, 80 { CPUID_TSC, "TSC" }, 81 { CPUID_MSR, "MSR" }, 82 { CPUID_PAE, "PAE" }, 83 { CPUID_MCE, "MCE" }, 84 { CPUID_CX8, "CX8" }, 85 { CPUID_APIC, "APIC" }, 86 { CPUID_SEP, "SEP" }, 87 { CPUID_MTRR, "MTRR" }, 88 { CPUID_PGE, "PGE" }, 89 { CPUID_MCA, "MCA" }, 90 { CPUID_CMOV, "CMOV" }, 91 { CPUID_PAT, "PAT" }, 92 { CPUID_PSE36, "PSE36" }, 93 { CPUID_PSN, "PSN" }, 94 { CPUID_CFLUSH, "CFLUSH" }, 95 { CPUID_DS, "DS" }, 96 { CPUID_ACPI, "ACPI" }, 97 { CPUID_MMX, "MMX" }, 98 { CPUID_FXSR, "FXSR" }, 99 { CPUID_SSE, "SSE" }, 100 { CPUID_SSE2, "SSE2" }, 101 { CPUID_SS, "SS" }, 102 { CPUID_HTT, "HTT" }, 103 { CPUID_TM, "TM" }, 104 { CPUID_PBE, "PBE" } 105}, cpu_ecpuid_features[] = { 106 { CPUID_MPC, "MPC" }, 107 { CPUID_NXE, "NXE" }, 108 { CPUID_MMXX, "MMXX" }, 109 { CPUID_FFXSR, "FFXSR" }, 110 { CPUID_PAGE1GB, "PAGE1GB" }, 111 { CPUID_RDTSCP, "RDTSCP" }, 112 { CPUID_LONG, "LONG" }, 113 { CPUID_3DNOW2, "3DNOW2" }, 114 { CPUID_3DNOW, "3DNOW" } 115}, cpu_cpuid_ecxfeatures[] = { 116 { CPUIDECX_SSE3, "SSE3" }, 117 { CPUIDECX_PCLMUL, "PCLMUL" }, 118 { CPUIDECX_DTES64, "DTES64" }, 119 { CPUIDECX_MWAIT, "MWAIT" }, 120 { CPUIDECX_DSCPL, "DS-CPL" }, 121 { CPUIDECX_VMX, "VMX" }, 122 { CPUIDECX_SMX, "SMX" }, 123 { CPUIDECX_EST, "EST" }, 124 { CPUIDECX_TM2, "TM2" }, 125 { CPUIDECX_SSSE3, "SSSE3" }, 126 { CPUIDECX_CNXTID, "CNXT-ID" }, 127 { CPUIDECX_SDBG, "SDBG" }, 128 { CPUIDECX_FMA3, "FMA3" }, 129 { CPUIDECX_CX16, "CX16" }, 130 { CPUIDECX_XTPR, "xTPR" }, 131 { CPUIDECX_PDCM, "PDCM" }, 132 { CPUIDECX_PCID, "PCID" }, 133 { CPUIDECX_DCA, "DCA" }, 134 { CPUIDECX_SSE41, "SSE4.1" }, 135 { CPUIDECX_SSE42, "SSE4.2" }, 136 { CPUIDECX_X2APIC, "x2APIC" }, 137 { CPUIDECX_MOVBE, "MOVBE" }, 138 { CPUIDECX_POPCNT, "POPCNT" }, 139 { CPUIDECX_DEADLINE, "DEADLINE" }, 140 { CPUIDECX_AES, "AES" }, 141 { CPUIDECX_XSAVE, "XSAVE" }, 142 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 143 { CPUIDECX_AVX, "AVX" }, 144 { CPUIDECX_F16C, "F16C" }, 145 { CPUIDECX_RDRAND, "RDRAND" }, 146 { CPUIDECX_HV, "HV" }, 147}, cpu_ecpuid_ecxfeatures[] = { 148 { CPUIDECX_LAHF, "LAHF" }, 149 { CPUIDECX_CMPLEG, "CMPLEG" }, 150 { CPUIDECX_SVM, "SVM" }, 151 { CPUIDECX_EAPICSP, "EAPICSP"}, 152 { CPUIDECX_AMCR8, "AMCR8"}, 153 { CPUIDECX_ABM, "ABM" }, 154 { CPUIDECX_SSE4A, "SSE4A" }, 155 { CPUIDECX_MASSE, "MASSE" }, 156 { CPUIDECX_3DNOWP, "3DNOWP" }, 157 { CPUIDECX_OSVW, "OSVW" }, 158 { CPUIDECX_IBS, "IBS" }, 159 { CPUIDECX_XOP, "XOP" }, 160 { CPUIDECX_SKINIT, "SKINIT" }, 161 { CPUIDECX_LWP, "WDT" }, 162 { CPUIDECX_FMA4, "FMA4" }, 163 { CPUIDECX_TCE, "TCE" }, 164 { CPUIDECX_NODEID, "NODEID" }, 165 { CPUIDECX_TBM, "TBM" }, 166 { CPUIDECX_TOPEXT, "TOPEXT" }, 167 { CPUIDECX_CPCTR, "CPCTR" }, 168 { CPUIDECX_DBKP, "DBKP" }, 169 { CPUIDECX_PERFTSC, "PERFTSC" }, 170 { CPUIDECX_PCTRL3, "PCTRL3" }, 171 { CPUIDECX_MWAITX, "MWAITX" }, 172}, cpu_seff0_ebxfeatures[] = { 173 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 174 { SEFF0EBX_SGX, "SGX" }, 175 { SEFF0EBX_BMI1, "BMI1" }, 176 { SEFF0EBX_HLE, "HLE" }, 177 { SEFF0EBX_AVX2, "AVX2" }, 178 { SEFF0EBX_SMEP, "SMEP" }, 179 { SEFF0EBX_BMI2, "BMI2" }, 180 { SEFF0EBX_ERMS, "ERMS" }, 181 { SEFF0EBX_INVPCID, "INVPCID" }, 182 { SEFF0EBX_RTM, "RTM" }, 183 { SEFF0EBX_PQM, "PQM" }, 184 { SEFF0EBX_MPX, "MPX" }, 185 { SEFF0EBX_AVX512F, "AVX512F" }, 186 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 187 { SEFF0EBX_RDSEED, "RDSEED" }, 188 { SEFF0EBX_ADX, "ADX" }, 189 { SEFF0EBX_SMAP, "SMAP" }, 190 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 191 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 192 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 193 { SEFF0EBX_CLWB, "CLWB" }, 194 { SEFF0EBX_PT, "PT" }, 195 { SEFF0EBX_AVX512PF, "AVX512PF" }, 196 { SEFF0EBX_AVX512ER, "AVX512ER" }, 197 { SEFF0EBX_AVX512CD, "AVX512CD" }, 198 { SEFF0EBX_SHA, "SHA" }, 199 { SEFF0EBX_AVX512BW, "AVX512BW" }, 200 { SEFF0EBX_AVX512VL, "AVX512VL" }, 201}, cpu_seff0_ecxfeatures[] = { 202 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 203 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 204 { SEFF0ECX_UMIP, "UMIP" }, 205 { SEFF0ECX_PKU, "PKU" }, 206}, cpu_seff0_edxfeatures[] = { 207 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 208 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 209 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 210 { SEFF0EDX_STIBP, "STIBP" }, 211 /* SEFF0EDX_ARCH_CAP (not printed) */ 212}, cpu_tpm_eaxfeatures[] = { 213 { TPM_SENSOR, "SENSOR" }, 214 { TPM_ARAT, "ARAT" }, 215}, cpu_cpuid_perf_eax[] = { 216 { CPUIDEAX_VERID, "PERF" }, 217}, cpu_cpuid_apmi_edx[] = { 218 { CPUIDEDX_ITSC, "ITSC" }, 219}, cpu_amdspec_ebxfeatures[] = { 220 { CPUIDEBX_IBPB, "IBPB" }, 221 { CPUIDEBX_IBRS, "IBRS" }, 222 { CPUIDEBX_STIBP, "STIBP" }, 223 { CPUIDEBX_SSBD, "SSBD" }, 224 { CPUIDEBX_VIRT_SSBD, "VIRTSSBD" }, 225 { CPUIDEBX_SSBD_NOTREQ, "SSBDNR" }, 226}, cpu_xsave_extfeatures[] = { 227 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 228 { XSAVE_XSAVEC, "XSAVEC" }, 229 { XSAVE_XGETBV1, "XGETBV1" }, 230 { XSAVE_XSAVES, "XSAVES" }, 231}; 232 233int 234cpu_amd64speed(int *freq) 235{ 236 *freq = cpuspeed; 237 return (0); 238} 239 240#ifndef SMALL_KERNEL 241void intelcore_update_sensor(void *args); 242/* 243 * Temperature read on the CPU is relative to the maximum 244 * temperature supported by the CPU, Tj(Max). 245 * Refer to: 246 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 247 * Section 35 and 248 * http://www.intel.com/content/dam/www/public/us/en/documents/ 249 * white-papers/cpu-monitoring-dts-peci-paper.pdf 250 * 251 * The temperature on Intel CPUs can be between 70 and 105 degC, since 252 * Westmere we can read the TJmax from the die. For older CPUs we have 253 * to guess or use undocumented MSRs. Then we subtract the temperature 254 * portion of thermal status from max to get current temperature. 255 */ 256void 257intelcore_update_sensor(void *args) 258{ 259 struct cpu_info *ci = (struct cpu_info *) args; 260 u_int64_t msr; 261 int max = 100; 262 263 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 264 if (ci->ci_model == 0x0e && 265 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 266 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 267 max = 85; 268 269 /* 270 * Newer CPUs can tell you what their max temperature is. 271 * See: '64-ia-32-architectures-software-developer- 272 * vol-3c-part-3-manual.pdf' 273 */ 274 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 275 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 276 ci->ci_model != 0x35 && ci->ci_model != 0x36) 277 max = MSR_TEMPERATURE_TARGET_TJMAX( 278 rdmsr(MSR_TEMPERATURE_TARGET)); 279 280 msr = rdmsr(MSR_THERM_STATUS); 281 if (msr & MSR_THERM_STATUS_VALID_BIT) { 282 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 283 /* micro degrees */ 284 ci->ci_sensor.value *= 1000000; 285 /* kelvin */ 286 ci->ci_sensor.value += 273150000; 287 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 288 } else { 289 ci->ci_sensor.value = 0; 290 ci->ci_sensor.flags |= SENSOR_FINVALID; 291 } 292} 293 294#endif 295 296void (*setperf_setup)(struct cpu_info *); 297 298void via_nano_setup(struct cpu_info *ci); 299 300void cpu_topology(struct cpu_info *ci); 301 302void 303via_nano_setup(struct cpu_info *ci) 304{ 305 u_int32_t regs[4], val; 306 u_int64_t msreg; 307 int model = (ci->ci_signature >> 4) & 15; 308 309 if (model >= 9) { 310 CPUID(0xC0000000, regs[0], regs[1], regs[2], regs[3]); 311 val = regs[0]; 312 if (val >= 0xC0000001) { 313 CPUID(0xC0000001, regs[0], regs[1], regs[2], regs[3]); 314 val = regs[3]; 315 } else 316 val = 0; 317 318 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 319 printf("%s:", ci->ci_dev->dv_xname); 320 321 /* Enable RNG if present and disabled */ 322 if (val & C3_CPUID_HAS_RNG) { 323 extern int viac3_rnd_present; 324 325 if (!(val & C3_CPUID_DO_RNG)) { 326 msreg = rdmsr(0x110B); 327 msreg |= 0x40; 328 wrmsr(0x110B, msreg); 329 } 330 viac3_rnd_present = 1; 331 printf(" RNG"); 332 } 333 334 /* Enable AES engine if present and disabled */ 335 if (val & C3_CPUID_HAS_ACE) { 336#ifdef CRYPTO 337 if (!(val & C3_CPUID_DO_ACE)) { 338 msreg = rdmsr(0x1107); 339 msreg |= (0x01 << 28); 340 wrmsr(0x1107, msreg); 341 } 342 amd64_has_xcrypt |= C3_HAS_AES; 343#endif /* CRYPTO */ 344 printf(" AES"); 345 } 346 347 /* Enable ACE2 engine if present and disabled */ 348 if (val & C3_CPUID_HAS_ACE2) { 349#ifdef CRYPTO 350 if (!(val & C3_CPUID_DO_ACE2)) { 351 msreg = rdmsr(0x1107); 352 msreg |= (0x01 << 28); 353 wrmsr(0x1107, msreg); 354 } 355 amd64_has_xcrypt |= C3_HAS_AESCTR; 356#endif /* CRYPTO */ 357 printf(" AES-CTR"); 358 } 359 360 /* Enable SHA engine if present and disabled */ 361 if (val & C3_CPUID_HAS_PHE) { 362#ifdef CRYPTO 363 if (!(val & C3_CPUID_DO_PHE)) { 364 msreg = rdmsr(0x1107); 365 msreg |= (0x01 << 28/**/); 366 wrmsr(0x1107, msreg); 367 } 368 amd64_has_xcrypt |= C3_HAS_SHA; 369#endif /* CRYPTO */ 370 printf(" SHA1 SHA256"); 371 } 372 373 /* Enable MM engine if present and disabled */ 374 if (val & C3_CPUID_HAS_PMM) { 375#ifdef CRYPTO 376 if (!(val & C3_CPUID_DO_PMM)) { 377 msreg = rdmsr(0x1107); 378 msreg |= (0x01 << 28/**/); 379 wrmsr(0x1107, msreg); 380 } 381 amd64_has_xcrypt |= C3_HAS_MM; 382#endif /* CRYPTO */ 383 printf(" RSA"); 384 } 385 386 printf("\n"); 387 } 388} 389 390#ifndef SMALL_KERNEL 391void via_update_sensor(void *args); 392void 393via_update_sensor(void *args) 394{ 395 struct cpu_info *ci = (struct cpu_info *) args; 396 u_int64_t msr; 397 398 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 399 ci->ci_sensor.value = (msr & 0xffffff); 400 /* micro degrees */ 401 ci->ci_sensor.value *= 1000000; 402 ci->ci_sensor.value += 273150000; 403 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 404} 405#endif 406 407uint64_t 408cpu_freq_ctr(struct cpu_info *ci) 409{ 410 uint64_t count, last_count, msr; 411 412 if ((ci->ci_flags & CPUF_CONST_TSC) == 0 || 413 (cpu_perf_eax & CPUIDEAX_VERID) <= 1 || 414 CPUIDEDX_NUM_FC(cpu_perf_edx) <= 1) 415 return (0); 416 417 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 418 if (msr & MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK)) { 419 /* some hypervisor is dicking us around */ 420 return (0); 421 } 422 423 msr |= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_1); 424 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 425 426 msr = rdmsr(MSR_PERF_GLOBAL_CTRL) | MSR_PERF_GLOBAL_CTR1_EN; 427 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 428 429 last_count = rdmsr(MSR_PERF_FIXED_CTR1); 430 delay(100000); 431 count = rdmsr(MSR_PERF_FIXED_CTR1); 432 433 msr = rdmsr(MSR_PERF_FIXED_CTR_CTRL); 434 msr &= MSR_PERF_FIXED_CTR_FC(1, MSR_PERF_FIXED_CTR_FC_MASK); 435 wrmsr(MSR_PERF_FIXED_CTR_CTRL, msr); 436 437 msr = rdmsr(MSR_PERF_GLOBAL_CTRL); 438 msr &= ~MSR_PERF_GLOBAL_CTR1_EN; 439 wrmsr(MSR_PERF_GLOBAL_CTRL, msr); 440 441 return ((count - last_count) * 10); 442} 443 444uint64_t 445cpu_freq(struct cpu_info *ci) 446{ 447 uint64_t last_count, count; 448 449 count = cpu_freq_ctr(ci); 450 if (count != 0) 451 return (count); 452 453 last_count = rdtsc(); 454 delay(100000); 455 count = rdtsc(); 456 457 return ((count - last_count) * 10); 458} 459 460void 461identifycpu(struct cpu_info *ci) 462{ 463 uint64_t freq = 0; 464 u_int32_t dummy, val; 465 char mycpu_model[48]; 466 int i; 467 char *brandstr_from, *brandstr_to; 468 int skipspace; 469 470 CPUID(1, ci->ci_signature, val, dummy, ci->ci_feature_flags); 471 CPUID(0x80000000, ci->ci_pnfeatset, dummy, dummy, dummy); 472 if (ci->ci_pnfeatset >= 0x80000001) { 473 CPUID(0x80000001, ci->ci_efeature_eax, dummy, 474 ci->ci_efeature_ecx, ci->ci_feature_eflags); 475 /* Other bits may clash */ 476 ci->ci_feature_flags |= (ci->ci_feature_eflags & CPUID_NXE); 477 if (ci->ci_flags & CPUF_PRIMARY) 478 ecpu_ecxfeature = ci->ci_efeature_ecx; 479 /* Let cpu_feature be the common bits */ 480 cpu_feature &= ci->ci_feature_flags; 481 } 482 483 CPUID(0x80000002, ci->ci_brand[0], 484 ci->ci_brand[1], ci->ci_brand[2], ci->ci_brand[3]); 485 CPUID(0x80000003, ci->ci_brand[4], 486 ci->ci_brand[5], ci->ci_brand[6], ci->ci_brand[7]); 487 CPUID(0x80000004, ci->ci_brand[8], 488 ci->ci_brand[9], ci->ci_brand[10], ci->ci_brand[11]); 489 strlcpy(mycpu_model, (char *)ci->ci_brand, sizeof(mycpu_model)); 490 491 /* Remove leading, trailing and duplicated spaces from mycpu_model */ 492 brandstr_from = brandstr_to = mycpu_model; 493 skipspace = 1; 494 while (*brandstr_from != '\0') { 495 if (!skipspace || *brandstr_from != ' ') { 496 skipspace = 0; 497 *(brandstr_to++) = *brandstr_from; 498 } 499 if (*brandstr_from == ' ') 500 skipspace = 1; 501 brandstr_from++; 502 } 503 if (skipspace && brandstr_to > mycpu_model) 504 brandstr_to--; 505 *brandstr_to = '\0'; 506 507 if (mycpu_model[0] == 0) 508 strlcpy(mycpu_model, "Opteron or Athlon 64", 509 sizeof(mycpu_model)); 510 511 /* If primary cpu, fill in the global cpu_model used by sysctl */ 512 if (ci->ci_flags & CPUF_PRIMARY) 513 strlcpy(cpu_model, mycpu_model, sizeof(cpu_model)); 514 515 ci->ci_family = (ci->ci_signature >> 8) & 0x0f; 516 ci->ci_model = (ci->ci_signature >> 4) & 0x0f; 517 if (ci->ci_family == 0x6 || ci->ci_family == 0xf) { 518 ci->ci_family += (ci->ci_signature >> 20) & 0xff; 519 ci->ci_model += ((ci->ci_signature >> 16) & 0x0f) << 4; 520 } 521 522 if (ci->ci_feature_flags && ci->ci_feature_flags & CPUID_TSC) { 523 /* Has TSC, check if it's constant */ 524 if (!strcmp(cpu_vendor, "GenuineIntel")) { 525 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 526 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 527 ci->ci_flags |= CPUF_CONST_TSC; 528 } 529 } else if (!strcmp(cpu_vendor, "CentaurHauls")) { 530 /* VIA */ 531 if (ci->ci_model >= 0x0f) { 532 ci->ci_flags |= CPUF_CONST_TSC; 533 } 534 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 535 if (cpu_apmi_edx & CPUIDEDX_ITSC) { 536 /* Invariant TSC indicates constant TSC on 537 * AMD. 538 */ 539 ci->ci_flags |= CPUF_CONST_TSC; 540 } 541 } 542 543 /* Check if it's an invariant TSC */ 544 if (cpu_apmi_edx & CPUIDEDX_ITSC) 545 ci->ci_flags |= CPUF_INVAR_TSC; 546 } 547 548 freq = cpu_freq(ci); 549 550 amd_cpu_cacheinfo(ci); 551 552 printf("%s: %s", ci->ci_dev->dv_xname, mycpu_model); 553 554 if (freq != 0) 555 printf(", %llu.%02llu MHz", (freq + 4999) / 1000000, 556 ((freq + 4999) / 10000) % 100); 557 558 if (ci->ci_flags & CPUF_PRIMARY) { 559 cpuspeed = (freq + 4999) / 1000000; 560 cpu_cpuspeed = cpu_amd64speed; 561 } 562 563 printf("\n%s: ", ci->ci_dev->dv_xname); 564 565 for (i = 0; i < nitems(cpu_cpuid_features); i++) 566 if (ci->ci_feature_flags & cpu_cpuid_features[i].bit) 567 printf("%s%s", i? "," : "", cpu_cpuid_features[i].str); 568 for (i = 0; i < nitems(cpu_cpuid_ecxfeatures); i++) 569 if (cpu_ecxfeature & cpu_cpuid_ecxfeatures[i].bit) 570 printf(",%s", cpu_cpuid_ecxfeatures[i].str); 571 for (i = 0; i < nitems(cpu_ecpuid_features); i++) 572 if (ci->ci_feature_eflags & cpu_ecpuid_features[i].bit) 573 printf(",%s", cpu_ecpuid_features[i].str); 574 for (i = 0; i < nitems(cpu_ecpuid_ecxfeatures); i++) 575 if (ecpu_ecxfeature & cpu_ecpuid_ecxfeatures[i].bit) 576 printf(",%s", cpu_ecpuid_ecxfeatures[i].str); 577 for (i = 0; i < nitems(cpu_cpuid_perf_eax); i++) 578 if (cpu_perf_eax & cpu_cpuid_perf_eax[i].bit) 579 printf(",%s", cpu_cpuid_perf_eax[i].str); 580 for (i = 0; i < nitems(cpu_cpuid_apmi_edx); i++) 581 if (cpu_apmi_edx & cpu_cpuid_apmi_edx[i].bit) 582 printf(",%s", cpu_cpuid_apmi_edx[i].str); 583 584 if (cpuid_level >= 0x07) { 585 /* "Structured Extended Feature Flags" */ 586 CPUID_LEAF(0x7, 0, dummy, ci->ci_feature_sefflags_ebx, 587 ci->ci_feature_sefflags_ecx, ci->ci_feature_sefflags_edx); 588 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 589 if (ci->ci_feature_sefflags_ebx & 590 cpu_seff0_ebxfeatures[i].bit) 591 printf(",%s", cpu_seff0_ebxfeatures[i].str); 592 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 593 if (ci->ci_feature_sefflags_ecx & 594 cpu_seff0_ecxfeatures[i].bit) 595 printf(",%s", cpu_seff0_ecxfeatures[i].str); 596 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 597 if (ci->ci_feature_sefflags_edx & 598 cpu_seff0_edxfeatures[i].bit) 599 printf(",%s", cpu_seff0_edxfeatures[i].str); 600 } 601 602 if (!strcmp(cpu_vendor, "GenuineIntel") && cpuid_level >= 0x06) { 603 CPUID(0x06, ci->ci_feature_tpmflags, dummy, dummy, dummy); 604 for (i = 0; i < nitems(cpu_tpm_eaxfeatures); i++) 605 if (ci->ci_feature_tpmflags & 606 cpu_tpm_eaxfeatures[i].bit) 607 printf(",%s", cpu_tpm_eaxfeatures[i].str); 608 } else if (!strcmp(cpu_vendor, "AuthenticAMD")) { 609 if (ci->ci_family >= 0x12) 610 ci->ci_feature_tpmflags |= TPM_ARAT; 611 } 612 613 /* AMD speculation control features */ 614 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 615 if (ci->ci_pnfeatset >= 0x80000008) { 616 CPUID(0x80000008, dummy, ci->ci_feature_amdspec_ebx, 617 dummy, dummy); 618 for (i = 0; i < nitems(cpu_amdspec_ebxfeatures); i++) 619 if (ci->ci_feature_amdspec_ebx & 620 cpu_amdspec_ebxfeatures[i].bit) 621 printf(",%s", 622 cpu_amdspec_ebxfeatures[i].str); 623 } 624 } 625 626 /* xsave subfeatures */ 627 if (cpuid_level >= 0xd) { 628 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 629 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 630 if (val & cpu_xsave_extfeatures[i].bit) 631 printf(",%s", cpu_xsave_extfeatures[i].str); 632 } 633 634 if (cpu_meltdown) 635 printf(",MELTDOWN"); 636 637 printf("\n"); 638 639 x86_print_cacheinfo(ci); 640 641 /* 642 * Attempt to disable Silicon Debug and lock the configuration 643 * if it's enabled and unlocked. 644 */ 645 if (!strcmp(cpu_vendor, "GenuineIntel") && 646 (cpu_ecxfeature & CPUIDECX_SDBG)) { 647 uint64_t msr; 648 649 msr = rdmsr(IA32_DEBUG_INTERFACE); 650 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 651 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 652 msr &= IA32_DEBUG_INTERFACE_MASK; 653 msr |= IA32_DEBUG_INTERFACE_LOCK; 654 wrmsr(IA32_DEBUG_INTERFACE, msr); 655 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 656 printf("%s: cannot disable silicon debug\n", 657 ci->ci_dev->dv_xname); 658 } 659 660 if (ci->ci_flags & CPUF_PRIMARY) { 661#ifndef SMALL_KERNEL 662 if (!strcmp(cpu_vendor, "AuthenticAMD") && 663 ci->ci_pnfeatset >= 0x80000007) { 664 CPUID(0x80000007, dummy, dummy, dummy, val); 665 666 if (val & 0x06) { 667 if ((ci->ci_signature & 0xF00) == 0xF00) 668 setperf_setup = k8_powernow_init; 669 } 670 if (ci->ci_family >= 0x10) 671 setperf_setup = k1x_init; 672 } 673 674 if (cpu_ecxfeature & CPUIDECX_EST) 675 setperf_setup = est_init; 676#endif 677 678 if (cpu_ecxfeature & CPUIDECX_RDRAND) 679 has_rdrand = 1; 680 681 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 682 has_rdseed = 1; 683 684 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 685 replacesmap(); 686 } 687#ifndef SMALL_KERNEL 688 if (!strncmp(mycpu_model, "Intel", 5)) { 689 u_int32_t cflushsz; 690 691 CPUID(0x01, dummy, cflushsz, dummy, dummy); 692 /* cflush cacheline size is equal to bits 15-8 of ebx * 8 */ 693 ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8; 694 } 695 696 if (CPU_IS_PRIMARY(ci) && (ci->ci_feature_tpmflags & TPM_SENSOR)) { 697 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 698 sizeof(ci->ci_sensordev.xname)); 699 ci->ci_sensor.type = SENSOR_TEMP; 700 sensor_task_register(ci, intelcore_update_sensor, 5); 701 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 702 sensordev_install(&ci->ci_sensordev); 703 } 704#endif 705 706#ifdef CRYPTO 707 if (ci->ci_flags & CPUF_PRIMARY) { 708 if (cpu_ecxfeature & CPUIDECX_PCLMUL) 709 amd64_has_pclmul = 1; 710 711 if (cpu_ecxfeature & CPUIDECX_AES) 712 amd64_has_aesni = 1; 713 } 714#endif 715 716 if (!strcmp(cpu_vendor, "AuthenticAMD")) 717 amd64_errata(ci); 718 719 if (CPU_IS_PRIMARY(ci) && !strcmp(cpu_vendor, "CentaurHauls")) { 720 ci->cpu_setup = via_nano_setup; 721#ifndef SMALL_KERNEL 722 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 723 sizeof(ci->ci_sensordev.xname)); 724 ci->ci_sensor.type = SENSOR_TEMP; 725 sensor_task_register(ci, via_update_sensor, 5); 726 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 727 sensordev_install(&ci->ci_sensordev); 728#endif 729 } 730 731 tsc_timecounter_init(ci, freq); 732 733 cpu_topology(ci); 734#if NVMM > 0 735 cpu_check_vmm_cap(ci); 736#endif /* NVMM > 0 */ 737} 738 739#ifndef SMALL_KERNEL 740/* 741 * Base 2 logarithm of an int. returns 0 for 0 (yeye, I know). 742 */ 743static int 744log2(unsigned int i) 745{ 746 int ret = 0; 747 748 while (i >>= 1) 749 ret++; 750 751 return (ret); 752} 753 754static int 755mask_width(u_int x) 756{ 757 int bit; 758 int mask; 759 int powerof2; 760 761 powerof2 = ((x - 1) & x) == 0; 762 mask = (x << (1 - powerof2)) - 1; 763 764 /* fls */ 765 if (mask == 0) 766 return (0); 767 for (bit = 1; mask != 1; bit++) 768 mask = (unsigned int)mask >> 1; 769 770 return (bit); 771} 772#endif 773 774/* 775 * Build up cpu topology for given cpu, must run on the core itself. 776 */ 777void 778cpu_topology(struct cpu_info *ci) 779{ 780#ifndef SMALL_KERNEL 781 u_int32_t eax, ebx, ecx, edx; 782 u_int32_t apicid, max_apicid = 0, max_coreid = 0; 783 u_int32_t smt_bits = 0, core_bits, pkg_bits = 0; 784 u_int32_t smt_mask = 0, core_mask, pkg_mask = 0; 785 786 /* We need at least apicid at CPUID 1 */ 787 if (cpuid_level < 1) 788 goto no_topology; 789 790 /* Initial apicid */ 791 CPUID(1, eax, ebx, ecx, edx); 792 apicid = (ebx >> 24) & 0xff; 793 794 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 795 /* We need at least apicid at CPUID 0x80000008 */ 796 if (ci->ci_pnfeatset < 0x80000008) 797 goto no_topology; 798 799 if (ci->ci_pnfeatset >= 0x8000001e) { 800 struct cpu_info *ci_other; 801 CPU_INFO_ITERATOR cii; 802 803 CPUID(0x8000001e, eax, ebx, ecx, edx); 804 ci->ci_core_id = ebx & 0xff; 805 ci->ci_pkg_id = ecx & 0xff; 806 ci->ci_smt_id = 0; 807 CPU_INFO_FOREACH(cii, ci_other) { 808 if (ci != ci_other && 809 ci_other->ci_core_id == ci->ci_core_id) 810 ci->ci_smt_id++; 811 } 812 } else { 813 CPUID(0x80000008, eax, ebx, ecx, edx); 814 core_bits = (ecx >> 12) & 0xf; 815 if (core_bits == 0) 816 goto no_topology; 817 /* So coreidsize 2 gives 3, 3 gives 7... */ 818 core_mask = (1 << core_bits) - 1; 819 /* Core id is the least significant considering mask */ 820 ci->ci_core_id = apicid & core_mask; 821 /* Pkg id is the upper remaining bits */ 822 ci->ci_pkg_id = apicid & ~core_mask; 823 ci->ci_pkg_id >>= core_bits; 824 } 825 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 826 /* We only support leaf 1/4 detection */ 827 if (cpuid_level < 4) 828 goto no_topology; 829 /* Get max_apicid */ 830 CPUID(1, eax, ebx, ecx, edx); 831 max_apicid = (ebx >> 16) & 0xff; 832 /* Get max_coreid */ 833 CPUID_LEAF(4, 0, eax, ebx, ecx, edx); 834 max_coreid = ((eax >> 26) & 0x3f) + 1; 835 /* SMT */ 836 smt_bits = mask_width(max_apicid / max_coreid); 837 smt_mask = (1 << smt_bits) - 1; 838 /* Core */ 839 core_bits = log2(max_coreid); 840 core_mask = (1 << (core_bits + smt_bits)) - 1; 841 core_mask ^= smt_mask; 842 /* Pkg */ 843 pkg_bits = core_bits + smt_bits; 844 pkg_mask = -1 << core_bits; 845 846 ci->ci_smt_id = apicid & smt_mask; 847 ci->ci_core_id = (apicid & core_mask) >> smt_bits; 848 ci->ci_pkg_id = (apicid & pkg_mask) >> pkg_bits; 849 } else 850 goto no_topology; 851#ifdef DEBUG 852 printf("cpu%d: smt %u, core %u, pkg %u " 853 "(apicid 0x%x, max_apicid 0x%x, max_coreid 0x%x, smt_bits 0x%x, smt_mask 0x%x, " 854 "core_bits 0x%x, core_mask 0x%x, pkg_bits 0x%x, pkg_mask 0x%x)\n", 855 ci->ci_cpuid, ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id, 856 apicid, max_apicid, max_coreid, smt_bits, smt_mask, core_bits, 857 core_mask, pkg_bits, pkg_mask); 858#else 859 printf("cpu%d: smt %u, core %u, package %u\n", ci->ci_cpuid, 860 ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id); 861 862#endif 863 return; 864 /* We can't map, so consider ci_core_id as ci_cpuid */ 865no_topology: 866#endif 867 ci->ci_smt_id = 0; 868 ci->ci_core_id = ci->ci_cpuid; 869 ci->ci_pkg_id = 0; 870} 871 872#if NVMM > 0 873/* 874 * cpu_check_vmm_cap 875 * 876 * Checks for VMM capabilities for 'ci'. Initializes certain per-cpu VMM 877 * state in 'ci' if virtualization extensions are found. 878 * 879 * Parameters: 880 * ci: the cpu being checked 881 */ 882void 883cpu_check_vmm_cap(struct cpu_info *ci) 884{ 885 uint64_t msr; 886 uint32_t cap, dummy, edx; 887 888 /* 889 * Check for workable VMX 890 */ 891 if (cpu_ecxfeature & CPUIDECX_VMX) { 892 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 893 894 if (!(msr & IA32_FEATURE_CONTROL_LOCK)) 895 ci->ci_vmm_flags |= CI_VMM_VMX; 896 else { 897 if (msr & IA32_FEATURE_CONTROL_VMX_EN) 898 ci->ci_vmm_flags |= CI_VMM_VMX; 899 else 900 ci->ci_vmm_flags |= CI_VMM_DIS; 901 } 902 } 903 904 /* 905 * Check for EPT (Intel Nested Paging) and other secondary 906 * controls 907 */ 908 if (ci->ci_vmm_flags & CI_VMM_VMX) { 909 /* Secondary controls available? */ 910 /* XXX should we check true procbased ctls here if avail? */ 911 msr = rdmsr(IA32_VMX_PROCBASED_CTLS); 912 if (msr & (IA32_VMX_ACTIVATE_SECONDARY_CONTROLS) << 32) { 913 msr = rdmsr(IA32_VMX_PROCBASED2_CTLS); 914 /* EPT available? */ 915 if (msr & (IA32_VMX_ENABLE_EPT) << 32) 916 ci->ci_vmm_flags |= CI_VMM_EPT; 917 /* VM Functions available? */ 918 if (msr & (IA32_VMX_ENABLE_VM_FUNCTIONS) << 32) { 919 ci->ci_vmm_cap.vcc_vmx.vmx_vm_func = 920 rdmsr(IA32_VMX_VMFUNC); 921 } 922 } 923 } 924 925 /* 926 * Check startup config (VMX) 927 */ 928 if (ci->ci_vmm_flags & CI_VMM_VMX) { 929 /* CR0 fixed and flexible bits */ 930 msr = rdmsr(IA32_VMX_CR0_FIXED0); 931 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed0 = msr; 932 msr = rdmsr(IA32_VMX_CR0_FIXED1); 933 ci->ci_vmm_cap.vcc_vmx.vmx_cr0_fixed1 = msr; 934 935 /* CR4 fixed and flexible bits */ 936 msr = rdmsr(IA32_VMX_CR4_FIXED0); 937 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed0 = msr; 938 msr = rdmsr(IA32_VMX_CR4_FIXED1); 939 ci->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed1 = msr; 940 941 /* VMXON region revision ID (bits 30:0 of IA32_VMX_BASIC) */ 942 msr = rdmsr(IA32_VMX_BASIC); 943 ci->ci_vmm_cap.vcc_vmx.vmx_vmxon_revision = 944 (uint32_t)(msr & 0x7FFFFFFF); 945 946 /* MSR save / load table size */ 947 msr = rdmsr(IA32_VMX_MISC); 948 ci->ci_vmm_cap.vcc_vmx.vmx_msr_table_size = 949 (uint32_t)(msr & IA32_VMX_MSR_LIST_SIZE_MASK) >> 25; 950 951 /* CR3 target count size */ 952 ci->ci_vmm_cap.vcc_vmx.vmx_cr3_tgt_count = 953 (uint32_t)(msr & IA32_VMX_CR3_TGT_SIZE_MASK) >> 16; 954 } 955 956 /* 957 * Check for workable SVM 958 */ 959 if (ecpu_ecxfeature & CPUIDECX_SVM) { 960 msr = rdmsr(MSR_AMD_VM_CR); 961 962 if (!(msr & AMD_SVMDIS)) 963 ci->ci_vmm_flags |= CI_VMM_SVM; 964 965 CPUID(CPUID_AMD_SVM_CAP, dummy, 966 ci->ci_vmm_cap.vcc_svm.svm_max_asid, dummy, edx); 967 968 if (ci->ci_vmm_cap.vcc_svm.svm_max_asid > 0xFFF) 969 ci->ci_vmm_cap.vcc_svm.svm_max_asid = 0xFFF; 970 971 if (edx & AMD_SVM_FLUSH_BY_ASID_CAP) 972 ci->ci_vmm_cap.vcc_svm.svm_flush_by_asid = 1; 973 974 if (edx & AMD_SVM_VMCB_CLEAN_CAP) 975 ci->ci_vmm_cap.vcc_svm.svm_vmcb_clean = 1; 976 } 977 978 /* 979 * Check for SVM Nested Paging 980 */ 981 if ((ci->ci_vmm_flags & CI_VMM_SVM) && 982 ci->ci_pnfeatset >= CPUID_AMD_SVM_CAP) { 983 CPUID(CPUID_AMD_SVM_CAP, dummy, dummy, dummy, cap); 984 if (cap & AMD_SVM_NESTED_PAGING_CAP) 985 ci->ci_vmm_flags |= CI_VMM_RVI; 986 } 987} 988#endif /* NVMM > 0 */ 989