1/* $OpenBSD: pci_6600.c,v 1.21 2015/07/26 05:09:44 miod Exp $ */ 2/* $NetBSD: pci_6600.c,v 1.5 2000/06/06 00:50:15 thorpej Exp $ */ 3 4/*- 5 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ross Harvey. 18 * 4. The name of Ross Harvey may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/kernel.h> 38#include <sys/device.h> 39#include <sys/malloc.h> 40 41#include <machine/autoconf.h> 42#define _ALPHA_BUS_DMA_PRIVATE 43#include <machine/bus.h> 44#include <machine/rpb.h> 45 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/ppbreg.h> 49#include <dev/pci/pciidereg.h> 50#include <dev/pci/pciidevar.h> 51 52#include <alpha/pci/tsreg.h> 53#include <alpha/pci/tsvar.h> 54#include <alpha/pci/pci_6600.h> 55 56#define pci_6600() { Generate ctags(1) key. } 57 58#include "sio.h" 59#if NSIO 60#include <alpha/pci/siovar.h> 61#endif 62 63#define PCI_NIRQ 64 64#define PCI_STRAY_MAX 5 65 66/* 67 * Some Tsunami models have a PCI device (the USB controller) with interrupts 68 * tied to ISA IRQ lines. The IRQ is encoded as: 69 * 70 * line = 0xe0 | isa_irq; 71 */ 72#define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 73#define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 74 75static struct tsp_config *sioprimary; 76 77void dec_6600_intr_disestablish(void *, void *); 78void *dec_6600_intr_establish(void *, pci_intr_handle_t, int, 79 int (*func)(void *), void *, const char *); 80const char *dec_6600_intr_string(void *, pci_intr_handle_t); 81int dec_6600_intr_line(void *, pci_intr_handle_t); 82int dec_6600_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 83void *dec_6600_pciide_compat_intr_establish(void *, struct device *, 84 struct pci_attach_args *, int, int (*)(void *), void *); 85void dec_6600_pciide_compat_intr_disestablish(void *, void *); 86 87struct alpha_shared_intr *dec_6600_pci_intr; 88 89void dec_6600_iointr(void *arg, unsigned long vec); 90extern void dec_6600_intr_enable(int irq); 91extern void dec_6600_intr_disable(int irq); 92 93void 94pci_6600_pickintr(pcp) 95 struct tsp_config *pcp; 96{ 97 bus_space_tag_t iot = &pcp->pc_iot; 98 pci_chipset_tag_t pc = &pcp->pc_pc; 99#if 0 100 char *cp; 101#endif 102 int i; 103 104 pc->pc_intr_v = pcp; 105 pc->pc_intr_map = dec_6600_intr_map; 106 pc->pc_intr_string = dec_6600_intr_string; 107 pc->pc_intr_line = dec_6600_intr_line; 108 pc->pc_intr_establish = dec_6600_intr_establish; 109 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 110 pc->pc_pciide_compat_intr_establish = NULL; 111 112 /* 113 * System-wide and Pchip-0-only logic... 114 */ 115 if (dec_6600_pci_intr == NULL) { 116 sioprimary = pcp; 117 pc->pc_pciide_compat_intr_establish = 118 dec_6600_pciide_compat_intr_establish; 119 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ); 120 for (i = 0; i < PCI_NIRQ; i++) { 121 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 122 PCI_STRAY_MAX); 123 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 124 sioprimary); 125 } 126#if NSIO 127 sio_intr_setup(pc, iot); 128 dec_6600_intr_enable(55); /* irq line for sio */ 129#endif 130 } 131} 132 133int 134dec_6600_intr_map(pa, ihp) 135 struct pci_attach_args *pa; 136 pci_intr_handle_t *ihp; 137{ 138 int buspin, line = pa->pa_intrline; 139 140 /* 141 * The console places the interrupt mapping in the "line" value. 142 * We trust it whenever possible. 143 */ 144 if (line >= 0 && line < PCI_NIRQ) { 145 *ihp = line; 146 return 0; 147 } 148 if (DEC_6600_LINE_IS_ISA(line)) { 149#if NSIO > 0 150 *ihp = line; 151 return 0; 152#else 153 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 154 DEC_6600_LINE_ISA_IRQ(line), 155 pa->pa_bus, pa->pa_device, pa->pa_function); 156 return 1; 157#endif 158 } 159 160 if (pa->pa_bridgetag) { 161 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 162 pa->pa_device); 163 if (pa->pa_bridgeih[buspin - 1] != 0) { 164 *ihp = pa->pa_bridgeih[buspin - 1]; 165 return 0; 166 } 167 } 168 169 return 1; 170} 171 172const char * 173dec_6600_intr_string(acv, ih) 174 void *acv; 175 pci_intr_handle_t ih; 176{ 177 178 static const char irqfmt[] = "dec 6600 irq %ld"; 179 static char irqstr[sizeof irqfmt]; 180 181#if NSIO 182 if (DEC_6600_LINE_IS_ISA(ih)) 183 return (sio_intr_string(NULL /*XXX*/, 184 DEC_6600_LINE_ISA_IRQ(ih))); 185#endif 186 187 snprintf(irqstr, sizeof irqstr, irqfmt, ih); 188 return (irqstr); 189} 190 191int 192dec_6600_intr_line(acv, ih) 193 void *acv; 194 pci_intr_handle_t ih; 195{ 196 197#if NSIO 198 if (DEC_6600_LINE_IS_ISA(ih)) 199 return (sio_intr_line(NULL /*XXX*/, 200 DEC_6600_LINE_ISA_IRQ(ih))); 201#endif 202 203 return (ih); 204} 205 206void * 207dec_6600_intr_establish(acv, ih, level, func, arg, name) 208 void *acv, *arg; 209 pci_intr_handle_t ih; 210 int level; 211 int (*func)(void *); 212 const char *name; 213{ 214 void *cookie; 215 216#if NSIO 217 if (DEC_6600_LINE_IS_ISA(ih)) 218 return (sio_intr_establish(NULL /*XXX*/, 219 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg, 220 name)); 221#endif 222 223 if (ih >= PCI_NIRQ) 224 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx", 225 ih); 226 227 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 228 level, func, arg, name); 229 230 if (cookie != NULL && 231 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) { 232 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL); 233 dec_6600_intr_enable(ih); 234 } 235 return (cookie); 236} 237 238void 239dec_6600_intr_disestablish(acv, cookie) 240 void *acv, *cookie; 241{ 242 struct alpha_shared_intrhand *ih = cookie; 243 unsigned int irq = ih->ih_num; 244 int s; 245 246#if NSIO 247 /* 248 * We have to determine if this is an ISA IRQ or not! We do this 249 * by checking to see if the intrhand points back to an intrhead 250 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 251 * Pretty disgusting, eh? 252 */ 253 if (ih->ih_intrhead->intr_private != sioprimary) { 254 sio_intr_disestablish(NULL /*XXX*/, cookie); 255 return; 256 } 257#endif 258 259 s = splhigh(); 260 261 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie); 262 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 263 dec_6600_intr_disable(irq); 264 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 265 IST_NONE); 266 scb_free(0x900 + SCB_IDXTOVEC(irq)); 267 } 268 269 splx(s); 270} 271 272void 273dec_6600_iointr(arg, vec) 274 void *arg; 275 unsigned long vec; 276{ 277 int irq; 278 279 irq = SCB_VECTOIDX(vec - 0x900); 280 281 if (irq >= PCI_NIRQ) 282 panic("dec_6600_iointr: irq %d is too high", irq); 283 284 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 285 alpha_shared_intr_stray(dec_6600_pci_intr, irq, "6600 irq"); 286 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 287 dec_6600_intr_disable(irq); 288 } else 289 alpha_shared_intr_reset_strays(dec_6600_pci_intr, irq); 290} 291 292void 293dec_6600_intr_enable(irq) 294 int irq; 295{ 296 alpha_mb(); 297 STQP(TS_C_DIM0) |= 1UL << irq; 298 alpha_mb(); 299} 300 301void 302dec_6600_intr_disable(irq) 303 int irq; 304{ 305 alpha_mb(); 306 STQP(TS_C_DIM0) &= ~(1UL << irq); 307 alpha_mb(); 308} 309 310void * 311dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 312 void *v; 313 struct device *dev; 314 struct pci_attach_args *pa; 315 int chan; 316 int (*func)(void *); 317 void *arg; 318{ 319 pci_chipset_tag_t pc = pa->pa_pc; 320 void *cookie = NULL; 321 int bus, irq; 322 323 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 324 325 /* 326 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 327 * bridge, all bets are off. 328 */ 329 if (bus != 0 || pc->pc_intr_v != sioprimary) 330 return (NULL); 331 332 irq = PCIIDE_COMPAT_IRQ(chan); 333#if NSIO 334 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 335 func, arg, dev->dv_xname); 336 337 if (cookie == NULL) 338 return (NULL); 339#endif 340 return (cookie); 341} 342 343void 344dec_6600_pciide_compat_intr_disestablish(v, cookie) 345 void *v; 346 void *cookie; 347{ 348 sio_intr_disestablish(NULL, cookie); 349} 350