pci_1000.c revision 1.9 
1/* $OpenBSD: pci_1000.c,v 1.9 2009/08/22 02:54:50 mk Exp $ */
2/* $NetBSD: pci_1000.c,v 1.12 2001/07/27 00:25:20 thorpej Exp $ */
3
4/*
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
9 * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
10 * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
11 * Computer Systems, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
37 * All rights reserved.
38 *
39 * Author: Chris G. Demetriou
40 *
41 * Permission to use, copy, modify and distribute this software and
42 * its documentation is hereby granted, provided that both the copyright
43 * notice and this permission notice appear in all copies of the
44 * software, derivative works or modified versions, and any portions
45 * thereof, and that both notices appear in supporting documentation.
46 *
47 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
48 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
49 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
50 *
51 * Carnegie Mellon requests users of this software to return to
52 *
53 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
54 *  School of Computer Science
55 *  Carnegie Mellon University
56 *  Pittsburgh PA 15213-3890
57 *
58 * any improvements or extensions that they make and grant Carnegie the
59 * rights to redistribute these changes.
60 */
61
62#include <sys/types.h>
63#include <sys/param.h>
64#include <sys/time.h>
65#include <sys/systm.h>
66#include <sys/errno.h>
67#include <sys/malloc.h>
68#include <sys/device.h>
69
70#include <uvm/uvm_extern.h>
71
72#include <machine/autoconf.h>
73
74#include <dev/pci/pcireg.h>
75#include <dev/pci/pcivar.h>
76
77#include <alpha/pci/pci_1000.h>
78
79#include "sio.h"
80#if NSIO > 0 || NPCEB > 0
81#include <alpha/pci/siovar.h>
82#endif
83
84static bus_space_tag_t another_mystery_icu_iot;
85static bus_space_handle_t another_mystery_icu_ioh;
86
87int	dec_1000_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
88const char *dec_1000_intr_string(void *, pci_intr_handle_t);
89int	dec_1000_intr_line(void *, pci_intr_handle_t);
90void	*dec_1000_intr_establish(void *, pci_intr_handle_t,
91	    int, int (*func)(void *), void *, const char *);
92void	dec_1000_intr_disestablish(void *, void *);
93
94#define	PCI_NIRQ	16
95#define	PCI_STRAY_MAX	5
96
97struct alpha_shared_intr *dec_1000_pci_intr;
98
99void dec_1000_iointr(void *arg, unsigned long vec);
100void dec_1000_enable_intr(int irq);
101void dec_1000_disable_intr(int irq);
102void pci_1000_imi(void);
103
104void
105pci_1000_pickintr(core, iot, memt, pc)
106	void *core;
107	bus_space_tag_t iot, memt;
108	pci_chipset_tag_t pc;
109{
110#if 0
111	char *cp;
112#endif
113	int i;
114
115	another_mystery_icu_iot = iot;
116
117	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
118		panic("pci_1000_pickintr");
119        pc->pc_intr_v = core;
120        pc->pc_intr_map = dec_1000_intr_map;
121        pc->pc_intr_string = dec_1000_intr_string;
122	pc->pc_intr_line = dec_1000_intr_line;
123        pc->pc_intr_establish = dec_1000_intr_establish;
124        pc->pc_intr_disestablish = dec_1000_intr_disestablish;
125
126	pc->pc_pciide_compat_intr_establish = NULL;
127	pc->pc_pciide_compat_intr_disestablish = NULL;
128
129	dec_1000_pci_intr =
130	    alpha_shared_intr_alloc(PCI_NIRQ);
131	for (i = 0; i < PCI_NIRQ; i++) {
132		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
133		    PCI_STRAY_MAX);
134	}
135
136	pci_1000_imi();
137#if NSIO > 0 || NPCEB > 0
138	sio_intr_setup(pc, iot);
139#endif
140}
141
142int
143dec_1000_intr_map(pa, ihp)
144	struct pci_attach_args *pa;
145        pci_intr_handle_t *ihp;
146{
147	pcitag_t bustag = pa->pa_intrtag;
148	int buspin = pa->pa_intrpin;
149	int device;
150
151	if (buspin == 0)	/* No IRQ used. */
152		return 1;
153	if (!(1 <= buspin && buspin <= 4))
154		goto bad;
155
156	pci_decompose_tag(pa->pa_pc, bustag, NULL, &device, NULL);
157
158	switch(device) {
159	case 6:
160		if(buspin != 1)
161			break;
162		*ihp = 0xc;		/* integrated ncr scsi */
163		return 0;
164	case 11:
165	case 12:
166	case 13:
167		*ihp = (device - 11) * 4 + buspin - 1;
168		return 0;
169	}
170
171bad:
172	return 1;
173}
174
175const char *
176dec_1000_intr_string(ccv, ih)
177	void *ccv;
178	pci_intr_handle_t ih;
179{
180	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
181        static char irqstr[sizeof irqmsg_fmt];
182
183        if (ih >= PCI_NIRQ)
184                panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih);
185
186        snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
187        return (irqstr);
188}
189
190int
191dec_1000_intr_line(ccv, ih)
192	void *ccv;
193	pci_intr_handle_t ih;
194{
195#if NSIO > 0
196	return sio_intr_line(NULL /*XXX*/, ih);
197#else
198	return (ih);
199#endif
200}
201
202void *
203dec_1000_intr_establish(ccv, ih, level, func, arg, name)
204        void *ccv;
205        pci_intr_handle_t ih;
206        int level;
207        int (*func)(void *);
208	void *arg;
209	const char *name;
210{
211	void *cookie;
212
213        if (ih >= PCI_NIRQ)
214                panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih);
215
216	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
217	    level, func, arg, name);
218
219	if (cookie != NULL &&
220	    alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) {
221		scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL);
222		dec_1000_enable_intr(ih);
223	}
224	return (cookie);
225}
226
227void
228dec_1000_intr_disestablish(ccv, cookie)
229        void *ccv, *cookie;
230{
231	struct alpha_shared_intrhand *ih = cookie;
232	unsigned int irq = ih->ih_num;
233	int s;
234
235	s = splhigh();
236
237	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
238	    "dec_1000 irq");
239	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
240		dec_1000_disable_intr(irq);
241		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
242		    IST_NONE);
243		scb_free(0x900 + SCB_IDXTOVEC(irq));
244	}
245
246	splx(s);
247}
248
249void
250dec_1000_iointr(arg, vec)
251	void *arg;
252	unsigned long vec;
253{
254	int irq;
255
256	irq = SCB_VECTOIDX(vec - 0x900);
257
258	if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
259		alpha_shared_intr_stray(dec_1000_pci_intr, irq,
260		    "dec_1000 irq");
261		if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
262			dec_1000_disable_intr(irq);
263	} else
264		alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq);
265}
266
267/*
268 * Read and write the mystery ICU IMR registers
269 */
270
271#define	IR() bus_space_read_2(another_mystery_icu_iot,		\
272				another_mystery_icu_ioh, 0)
273
274#define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
275				another_mystery_icu_ioh, 0, (v))
276
277/*
278 * Enable and disable interrupts at the ICU level
279 */
280
281void
282dec_1000_enable_intr(irq)
283	int irq;
284{
285	IW(IR() | 1 << irq);
286}
287
288void
289dec_1000_disable_intr(irq)
290	int irq;
291{
292	IW(IR() & ~(1 << irq));
293}
294/*
295 * Initialize mystery ICU
296 */
297void
298pci_1000_imi()
299{
300	IW(0);					/* XXX ?? */
301}
302