pci_1000.c revision 1.7 
1/* $OpenBSD: pci_1000.c,v 1.7 2008/06/26 05:42:09 ray Exp $ */
2/* $NetBSD: pci_1000.c,v 1.12 2001/07/27 00:25:20 thorpej Exp $ */
3
4/*
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
9 * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
10 * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
11 * Computer Systems, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
37 * All rights reserved.
38 *
39 * Author: Chris G. Demetriou
40 *
41 * Permission to use, copy, modify and distribute this software and
42 * its documentation is hereby granted, provided that both the copyright
43 * notice and this permission notice appear in all copies of the
44 * software, derivative works or modified versions, and any portions
45 * thereof, and that both notices appear in supporting documentation.
46 *
47 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
48 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
49 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
50 *
51 * Carnegie Mellon requests users of this software to return to
52 *
53 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
54 *  School of Computer Science
55 *  Carnegie Mellon University
56 *  Pittsburgh PA 15213-3890
57 *
58 * any improvements or extensions that they make and grant Carnegie the
59 * rights to redistribute these changes.
60 */
61
62#include <sys/types.h>
63#include <sys/param.h>
64#include <sys/time.h>
65#include <sys/systm.h>
66#include <sys/errno.h>
67#include <sys/malloc.h>
68#include <sys/device.h>
69
70#include <uvm/uvm_extern.h>
71
72#include <machine/autoconf.h>
73
74#include <dev/pci/pcireg.h>
75#include <dev/pci/pcivar.h>
76
77#include <alpha/pci/pci_1000.h>
78
79#include "sio.h"
80#if NSIO > 0 || NPCEB > 0
81#include <alpha/pci/siovar.h>
82#endif
83
84static bus_space_tag_t another_mystery_icu_iot;
85static bus_space_handle_t another_mystery_icu_ioh;
86
87int	dec_1000_intr_map(void *, pcitag_t, int, int, pci_intr_handle_t *);
88const char *dec_1000_intr_string(void *, pci_intr_handle_t);
89int	dec_1000_intr_line(void *, pci_intr_handle_t);
90void	*dec_1000_intr_establish(void *, pci_intr_handle_t,
91	    int, int (*func)(void *), void *, char *);
92void	dec_1000_intr_disestablish(void *, void *);
93
94#define	PCI_NIRQ	16
95#define	PCI_STRAY_MAX	5
96
97struct alpha_shared_intr *dec_1000_pci_intr;
98
99void dec_1000_iointr(void *arg, unsigned long vec);
100void dec_1000_enable_intr(int irq);
101void dec_1000_disable_intr(int irq);
102void pci_1000_imi(void);
103static pci_chipset_tag_t pc_tag;
104
105void
106pci_1000_pickintr(core, iot, memt, pc)
107	void *core;
108	bus_space_tag_t iot, memt;
109	pci_chipset_tag_t pc;
110{
111#if 0
112	char *cp;
113#endif
114	int i;
115
116	another_mystery_icu_iot = iot;
117
118	pc_tag = pc;
119	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
120		panic("pci_1000_pickintr");
121        pc->pc_intr_v = core;
122        pc->pc_intr_map = dec_1000_intr_map;
123        pc->pc_intr_string = dec_1000_intr_string;
124	pc->pc_intr_line = dec_1000_intr_line;
125        pc->pc_intr_establish = dec_1000_intr_establish;
126        pc->pc_intr_disestablish = dec_1000_intr_disestablish;
127
128	pc->pc_pciide_compat_intr_establish = NULL;
129	pc->pc_pciide_compat_intr_disestablish = NULL;
130
131	dec_1000_pci_intr =
132	    alpha_shared_intr_alloc(PCI_NIRQ);
133	for (i = 0; i < PCI_NIRQ; i++) {
134		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
135		    PCI_STRAY_MAX);
136	}
137
138	pci_1000_imi();
139#if NSIO > 0 || NPCEB > 0
140	sio_intr_setup(pc, iot);
141#endif
142}
143
144int
145dec_1000_intr_map(ccv, bustag, buspin, line, ihp)
146	void *ccv;
147	pcitag_t bustag;
148	int buspin, line;
149        pci_intr_handle_t *ihp;
150{
151	int	device;
152
153	if (buspin == 0)	/* No IRQ used. */
154		return 1;
155	if (!(1 <= buspin && buspin <= 4))
156		goto bad;
157
158	pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL);
159
160	switch(device) {
161	case 6:
162		if(buspin != 1)
163			break;
164		*ihp = 0xc;		/* integrated ncr scsi */
165		return 0;
166	case 11:
167	case 12:
168	case 13:
169		*ihp = (device - 11) * 4 + buspin - 1;
170		return 0;
171	}
172
173bad:
174	return 1;
175}
176
177const char *
178dec_1000_intr_string(ccv, ih)
179	void *ccv;
180	pci_intr_handle_t ih;
181{
182	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
183        static char irqstr[sizeof irqmsg_fmt];
184
185        if (ih >= PCI_NIRQ)
186                panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih);
187
188        snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
189        return (irqstr);
190}
191
192int
193dec_1000_intr_line(ccv, ih)
194	void *ccv;
195	pci_intr_handle_t ih;
196{
197#if NSIO > 0
198	return sio_intr_line(NULL /*XXX*/, ih);
199#else
200	return (ih);
201#endif
202}
203
204void *
205dec_1000_intr_establish(ccv, ih, level, func, arg, name)
206        void *ccv;
207        pci_intr_handle_t ih;
208        int level;
209        int (*func)(void *);
210	void *arg;
211	char *name;
212{
213	void *cookie;
214
215        if (ih >= PCI_NIRQ)
216                panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih);
217
218	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
219	    level, func, arg, name);
220
221	if (cookie != NULL &&
222	    alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) {
223		scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL);
224		dec_1000_enable_intr(ih);
225	}
226	return (cookie);
227}
228
229void
230dec_1000_intr_disestablish(ccv, cookie)
231        void *ccv, *cookie;
232{
233	struct alpha_shared_intrhand *ih = cookie;
234	unsigned int irq = ih->ih_num;
235	int s;
236
237	s = splhigh();
238
239	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
240	    "dec_1000 irq");
241	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
242		dec_1000_disable_intr(irq);
243		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
244		    IST_NONE);
245		scb_free(0x900 + SCB_IDXTOVEC(irq));
246	}
247
248	splx(s);
249}
250
251void
252dec_1000_iointr(arg, vec)
253	void *arg;
254	unsigned long vec;
255{
256	int irq;
257
258	irq = SCB_VECTOIDX(vec - 0x900);
259
260	if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
261		alpha_shared_intr_stray(dec_1000_pci_intr, irq,
262		    "dec_1000 irq");
263		if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
264			dec_1000_disable_intr(irq);
265	} else
266		alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq);
267}
268
269/*
270 * Read and write the mystery ICU IMR registers
271 */
272
273#define	IR() bus_space_read_2(another_mystery_icu_iot,		\
274				another_mystery_icu_ioh, 0)
275
276#define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
277				another_mystery_icu_ioh, 0, (v))
278
279/*
280 * Enable and disable interrupts at the ICU level
281 */
282
283void
284dec_1000_enable_intr(irq)
285	int irq;
286{
287	IW(IR() | 1 << irq);
288}
289
290void
291dec_1000_disable_intr(irq)
292	int irq;
293{
294	IW(IR() & ~(1 << irq));
295}
296/*
297 * Initialize mystery ICU
298 */
299void
300pci_1000_imi()
301{
302	IW(0);					/* XXX ?? */
303}
304