pci_1000.c revision 1.5
1/* $OpenBSD: pci_1000.c,v 1.5 2006/06/15 20:08:29 brad Exp $ */ 2/* $NetBSD: pci_1000.c,v 1.12 2001/07/27 00:25:20 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at 9 * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle 10 * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon 11 * Computer Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42/* 43 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 44 * All rights reserved. 45 * 46 * Author: Chris G. Demetriou 47 * 48 * Permission to use, copy, modify and distribute this software and 49 * its documentation is hereby granted, provided that both the copyright 50 * notice and this permission notice appear in all copies of the 51 * software, derivative works or modified versions, and any portions 52 * thereof, and that both notices appear in supporting documentation. 53 * 54 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 55 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 56 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 57 * 58 * Carnegie Mellon requests users of this software to return to 59 * 60 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 61 * School of Computer Science 62 * Carnegie Mellon University 63 * Pittsburgh PA 15213-3890 64 * 65 * any improvements or extensions that they make and grant Carnegie the 66 * rights to redistribute these changes. 67 */ 68 69#include <sys/types.h> 70#include <sys/param.h> 71#include <sys/time.h> 72#include <sys/systm.h> 73#include <sys/errno.h> 74#include <sys/malloc.h> 75#include <sys/device.h> 76 77#include <uvm/uvm_extern.h> 78 79#include <machine/autoconf.h> 80 81#include <dev/pci/pcireg.h> 82#include <dev/pci/pcivar.h> 83 84#include <alpha/pci/pci_1000.h> 85 86#include "sio.h" 87#if NSIO > 0 || NPCEB > 0 88#include <alpha/pci/siovar.h> 89#endif 90 91static bus_space_tag_t another_mystery_icu_iot; 92static bus_space_handle_t another_mystery_icu_ioh; 93 94int dec_1000_intr_map(void *, pcitag_t, int, int, pci_intr_handle_t *); 95const char *dec_1000_intr_string(void *, pci_intr_handle_t); 96int dec_1000_intr_line(void *, pci_intr_handle_t); 97void *dec_1000_intr_establish(void *, pci_intr_handle_t, 98 int, int (*func)(void *), void *, char *); 99void dec_1000_intr_disestablish(void *, void *); 100 101#define PCI_NIRQ 16 102#define PCI_STRAY_MAX 5 103 104struct alpha_shared_intr *dec_1000_pci_intr; 105 106void dec_1000_iointr(void *arg, unsigned long vec); 107void dec_1000_enable_intr(int irq); 108void dec_1000_disable_intr(int irq); 109void pci_1000_imi(void); 110static pci_chipset_tag_t pc_tag; 111 112void 113pci_1000_pickintr(core, iot, memt, pc) 114 void *core; 115 bus_space_tag_t iot, memt; 116 pci_chipset_tag_t pc; 117{ 118#if 0 119 char *cp; 120#endif 121 int i; 122 123 another_mystery_icu_iot = iot; 124 125 pc_tag = pc; 126 if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh)) 127 panic("pci_1000_pickintr"); 128 pc->pc_intr_v = core; 129 pc->pc_intr_map = dec_1000_intr_map; 130 pc->pc_intr_string = dec_1000_intr_string; 131 pc->pc_intr_line = dec_1000_intr_line; 132 pc->pc_intr_establish = dec_1000_intr_establish; 133 pc->pc_intr_disestablish = dec_1000_intr_disestablish; 134 135 pc->pc_pciide_compat_intr_establish = NULL; 136 pc->pc_pciide_compat_intr_disestablish = NULL; 137 138 dec_1000_pci_intr = 139 alpha_shared_intr_alloc(PCI_NIRQ); 140 for (i = 0; i < PCI_NIRQ; i++) { 141 alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i, 142 PCI_STRAY_MAX); 143 } 144 145 pci_1000_imi(); 146#if NSIO > 0 || NPCEB > 0 147 sio_intr_setup(pc, iot); 148#endif 149} 150 151int 152dec_1000_intr_map(ccv, bustag, buspin, line, ihp) 153 void *ccv; 154 pcitag_t bustag; 155 int buspin, line; 156 pci_intr_handle_t *ihp; 157{ 158 int device; 159 160 if (buspin == 0) /* No IRQ used. */ 161 return 1; 162 if (!(1 <= buspin && buspin <= 4)) 163 goto bad; 164 165 pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL); 166 167 switch(device) { 168 case 6: 169 if(buspin != 1) 170 break; 171 *ihp = 0xc; /* integrated ncr scsi */ 172 return 0; 173 case 11: 174 case 12: 175 case 13: 176 *ihp = (device - 11) * 4 + buspin - 1; 177 return 0; 178 } 179 180bad: printf("dec_1000_intr_map: can't map dev %d pin %d\n", device, buspin); 181 return 1; 182} 183 184const char * 185dec_1000_intr_string(ccv, ih) 186 void *ccv; 187 pci_intr_handle_t ih; 188{ 189 static const char irqmsg_fmt[] = "dec_1000 irq %ld"; 190 static char irqstr[sizeof irqmsg_fmt]; 191 192 if (ih >= PCI_NIRQ) 193 panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih); 194 195 snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih); 196 return (irqstr); 197} 198 199int 200dec_1000_intr_line(ccv, ih) 201 void *ccv; 202 pci_intr_handle_t ih; 203{ 204#if NSIO > 0 205 return sio_intr_line(NULL /*XXX*/, ih); 206#else 207 return (ih); 208#endif 209} 210 211void * 212dec_1000_intr_establish(ccv, ih, level, func, arg, name) 213 void *ccv; 214 pci_intr_handle_t ih; 215 int level; 216 int (*func)(void *); 217 void *arg; 218 char *name; 219{ 220 void *cookie; 221 222 if (ih >= PCI_NIRQ) 223 panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih); 224 225 cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL, 226 level, func, arg, name); 227 228 if (cookie != NULL && 229 alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) { 230 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL); 231 dec_1000_enable_intr(ih); 232 } 233 return (cookie); 234} 235 236void 237dec_1000_intr_disestablish(ccv, cookie) 238 void *ccv, *cookie; 239{ 240 struct alpha_shared_intrhand *ih = cookie; 241 unsigned int irq = ih->ih_num; 242 int s; 243 244 s = splhigh(); 245 246 alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie, 247 "dec_1000 irq"); 248 if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) { 249 dec_1000_disable_intr(irq); 250 alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq, 251 IST_NONE); 252 scb_free(0x900 + SCB_IDXTOVEC(irq)); 253 } 254 255 splx(s); 256} 257 258void 259dec_1000_iointr(arg, vec) 260 void *arg; 261 unsigned long vec; 262{ 263 int irq; 264 265 irq = SCB_VECTOIDX(vec - 0x900); 266 267 if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) { 268 alpha_shared_intr_stray(dec_1000_pci_intr, irq, 269 "dec_1000 irq"); 270 if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq)) 271 dec_1000_disable_intr(irq); 272 } else 273 alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq); 274} 275 276/* 277 * Read and write the mystery ICU IMR registers 278 */ 279 280#define IR() bus_space_read_2(another_mystery_icu_iot, \ 281 another_mystery_icu_ioh, 0) 282 283#define IW(v) bus_space_write_2(another_mystery_icu_iot, \ 284 another_mystery_icu_ioh, 0, (v)) 285 286/* 287 * Enable and disable interrupts at the ICU level 288 */ 289 290void 291dec_1000_enable_intr(irq) 292 int irq; 293{ 294 IW(IR() | 1 << irq); 295} 296 297void 298dec_1000_disable_intr(irq) 299 int irq; 300{ 301 IW(IR() & ~(1 << irq)); 302} 303/* 304 * Initialize mystery ICU 305 */ 306void 307pci_1000_imi() 308{ 309 IW(0); /* XXX ?? */ 310} 311