pci_1000.c revision 1.2 
1/* $OpenBSD: pci_1000.c,v 1.2 2004/06/28 02:28:42 aaron Exp $ */
2/* $NetBSD: pci_1000.c,v 1.12 2001/07/27 00:25:20 thorpej Exp $ */
3
4/*
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
9 * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
10 * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
11 * Computer Systems, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 *    must display the following acknowledgement:
23 *	This product includes software developed by the NetBSD
24 *	Foundation, Inc. and its contributors.
25 * 4. Neither the name of The NetBSD Foundation nor the names of its
26 *    contributors may be used to endorse or promote products derived
27 *    from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42/*
43 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
44 * All rights reserved.
45 *
46 * Author: Chris G. Demetriou
47 *
48 * Permission to use, copy, modify and distribute this software and
49 * its documentation is hereby granted, provided that both the copyright
50 * notice and this permission notice appear in all copies of the
51 * software, derivative works or modified versions, and any portions
52 * thereof, and that both notices appear in supporting documentation.
53 *
54 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
55 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
56 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
57 *
58 * Carnegie Mellon requests users of this software to return to
59 *
60 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
61 *  School of Computer Science
62 *  Carnegie Mellon University
63 *  Pittsburgh PA 15213-3890
64 *
65 * any improvements or extensions that they make and grant Carnegie the
66 * rights to redistribute these changes.
67 */
68
69#include <sys/types.h>
70#include <sys/param.h>
71#include <sys/time.h>
72#include <sys/systm.h>
73#include <sys/errno.h>
74#include <sys/malloc.h>
75#include <sys/device.h>
76
77#include <uvm/uvm_extern.h>
78
79#include <machine/autoconf.h>
80
81#include <dev/pci/pcireg.h>
82#include <dev/pci/pcivar.h>
83
84#include <alpha/pci/pci_1000.h>
85
86#include "sio.h"
87#if NSIO > 0 || NPCEB > 0
88#include <alpha/pci/siovar.h>
89#endif
90
91static bus_space_tag_t another_mystery_icu_iot;
92static bus_space_handle_t another_mystery_icu_ioh;
93
94int	dec_1000_intr_map(void *, pcitag_t, int, int, pci_intr_handle_t *);
95const char *dec_1000_intr_string(void *, pci_intr_handle_t);
96int	dec_1000_intr_line(void *, pci_intr_handle_t);
97void	*dec_1000_intr_establish(void *, pci_intr_handle_t,
98	    int, int (*func)(void *), void *, char *);
99void	dec_1000_intr_disestablish(void *, void *);
100
101#define	PCI_NIRQ	16
102#define	PCI_STRAY_MAX	5
103
104struct alpha_shared_intr *dec_1000_pci_intr;
105
106void dec_1000_iointr(void *framep, unsigned long vec);
107void dec_1000_enable_intr(int irq);
108void dec_1000_disable_intr(int irq);
109void pci_1000_imi(void);
110static pci_chipset_tag_t pc_tag;
111
112void
113pci_1000_pickintr(core, iot, memt, pc)
114	void *core;
115	bus_space_tag_t iot, memt;
116	pci_chipset_tag_t pc;
117{
118#if 0
119	char *cp;
120#endif
121	int i;
122
123	another_mystery_icu_iot = iot;
124
125	pc_tag = pc;
126	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
127		panic("pci_1000_pickintr");
128        pc->pc_intr_v = core;
129        pc->pc_intr_map = dec_1000_intr_map;
130        pc->pc_intr_string = dec_1000_intr_string;
131	pc->pc_intr_line = dec_1000_intr_line;
132        pc->pc_intr_establish = dec_1000_intr_establish;
133        pc->pc_intr_disestablish = dec_1000_intr_disestablish;
134
135	pc->pc_pciide_compat_intr_establish = NULL;
136	pc->pc_pciide_compat_intr_disestablish = NULL;
137
138	dec_1000_pci_intr =
139	    alpha_shared_intr_alloc(PCI_NIRQ);
140	for (i = 0; i < PCI_NIRQ; i++) {
141		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
142		    PCI_STRAY_MAX);
143	}
144
145	pci_1000_imi();
146#if NSIO > 0 || NPCEB > 0
147	sio_intr_setup(pc, iot);
148#endif
149	set_iointr(dec_1000_iointr);
150}
151
152int
153dec_1000_intr_map(ccv, bustag, buspin, line, ihp)
154	void *ccv;
155	pcitag_t bustag;
156	int buspin, line;
157        pci_intr_handle_t *ihp;
158{
159	int	device;
160
161	if (buspin == 0)	/* No IRQ used. */
162		return 1;
163	if (!(1 <= buspin && buspin <= 4))
164		goto bad;
165
166	alpha_pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL);
167
168	switch(device) {
169	case 6:
170		if(buspin != 1)
171			break;
172		*ihp = 0xc;		/* integrated ncr scsi */
173		return 0;
174	case 11:
175	case 12:
176	case 13:
177		*ihp = (device - 11) * 4 + buspin - 1;
178		return 0;
179	}
180
181bad:	printf("dec_1000_intr_map: can't map dev %d pin %d\n", device, buspin);
182	return 1;
183}
184
185const char *
186dec_1000_intr_string(ccv, ih)
187	void *ccv;
188	pci_intr_handle_t ih;
189{
190	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
191        static char irqstr[sizeof irqmsg_fmt];
192
193        if (ih >= PCI_NIRQ)
194                panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih);
195
196        snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
197        return (irqstr);
198}
199
200int
201dec_1000_intr_line(ccv, ih)
202	void *ccv;
203	pci_intr_handle_t ih;
204{
205#if NSIO > 0
206	return sio_intr_line(NULL /*XXX*/, ih);
207#else
208	return (ih);
209#endif
210}
211
212void *
213dec_1000_intr_establish(ccv, ih, level, func, arg, name)
214        void *ccv;
215        pci_intr_handle_t ih;
216        int level;
217        int (*func)(void *);
218	void *arg;
219	char *name;
220{
221	void *cookie;
222
223        if (ih >= PCI_NIRQ)
224                panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih);
225
226	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
227	    level, func, arg, name);
228
229	if (cookie != NULL &&
230	    alpha_shared_intr_isactive(dec_1000_pci_intr, ih)) {
231		dec_1000_enable_intr(ih);
232	}
233	return (cookie);
234}
235
236void
237dec_1000_intr_disestablish(ccv, cookie)
238        void *ccv, *cookie;
239{
240	struct alpha_shared_intrhand *ih = cookie;
241	unsigned int irq = ih->ih_num;
242	int s;
243
244	s = splhigh();
245
246	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
247	    "dec_1000 irq");
248	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
249		dec_1000_disable_intr(irq);
250		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
251		    IST_NONE);
252	}
253
254	splx(s);
255}
256
257void
258dec_1000_iointr(framep, vec)
259	void *framep;
260	unsigned long vec;
261{
262	int irq;
263
264	if (vec >= 0x900) {
265		if (vec >= 0x900 + (PCI_NIRQ << 4))
266			panic("dec_1000_iointr: vec 0x%lx out of range", vec);
267		irq = (vec - 0x900) >> 4;
268
269		if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
270			alpha_shared_intr_stray(dec_1000_pci_intr, irq,
271			    "dec_1000 irq");
272			if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
273				dec_1000_disable_intr(irq);
274		}
275		return;
276	}
277#if NSIO > 0 || NPCEB > 0
278	if (vec >= 0x800) {
279		sio_iointr(framep, vec);
280		return;
281	}
282#endif
283	panic("dec_1000_intr: weird vec 0x%lx", vec);
284}
285
286/*
287 * Read and write the mystery ICU IMR registers
288 */
289
290#define	IR() bus_space_read_2(another_mystery_icu_iot,		\
291				another_mystery_icu_ioh, 0)
292
293#define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
294				another_mystery_icu_ioh, 0, (v))
295
296/*
297 * Enable and disable interrupts at the ICU level
298 */
299
300void
301dec_1000_enable_intr(irq)
302	int irq;
303{
304	IW(IR() | 1 << irq);
305}
306
307void
308dec_1000_disable_intr(irq)
309	int irq;
310{
311	IW(IR() & ~(1 << irq));
312}
313/*
314 * Initialize mystery ICU
315 */
316void
317pci_1000_imi()
318{
319	IW(0);					/* XXX ?? */
320}
321