ciareg.h revision 1.2 
1/*	$NetBSD: ciareg.h,v 1.1.4.3 1996/06/13 18:35:27 cgd Exp $	*/
2
3/*
4 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22 *  School of Computer Science
23 *  Carnegie Mellon University
24 *  Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30/*
31 * 21171 Chipset registers and constants.
32 *
33 * Taken from XXX
34 */
35
36#define	REGVAL(r)	(*(int32_t *)phystok0seg(r))
37
38/*
39 * Base addresses
40 */
41#define	CIA_PCI_SMEM1	0x8000000000L
42#define	CIA_PCI_SMEM2	0x8400000000L
43#define	CIA_PCI_SMEM3	0x8500000000L
44#define	CIA_PCI_SIO1	0x8580000000L
45#define	CIA_PCI_SIO2	0x85c0000000L
46#define	CIA_PCI_DENSE	0x8600000000L
47#define	CIA_PCI_CONF	0x8700000000L
48#define	CIA_PCI_IACK	0x8720000000L
49#define	CIA_CSRS	0x8740000000L
50#define	CIA_PCI_MC_CSRS	0x8750000000L
51#define	CIA_PCI_ATRANS	0x8760000000L
52
53/*
54 * General CSRs
55 */
56
57#define	CIA_CSR_HAE_MEM	(CIA_CSRS + 0x400)
58
59#define		HAE_MEM_REG1_START(x)	(((u_int32_t)(x) & 0xe0000000) << 0)
60#define		HAE_MEM_REG1_MASK	0x1fffffff
61#define		HAE_MEM_REG2_START(x)	(((u_int32_t)(x) & 0x0000f800) << 16)
62#define		HAE_MEM_REG2_MASK	0x07ffffff
63#define		HAE_MEM_REG3_START(x)	(((u_int32_t)(x) & 0x000000fc) << 16)
64#define		HAE_MEM_REG3_MASK	0x03ffffff
65
66#define	CIA_CSR_HAE_IO	(CIA_CSRS + 0x440)
67
68#define		HAE_IO_REG1_START(x)	0
69#define		HAE_IO_REG1_MASK	0x01ffffff
70#define		HAE_IO_REG2_START(x)	(((u_int32_t)(x) & 0xfe000000) << 0)
71#define		HAE_IO_REG2_MASK	0x01ffffff
72