cia_bus_mem.c revision 1.5 
1/*	$OpenBSD: cia_bus_mem.c,v 1.5 1996/12/08 00:20:36 niklas Exp $	*/
2/*	$NetBSD: cia_bus_mem.c,v 1.5 1996/08/27 16:29:26 cgd Exp $	*/
3
4/*
5 * Copyright (c) 1996 Carnegie-Mellon University.
6 * All rights reserved.
7 *
8 * Author: Chris G. Demetriou
9 *
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
23 *  School of Computer Science
24 *  Carnegie Mellon University
25 *  Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/malloc.h>
34#include <sys/syslog.h>
35#include <sys/device.h>
36#include <vm/vm.h>
37
38#include <machine/bus.h>
39
40#include <alpha/pci/ciareg.h>
41#include <alpha/pci/ciavar.h>
42
43#define	CHIP		cia
44
45/* Dense region 1 */
46#define	CHIP_D_MEM_W1_START(v)	0x00000000
47#define	CHIP_D_MEM_W1_END(v)	0xffffffff
48#define	CHIP_D_MEM_W1_BASE(v)	CIA_PCI_DENSE
49#define	CHIP_D_MEM_W1_MASK(v)	0xffffffff
50
51/* Sparse region 1 */
52#define	CHIP_S_MEM_W1_START(v)						\
53	    HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
54#define	CHIP_S_MEM_W1_END(v)						\
55	    (CHIP_S_MEM_W1_START(v) + HAE_MEM_REG1_MASK)
56#define	CHIP_S_MEM_W1_BASE(v)						\
57	    CIA_PCI_SMEM1
58#define	CHIP_S_MEM_W1_MASK(v)						\
59	    HAE_MEM_REG1_MASK
60
61/* Sparse region 2 */
62#define	CHIP_S_MEM_W2_START(v)						\
63	    HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
64#define	CHIP_S_MEM_W2_END(v)						\
65	    (CHIP_S_MEM_W2_START(v) + HAE_MEM_REG2_MASK)
66#define	CHIP_S_MEM_W2_BASE(v)						\
67	    CIA_PCI_SMEM2
68#define	CHIP_S_MEM_W2_MASK(v)						\
69	    HAE_MEM_REG2_MASK
70
71/* Sparse region 3 */
72#define	CHIP_S_MEM_W3_START(v)						\
73	    HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
74#define	CHIP_S_MEM_W3_END(v)						\
75	    (CHIP_S_MEM_W3_START(v) + HAE_MEM_REG3_MASK)
76#define	CHIP_S_MEM_W3_BASE(v)						\
77	    CIA_PCI_SMEM3
78#define	CHIP_S_MEM_W3_MASK(v)						\
79	    HAE_MEM_REG3_MASK
80
81#include "pcs_bus_mem_common.c"
82