cia_bus_mem.c revision 1.2
1/* $OpenBSD: cia_bus_mem.c,v 1.2 1996/07/29 23:00:19 niklas Exp $ */ 2/* $NetBSD: cia_bus_mem.c,v 1.2.4.2 1996/06/13 18:15:01 cgd Exp $ */ 3 4/* 5 * Copyright (c) 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31#include <sys/param.h> 32#include <sys/malloc.h> 33#include <sys/syslog.h> 34#include <sys/device.h> 35#include <vm/vm.h> 36 37#include <machine/bus.h> 38 39#include <alpha/pci/ciareg.h> 40#include <alpha/pci/ciavar.h> 41 42#define CHIP cia 43 44/* Dense region 1 */ 45#define CHIP_D_MEM_W1_START(v) 0x00000000 46#define CHIP_D_MEM_W1_END(v) 0xffffffff 47#define CHIP_D_MEM_W1_BASE(v) CIA_PCI_DENSE 48#define CHIP_D_MEM_W1_MASK(v) 0xffffffff 49 50/* Sparse region 1 */ 51#define CHIP_S_MEM_W1_START(v) \ 52 HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem) 53#define CHIP_S_MEM_W1_END(v) \ 54 (CHIP_S_MEM_W1_START(v) + HAE_MEM_REG1_MASK) 55#define CHIP_S_MEM_W1_BASE(v) \ 56 CIA_PCI_SMEM1 57#define CHIP_S_MEM_W1_MASK(v) \ 58 HAE_MEM_REG1_MASK 59 60/* Sparse region 2 */ 61#define CHIP_S_MEM_W2_START(v) \ 62 HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem) 63#define CHIP_S_MEM_W2_END(v) \ 64 (CHIP_S_MEM_W2_START(v) + HAE_MEM_REG2_MASK) 65#define CHIP_S_MEM_W2_BASE(v) \ 66 CIA_PCI_SMEM2 67#define CHIP_S_MEM_W2_MASK(v) \ 68 HAE_MEM_REG2_MASK 69 70/* Sparse region 3 */ 71#define CHIP_S_MEM_W3_START(v) \ 72 HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem) 73#define CHIP_S_MEM_W3_END(v) \ 74 (CHIP_S_MEM_W3_START(v) + HAE_MEM_REG3_MASK) 75#define CHIP_S_MEM_W3_BASE(v) \ 76 CIA_PCI_SMEM3 77#define CHIP_S_MEM_W3_MASK(v) \ 78 HAE_MEM_REG3_MASK 79 80#include "pcs_bus_mem_common.c" 81