1/* Standard register usage. */ 2 3/* Number of actual hardware registers. 4 The hardware registers are assigned numbers for the compiler 5 from 0 to just below FIRST_PSEUDO_REGISTER. 6 All registers that the compiler knows about must be given numbers, 7 even those that are not normally considered general registers. 8 9 HP-PA 1.0 has 32 fullword registers and 16 floating point 10 registers. The floating point registers hold either word or double 11 word values. 12 13 16 additional registers are reserved. 14 15 HP-PA 1.1 has 32 fullword registers and 32 floating point 16 registers. However, the floating point registers behave 17 differently: the left and right halves of registers are addressable 18 as 32 bit registers. So, we will set things up like the 68k which 19 has different fp units: define separate register sets for the 1.0 20 and 1.1 fp units. */ 21 22#define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs + 23 + 1 shift reg */ 24 25/* 1 for registers that have pervasive standard uses 26 and are not available for the register allocator. 27 28 On the HP-PA, these are: 29 Reg 0 = 0 (hardware). However, 0 is used for condition code, 30 so is not fixed. 31 Reg 1 = ADDIL target/Temporary (hardware). 32 Reg 2 = Return Pointer 33 Reg 3 = Frame Pointer 34 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) 35 Reg 4-18 = Preserved Registers 36 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. 37 Reg 20-22 = Temporary Registers 38 Reg 23-26 = Temporary/Parameter Registers 39 Reg 27 = Global Data Pointer (hp) 40 Reg 28 = Temporary/Return Value register 41 Reg 29 = Temporary/Static Chain/Return Value register #2 42 Reg 30 = stack pointer 43 Reg 31 = Temporary/Millicode Return Pointer (hp) 44 45 Freg 0-3 = Status Registers -- Not known to the compiler. 46 Freg 4-7 = Arguments/Return Value 47 Freg 8-11 = Temporary Registers 48 Freg 12-15 = Preserved Registers 49 50 Freg 16-31 = Reserved 51 52 On the Snake, fp regs are 53 54 Freg 0-3 = Status Registers -- Not known to the compiler. 55 Freg 4L-7R = Arguments/Return Value 56 Freg 8L-11R = Temporary Registers 57 Freg 12L-21R = Preserved Registers 58 Freg 22L-31R = Temporary Registers 59 60*/ 61 62#define FIXED_REGISTERS \ 63 {0, 0, 0, 0, 0, 0, 0, 0, \ 64 0, 0, 0, 0, 0, 0, 0, 0, \ 65 0, 0, 0, 0, 0, 0, 0, 0, \ 66 0, 0, 0, 1, 0, 0, 1, 0, \ 67 /* fp registers */ \ 68 0, 0, 0, 0, 0, 0, 0, 0, \ 69 0, 0, 0, 0, 0, 0, 0, 0, \ 70 0, 0, 0, 0, 0, 0, 0, 0, \ 71 0, 0, 0, 0, 0, 0, 0, 0, \ 72 0, 0, 0, 0, 0, 0, 0, 0, \ 73 0, 0, 0, 0, 0, 0, 0, 0, \ 74 0, 0, 0, 0, 0, 0, 0, 0, \ 75 0} 76 77/* 1 for registers not available across function calls. 78 These must include the FIXED_REGISTERS and also any 79 registers that can be used without being saved. 80 The latter must include the registers where values are returned 81 and the register where structure-value addresses are passed. 82 Aside from that, you can include as many other registers as you like. */ 83#define CALL_USED_REGISTERS \ 84 {1, 1, 1, 0, 0, 0, 0, 0, \ 85 0, 0, 0, 0, 0, 0, 0, 0, \ 86 0, 0, 0, 1, 1, 1, 1, 1, \ 87 1, 1, 1, 1, 1, 1, 1, 1, \ 88 /* fp registers */ \ 89 1, 1, 1, 1, 1, 1, 1, 1, \ 90 1, 1, 1, 1, 1, 1, 1, 1, \ 91 0, 0, 0, 0, 0, 0, 0, 0, \ 92 0, 0, 0, 0, 0, 0, 0, 0, \ 93 0, 0, 0, 0, 1, 1, 1, 1, \ 94 1, 1, 1, 1, 1, 1, 1, 1, \ 95 1, 1, 1, 1, 1, 1, 1, 1, \ 96 1} 97 98#define CONDITIONAL_REGISTER_USAGE \ 99{ \ 100 int i; \ 101 if (!TARGET_PA_11) \ 102 { \ 103 for (i = 56; i < 88; i++) \ 104 fixed_regs[i] = call_used_regs[i] = 1; \ 105 for (i = 33; i < 88; i += 2) \ 106 fixed_regs[i] = call_used_regs[i] = 1; \ 107 } \ 108 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\ 109 { \ 110 for (i = 32; i < 88; i++) \ 111 fixed_regs[i] = call_used_regs[i] = 1; \ 112 } \ 113 if (flag_pic) \ 114 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 115} 116 117/* Allocate the call used registers first. This should minimize 118 the number of registers that need to be saved (as call used 119 registers will generally not be allocated across a call). 120 121 Experimentation has shown slightly better results by allocating 122 FP registers first. 123 124 FP registers are ordered so that all L registers are selected before 125 R registers. This works around a false dependency interlock on the 126 PA8000 when accessing the high and low parts of an FP register 127 independently. */ 128 129#define REG_ALLOC_ORDER \ 130 { \ 131 /* caller-saved fp regs. */ \ 132 68, 70, 72, 74, 76, 78, 80, 82, \ 133 84, 86, 40, 42, 44, 46, 32, 34, \ 134 36, 38, \ 135 69, 71, 73, 75, 77, 79, 81, 83, \ 136 85, 87, 41, 43, 45, 47, 33, 35, \ 137 37, 39, \ 138 /* caller-saved general regs. */ \ 139 19, 20, 21, 22, 23, 24, 25, 26, \ 140 27, 28, 29, 31, 2, \ 141 /* callee-saved fp regs. */ \ 142 48, 50, 52, 54, 56, 58, 60, 62, \ 143 64, 66, \ 144 49, 51, 53, 55, 57, 59, 61, 63, \ 145 65, 67, \ 146 /* callee-saved general regs. */ \ 147 3, 4, 5, 6, 7, 8, 9, 10, \ 148 11, 12, 13, 14, 15, 16, 17, 18, \ 149 /* special registers. */ \ 150 1, 30, 0, 88} 151 152 153/* Return number of consecutive hard regs needed starting at reg REGNO 154 to hold something of mode MODE. 155 This is ordinarily the length in words of a value of mode MODE 156 but can be less for certain modes in special long registers. 157 158 On the HP-PA, ordinary registers hold 32 bits worth; 159 The floating point registers are 64 bits wide. Snake fp regs are 32 160 bits wide */ 161#define HARD_REGNO_NREGS(REGNO, MODE) \ 162 (FP_REGNO_P (REGNO) \ 163 ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ 164 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 165 166/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 167 On the HP-PA, the cpu registers can hold any mode. For DImode, we 168 choose a set of general register that includes the incoming arguments 169 and the return value. We specify a set with no overlaps so that we don't 170 have to specify that the destination register in patterns using this mode 171 is an early clobber. */ 172#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 173 ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \ 174 /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \ 175 : !TARGET_PA_11 && FP_REGNO_P (REGNO) \ 176 ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \ 177 : FP_REGNO_P (REGNO) \ 178 ? GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0 \ 179 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ 180 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ 181 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ 182 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ 183 && (((REGNO) & 3) == 3 && (REGNO) <= 23)))) 184 185/* How to renumber registers for dbx and gdb. 186 187 Registers 0 - 31 remain unchanged. 188 189 Registers 32 - 87 are mapped to 72 - 127 190 191 Register 88 is mapped to 32. */ 192 193#define DBX_REGISTER_NUMBER(REGNO) \ 194 ((REGNO) <= 31 ? (REGNO) : \ 195 ((REGNO) <= 87 ? (REGNO) + 40 : 32)) 196 197/* We must not use the DBX register numbers for the DWARF 2 CFA column 198 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 199 Instead use the identity mapping. */ 200#define DWARF_FRAME_REGNUM(REG) REG 201 202/* Define the classes of registers for register constraints in the 203 machine description. Also define ranges of constants. 204 205 One of the classes must always be named ALL_REGS and include all hard regs. 206 If there is more than one class, another class must be named NO_REGS 207 and contain no registers. 208 209 The name GENERAL_REGS must be the name of a class (or an alias for 210 another name such as ALL_REGS). This is the class of registers 211 that is allowed by "g" or "r" in a register constraint. 212 Also, registers outside this class are allocated only when 213 instructions express preferences for them. 214 215 The classes must be numbered in nondecreasing order; that is, 216 a larger-numbered class must never be contained completely 217 in a smaller-numbered class. 218 219 For any two classes, it is very desirable that there be another 220 class that represents their union. */ 221 222 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, 223 1.1 fp regs, and the high 1.1 fp regs, to which the operands of 224 fmpyadd and fmpysub are restricted. */ 225 226enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, 227 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; 228 229#define N_REG_CLASSES (int) LIM_REG_CLASSES 230 231/* Give names of register classes as strings for dump file. */ 232 233#define REG_CLASS_NAMES \ 234 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \ 235 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} 236 237/* Define which registers fit in which classes. 238 This is an initializer for a vector of HARD_REG_SET 239 of length N_REG_CLASSES. Register 0, the "condition code" register, 240 is in no class. */ 241 242#define REG_CLASS_CONTENTS \ 243 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \ 244 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \ 245 {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \ 246 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \ 247 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \ 248 {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \ 249 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ 250 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ 251 252/* Return the class number of the smallest class containing 253 reg number REGNO. This could be a conditional expression 254 or could index an array. */ 255 256#define REGNO_REG_CLASS(REGNO) \ 257 ((REGNO) == 0 ? NO_REGS \ 258 : (REGNO) == 1 ? R1_REGS \ 259 : (REGNO) < 32 ? GENERAL_REGS \ 260 : (REGNO) < 56 ? FP_REGS \ 261 : (REGNO) < 88 ? FPUPPER_REGS \ 262 : SHIFT_REGS) 263 264/* Get reg_class from a letter such as appears in the machine description. */ 265/* Keep 'x' for backward compatibility with user asm. */ 266#define REG_CLASS_FROM_LETTER(C) \ 267 ((C) == 'f' ? FP_REGS : \ 268 (C) == 'y' ? FPUPPER_REGS : \ 269 (C) == 'x' ? FP_REGS : \ 270 (C) == 'q' ? SHIFT_REGS : \ 271 (C) == 'a' ? R1_REGS : \ 272 (C) == 'Z' ? ALL_REGS : NO_REGS) 273 274/* Return the maximum number of consecutive registers 275 needed to represent mode MODE in a register of class CLASS. */ 276#define CLASS_MAX_NREGS(CLASS, MODE) \ 277 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \ 278 ? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ 279 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 280 281/* 1 if N is a possible register number for function argument passing. */ 282 283#define FUNCTION_ARG_REGNO_P(N) \ 284 (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) 285 286/* How to refer to registers in assembler output. 287 This sequence is indexed by compiler's hard-register-number (see above). */ 288 289#define REGISTER_NAMES \ 290{"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 291 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 292 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ 293 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ 294 "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \ 295 "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \ 296 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \ 297 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \ 298 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \ 299 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \ 300 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \ 301 "SAR"} 302 303#define ADDITIONAL_REGISTER_NAMES \ 304{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \ 305 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \ 306 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \ 307 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \ 308 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \ 309 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \ 310 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \ 311 {"%cr11",88}} 312 313#define FP_SAVED_REG_LAST 66 314#define FP_SAVED_REG_FIRST 48 315#define FP_REG_STEP 2 316#define FP_REG_FIRST 32 317#define FP_REG_LAST 87 318