1# $OpenBSD: Makefile,v 1.7 2023/11/11 18:35:36 robert Exp $
2
3LIB=	LLVMAMDGPUCodeGen
4NOPROFILE=
5
6CPPFLAGS+=	-I${.OBJDIR}/../include/llvm/AMDGPU \
7		-I${LLVM_SRCS}/lib/Target/AMDGPU
8
9SRCS+=	AMDGPUAliasAnalysis.cpp \
10	AMDGPUAlwaysInlinePass.cpp \
11	AMDGPUAnnotateKernelFeatures.cpp \
12	AMDGPUAnnotateUniformValues.cpp \
13	AMDGPUArgumentUsageInfo.cpp \
14	AMDGPUAsmPrinter.cpp \
15	AMDGPUAtomicOptimizer.cpp \
16	AMDGPUAttributor.cpp \
17	AMDGPUCallLowering.cpp \
18	AMDGPUCodeGenPrepare.cpp \
19	AMDGPUCombinerHelper.cpp \
20	AMDGPUCtorDtorLowering.cpp \
21	AMDGPUExportClustering.cpp \
22	AMDGPUFrameLowering.cpp \
23	AMDGPUGlobalISelUtils.cpp \
24	AMDGPUHSAMetadataStreamer.cpp \
25	AMDGPUInsertDelayAlu.cpp \
26	AMDGPUInstCombineIntrinsic.cpp \
27	AMDGPUInstrInfo.cpp \
28	AMDGPUInstructionSelector.cpp \
29	AMDGPUISelDAGToDAG.cpp \
30	AMDGPUISelLowering.cpp \
31	AMDGPULateCodeGenPrepare.cpp \
32	AMDGPULegalizerInfo.cpp \
33	AMDGPULibCalls.cpp \
34	AMDGPULibFunc.cpp \
35	AMDGPULowerIntrinsics.cpp \
36	AMDGPULowerKernelArguments.cpp \
37	AMDGPULowerKernelAttributes.cpp \
38	AMDGPULowerModuleLDSPass.cpp \
39	AMDGPUMachineCFGStructurizer.cpp \
40	AMDGPUMachineFunction.cpp \
41	AMDGPUMachineModuleInfo.cpp \
42	AMDGPUMacroFusion.cpp \
43	AMDGPUMCInstLower.cpp \
44	AMDGPUIGroupLP.cpp \
45	AMDGPUMIRFormatter.cpp \
46	AMDGPUOpenCLEnqueuedBlockLowering.cpp \
47	AMDGPUPerfHintAnalysis.cpp \
48	AMDGPUPostLegalizerCombiner.cpp \
49	AMDGPUPreLegalizerCombiner.cpp \
50	AMDGPUPrintfRuntimeBinding.cpp \
51	AMDGPUPromoteAlloca.cpp \
52	AMDGPUPropagateAttributes.cpp \
53	AMDGPUPromoteKernelArguments.cpp \
54	AMDGPURegBankCombiner.cpp \
55	AMDGPURegisterBankInfo.cpp \
56	AMDGPUReleaseVGPRs.cpp \
57	AMDGPUReplaceLDSUseWithPointer.cpp \
58	AMDGPUResourceUsageAnalysis.cpp \
59	AMDGPURewriteOutArguments.cpp \
60	AMDGPURewriteUndefForPHI.cpp \
61	AMDGPUSetWavePriority.cpp \
62	AMDGPUSubtarget.cpp \
63	AMDGPUTargetMachine.cpp \
64	AMDGPUTargetObjectFile.cpp \
65	AMDGPUTargetTransformInfo.cpp \
66	AMDGPUUnifyDivergentExitNodes.cpp \
67	AMDGPUUnifyMetadata.cpp \
68	R600MachineCFGStructurizer.cpp \
69	GCNCreateVOPD.cpp \
70	GCNDPPCombine.cpp \
71	GCNHazardRecognizer.cpp \
72	GCNILPSched.cpp \
73	GCNIterativeScheduler.cpp \
74	GCNMinRegStrategy.cpp \
75	GCNNSAReassign.cpp \
76	GCNPreRAOptimizations.cpp \
77	GCNRegPressure.cpp \
78	GCNSchedStrategy.cpp \
79	GCNVOPDUtils.cpp \
80	R600AsmPrinter.cpp \
81	R600ClauseMergePass.cpp \
82	R600ControlFlowFinalizer.cpp \
83	R600EmitClauseMarkers.cpp \
84	R600ExpandSpecialInstrs.cpp \
85	R600FrameLowering.cpp \
86	R600InstrInfo.cpp \
87	R600ISelDAGToDAG.cpp \
88	R600ISelLowering.cpp \
89	R600MachineFunctionInfo.cpp \
90	R600MachineScheduler.cpp \
91	R600MCInstLower.cpp \
92	R600OpenCLImageTypeLoweringPass.cpp \
93	R600OptimizeVectorRegisters.cpp \
94	R600Packetizer.cpp \
95	R600RegisterInfo.cpp \
96	R600Subtarget.cpp \
97	R600TargetMachine.cpp \
98	R600TargetTransformInfo.cpp \
99	SIAnnotateControlFlow.cpp \
100	SIFixSGPRCopies.cpp \
101	SIFixVGPRCopies.cpp \
102	SIFoldOperands.cpp \
103	SIFormMemoryClauses.cpp \
104	SIFrameLowering.cpp \
105	SIInsertHardClauses.cpp \
106	SIInsertWaitcnts.cpp \
107	SIInstrInfo.cpp \
108	SIISelLowering.cpp \
109	SILateBranchLowering.cpp \
110	SILoadStoreOptimizer.cpp \
111	SILowerControlFlow.cpp \
112	SILowerI1Copies.cpp \
113	SILowerSGPRSpills.cpp \
114	SIMachineFunctionInfo.cpp \
115	SIMachineScheduler.cpp \
116	SIMemoryLegalizer.cpp \
117	SIModeRegister.cpp \
118	SIOptimizeExecMasking.cpp \
119	SIOptimizeExecMaskingPreRA.cpp \
120	SIOptimizeVGPRLiveRange.cpp \
121	SIPeepholeSDWA.cpp \
122	SIPostRABundler.cpp \
123	SIPreAllocateWWMRegs.cpp \
124	SIPreEmitPeephole.cpp \
125	SIProgramInfo.cpp \
126	SIRegisterInfo.cpp \
127	SIShrinkInstructions.cpp \
128	SIWholeQuadMode.cpp
129
130.PATH:	${.CURDIR}/../../../llvm/llvm/lib/Target/AMDGPU
131