Makefile revision 1.8 
1# $OpenBSD: Makefile,v 1.8 2021/04/28 12:55:38 patrick Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7DEFS=	Attributes.inc \
8	IntrinsicImpl.inc \
9	IntrinsicEnums.inc \
10	IntrinsicsAArch64.h \
11	IntrinsicsAMDGPU.h \
12	IntrinsicsARM.h \
13	IntrinsicsBPF.h \
14	IntrinsicsHexagon.h \
15	IntrinsicsMips.h \
16	IntrinsicsNVPTX.h \
17	IntrinsicsPowerPC.h \
18	IntrinsicsR600.h \
19	IntrinsicsRISCV.h \
20	IntrinsicsS390.h \
21	IntrinsicsWebAssembly.h \
22	IntrinsicsX86.h \
23	IntrinsicsXCore.h
24
25INCDIR=	/usr/include/llvm/IR
26
27all: ${DEFS}
28
29clean cleandir:
30	rm -f ${DEFS}
31
32Attributes.inc: ${LLVM_SRCS}/include/llvm/IR/Attributes.td
33	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-attrs \
34		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
35		-I${LLVM_SRCS}/include \
36		-o ${.TARGET} ${.ALLSRC}
37
38IntrinsicImpl.inc: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
39	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-impl \
40		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
41		-I${LLVM_SRCS}/include \
42		-o ${.TARGET} ${.ALLSRC}
43
44IntrinsicEnums.inc: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
45	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums \
46		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
47		-I${LLVM_SRCS}/include \
48		-o ${.TARGET} ${.ALLSRC}
49
50IntrinsicsAArch64.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
51	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=aarch64 \
52		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
53		-I${LLVM_SRCS}/include \
54		-o ${.TARGET} ${.ALLSRC}
55
56IntrinsicsAMDGPU.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
57	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=amdgcn \
58		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
59		-I${LLVM_SRCS}/include \
60		-o ${.TARGET} ${.ALLSRC}
61
62IntrinsicsARM.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
63	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=arm \
64		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
65		-I${LLVM_SRCS}/include \
66		-o ${.TARGET} ${.ALLSRC}
67
68IntrinsicsBPF.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
69	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=bpf \
70		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
71		-I${LLVM_SRCS}/include \
72		-o ${.TARGET} ${.ALLSRC}
73
74IntrinsicsHexagon.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
75	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=hexagon \
76		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
77		-I${LLVM_SRCS}/include \
78		-o ${.TARGET} ${.ALLSRC}
79
80IntrinsicsMips.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
81	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=mips \
82		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
83		-I${LLVM_SRCS}/include \
84		-o ${.TARGET} ${.ALLSRC}
85
86IntrinsicsNVPTX.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
87	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=nvvm \
88		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
89		-I${LLVM_SRCS}/include \
90		-o ${.TARGET} ${.ALLSRC}
91
92IntrinsicsPowerPC.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
93	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=ppc \
94		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
95		-I${LLVM_SRCS}/include \
96		-o ${.TARGET} ${.ALLSRC}
97
98IntrinsicsR600.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
99	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=r600 \
100		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
101		-I${LLVM_SRCS}/include \
102		-o ${.TARGET} ${.ALLSRC}
103
104IntrinsicsRISCV.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
105	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=riscv \
106		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
107		-I${LLVM_SRCS}/include \
108		-o ${.TARGET} ${.ALLSRC}
109
110IntrinsicsS390.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
111	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=s390 \
112		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
113		-I${LLVM_SRCS}/include \
114		-o ${.TARGET} ${.ALLSRC}
115
116IntrinsicsWebAssembly.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
117	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=wasm \
118		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
119		-I${LLVM_SRCS}/include \
120		-o ${.TARGET} ${.ALLSRC}
121
122IntrinsicsX86.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
123	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=x86 \
124		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
125		-I${LLVM_SRCS}/include \
126		-o ${.TARGET} ${.ALLSRC}
127
128IntrinsicsXCore.h: ${LLVM_SRCS}/include/llvm/IR/Intrinsics.td
129	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-intrinsic-enums -intrinsic-prefix=xcore \
130		-I${LLVM_SRCS}/include/llvm/IR -I${LLVM_SRCS}/lib/Target \
131		-I${LLVM_SRCS}/include \
132		-o ${.TARGET} ${.ALLSRC}
133
134install includes: ${DEFS}
135	${INSTALL} -d -m 755 ${DESTDIR}${INCDIR}
136	@cd ${.OBJDIR}; for i in $(DEFS); do \
137	    j="cmp -s $$i ${DESTDIR}${INCDIR}/$$i || \
138		${INSTALL} ${INSTALL_COPY} -o ${BINOWN} -g ${BINGRP} \
139		-m 444 $$i ${DESTDIR}${INCDIR}"; \
140	    echo $$j; \
141	    eval "$$j"; \
142	done
143
144.include <bsd.obj.mk>
145