1/* regPacket.h - register packet definitions for rdb */ 2 3/* Copyright 1992-1993 Wind River Systems, Inc. */ 4 5/* 6modification history 7-------------------- 801d,30nov93,pad Added Am29K target definitions. 901c,14jun93,maf additional definitions for documentation purposes. 10 fixed reversal of MIPS_R_LO and MIPS_R_HI. 1101b,08feb93,scy added SPARC target definitions. changed to WRS code convetion. 1201a,20feb92,j_w created. 13*/ 14 15#ifndef __INCregPacketh 16#define __INCregPacketh 17 18 19/* MC68K */ 20 21#define MC68K_GREG_SIZE 0x04 /* size of general-purpose reg */ 22#define MC68K_GREG_PLEN 0x48 /* size of general-purpose reg block */ 23 24/* offsets into general-purpose register block */ 25 26#define MC68K_R_D0 0x00 /* d0; d1 - d7 follow in sequence */ 27#define MC68K_R_A0 0x20 /* a0; a1 - a7 follow in sequence */ 28#define MC68K_R_SR 0x40 /* sr (represented as a 4-byte val) */ 29#define MC68K_R_PC 0x44 /* pc */ 30 31#define MC68K_FPREG_SIZE 0x0c /* size of floating-point data reg */ 32#define MC68K_FPREG_PLEN 0x6c /* size of floating-point reg block */ 33 34/* offsets into floating-point register block */ 35 36#define MC68K_R_FP0 0x00 /* fp0; fp1 - fp7 follow in sequence */ 37#define MC68K_R_FPCR 0x60 /* fpcr */ 38#define MC68K_R_FPSR 0x64 /* fpsr */ 39#define MC68K_R_FPIAR 0x68 /* fpiar */ 40 41 42/* I960 */ 43 44#define I960_GREG_SIZE 0x04 /* size of general-purpose reg */ 45#define I960_GREG_PLEN 0x8c /* size of general-purpose reg block */ 46 47/* offsets into general-purpose register block */ 48 49#define I960_R_R0 0x00 /* r0; r1 - r15 follow in sequence */ 50#define I960_R_G0 0x40 /* g0; g1 - g15 follow in sequence */ 51#define I960_R_PCW 0x80 /* pcw */ 52#define I960_R_ACW 0x84 /* acw */ 53#define I960_R_TCW 0x88 /* tcw */ 54 55#define I960_FPREG_SIZE 0x10 /* size of floating-point reg */ 56#define I960_FPREG_PLEN 0x28 /* size of floating-point reg block */ 57 58/* offsets into floating-point register block */ 59 60#define I960_R_FP0 0x00 /* fp0; fp1 - fp3 follow in sequence */ 61 62 63/* SPARC */ 64 65#define SPARC_GREG_SIZE 0x04 /* size of general-purpose reg */ 66#define SPARC_GREG_PLEN 0x98 /* size of general-purpose reg block */ 67 68/* offsets into general-purpose register block */ 69 70#define SPARC_R_G0 0x00 /* g0; g1 - g7 follow in sequence */ 71#define SPARC_R_O0 0x20 /* o0; o1 - o7 follow in sequence */ 72#define SPARC_R_L0 0x40 /* l0; l1 - l7 follow in sequence */ 73#define SPARC_R_I0 0x60 /* i0; i1 - i7 follow in sequence */ 74#define SPARC_R_Y 0x80 /* y */ 75#define SPARC_R_PSR 0x84 /* psr */ 76#define SPARC_R_WIM 0x88 /* wim */ 77#define SPARC_R_TBR 0x8c /* tbr */ 78#define SPARC_R_PC 0x90 /* pc */ 79#define SPARC_R_NPC 0x94 /* npc */ 80 81#define SPARC_FPREG_SIZE 0x04 /* size of floating-point reg */ 82#define SPARC_FPREG_PLEN 0x84 /* size of floating-point reg block */ 83 84/* offsets into floating-point register block */ 85 86#define SPARC_R_FP0 0x00 /* f0; f1 - f31 follow in sequence */ 87#define SPARC_R_FSR 0x80 /* fsr */ 88 89 90/* MIPS */ 91 92#define MIPS_GREG_SIZE 0x04 /* size of general-purpose reg */ 93#define MIPS_GREG_PLEN 0x90 /* size of general-purpose reg block */ 94 95/* offsets into general-purpose register block */ 96 97#define MIPS_R_GP0 0x00 /* gp0 (zero) */ 98#define MIPS_R_AT 0x04 /* at */ 99#define MIPS_R_V0 0x08 /* v0 */ 100#define MIPS_R_V1 0x0c /* v1 */ 101#define MIPS_R_A0 0x10 /* a0 */ 102#define MIPS_R_A1 0x14 /* a1 */ 103#define MIPS_R_A2 0x18 /* a2 */ 104#define MIPS_R_A3 0x1c /* a3 */ 105#define MIPS_R_T0 0x20 /* t0 */ 106#define MIPS_R_T1 0x24 /* t1 */ 107#define MIPS_R_T2 0x28 /* t2 */ 108#define MIPS_R_T3 0x2c /* t3 */ 109#define MIPS_R_T4 0x30 /* t4 */ 110#define MIPS_R_T5 0x34 /* t5 */ 111#define MIPS_R_T6 0x38 /* t6 */ 112#define MIPS_R_T7 0x3c /* t7 */ 113#define MIPS_R_S0 0x40 /* s0 */ 114#define MIPS_R_S1 0x44 /* s1 */ 115#define MIPS_R_S2 0x48 /* s2 */ 116#define MIPS_R_S3 0x4c /* s3 */ 117#define MIPS_R_S4 0x50 /* s4 */ 118#define MIPS_R_S5 0x54 /* s5 */ 119#define MIPS_R_S6 0x58 /* s6 */ 120#define MIPS_R_S7 0x5c /* s7 */ 121#define MIPS_R_T8 0x60 /* t8 */ 122#define MIPS_R_T9 0x64 /* t9 */ 123#define MIPS_R_K0 0x68 /* k0 */ 124#define MIPS_R_K1 0x6c /* k1 */ 125#define MIPS_R_GP 0x70 /* gp */ 126#define MIPS_R_SP 0x74 /* sp */ 127#define MIPS_R_S8 0x78 /* s8 */ 128#define MIPS_R_LO 0x80 /* lo */ 129#define MIPS_R_HI 0x84 /* hi */ 130#define MIPS_R_SR 0x88 /* sr */ 131#define MIPS_R_PC 0x8c /* pc */ 132 133#define MIPS_FPREG_SIZE 0x04 /* size of floating-point data reg */ 134#define MIPS_FPREG_PLEN 0x84 /* size of floating-point reg block */ 135 136/* offsets into floating-point register block */ 137 138#define MIPS_R_FP0 0x00 /* f0; f1 - f31 follow in sequence */ 139#define MIPS_R_FPCSR 0x80 /* offset of fpcsr in reg block */ 140 141 142/* General registers for the Am29k */ 143 144#define AM29K_GREG_SIZE 0x04 145#define AM29K_GREG_PLEN 0x2d4 146 147#define AM29K_R_GR96 0x0 148#define AM29K_R_VAB 0x280 149#define AM29K_R_INTE 0x2bc 150#define AM29K_R_RSP 0x2c0 151 152/* Floating Point registers for the Am29k */ 153 154#define AM29K_FPREG_SIZE 0x04 155#define AM29K_FPREG_PLEN 0x8 156 157#define AM29K_R_FPE 0x0 158#define AM29K_R_FPS 0x4 159 160#endif /* __INCregPacketh */ 161