1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend is responsible for emitting a description of the target
10// instruction set for the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#include "CodeGenDAGPatterns.h"
15#include "CodeGenInstruction.h"
16#include "CodeGenSchedule.h"
17#include "CodeGenTarget.h"
18#include "PredicateExpander.h"
19#include "SequenceToOffsetTable.h"
20#include "SubtargetFeatureInfo.h"
21#include "TableGenBackends.h"
22#include "Types.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringExtras.h"
26#include "llvm/Support/Casting.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/TableGen/Error.h"
29#include "llvm/TableGen/Record.h"
30#include "llvm/TableGen/TableGenBackend.h"
31#include <cassert>
32#include <cstdint>
33#include <iterator>
34#include <map>
35#include <string>
36#include <utility>
37#include <vector>
38
39using namespace llvm;
40
41cl::OptionCategory InstrInfoEmitterCat("Options for -gen-instr-info");
42static cl::opt<bool> ExpandMIOperandInfo(
43    "instr-info-expand-mi-operand-info",
44    cl::desc("Expand operand's MIOperandInfo DAG into suboperands"),
45    cl::cat(InstrInfoEmitterCat), cl::init(true));
46
47namespace {
48
49class InstrInfoEmitter {
50  RecordKeeper &Records;
51  CodeGenDAGPatterns CDP;
52  const CodeGenSchedModels &SchedModels;
53
54public:
55  InstrInfoEmitter(RecordKeeper &R):
56    Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
57
58  // run - Output the instruction set description.
59  void run(raw_ostream &OS);
60
61private:
62  void emitEnums(raw_ostream &OS);
63
64  typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
65
66  /// The keys of this map are maps which have OpName enum values as their keys
67  /// and instruction operand indices as their values.  The values of this map
68  /// are lists of instruction names.
69  typedef std::map<std::map<unsigned, unsigned>,
70                   std::vector<std::string>> OpNameMapTy;
71  typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
72
73  /// Generate member functions in the target-specific GenInstrInfo class.
74  ///
75  /// This method is used to custom expand TIIPredicate definitions.
76  /// See file llvm/Target/TargetInstPredicates.td for a description of what is
77  /// a TIIPredicate and how to use it.
78  void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
79                            bool ExpandDefinition = true);
80
81  /// Expand TIIPredicate definitions to functions that accept a const MCInst
82  /// reference.
83  void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
84
85  /// Write verifyInstructionPredicates methods.
86  void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
87  void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
88                  Record *InstrInfo,
89                  std::map<std::vector<Record*>, unsigned> &EL,
90                  const OperandInfoMapTy &OpInfo,
91                  raw_ostream &OS);
92  void emitOperandTypeMappings(
93      raw_ostream &OS, const CodeGenTarget &Target,
94      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
95  void initOperandMapData(
96            ArrayRef<const CodeGenInstruction *> NumberedInstructions,
97            StringRef Namespace,
98            std::map<std::string, unsigned> &Operands,
99            OpNameMapTy &OperandMap);
100  void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
101            ArrayRef<const CodeGenInstruction*> NumberedInstructions);
102
103  void emitLogicalOperandSizeMappings(
104      raw_ostream &OS, StringRef Namespace,
105      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
106  void emitLogicalOperandTypeMappings(
107      raw_ostream &OS, StringRef Namespace,
108      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
109
110  // Operand information.
111  void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
112  std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
113};
114
115} // end anonymous namespace
116
117static void PrintDefList(const std::vector<Record*> &Uses,
118                         unsigned Num, raw_ostream &OS) {
119  OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
120  for (auto [Idx, U] : enumerate(Uses))
121    OS << (Idx ? ", " : "") << getQualifiedName(U);
122  OS << " };\n";
123}
124
125//===----------------------------------------------------------------------===//
126// Operand Info Emission.
127//===----------------------------------------------------------------------===//
128
129std::vector<std::string>
130InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
131  std::vector<std::string> Result;
132
133  for (auto &Op : Inst.Operands) {
134    // Handle aggregate operands and normal operands the same way by expanding
135    // either case into a list of operands for this op.
136    std::vector<CGIOperandList::OperandInfo> OperandList;
137
138    // This might be a multiple operand thing.  Targets like X86 have
139    // registers in their multi-operand operands.  It may also be an anonymous
140    // operand, which has a single operand, but no declared class for the
141    // operand.
142    DagInit *MIOI = Op.MIOperandInfo;
143
144    if (!MIOI || MIOI->getNumArgs() == 0) {
145      // Single, anonymous, operand.
146      OperandList.push_back(Op);
147    } else {
148      for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
149        OperandList.push_back(Op);
150
151        auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
152        OperandList.back().Rec = OpR;
153      }
154    }
155
156    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
157      Record *OpR = OperandList[j].Rec;
158      std::string Res;
159
160      if (OpR->isSubClassOf("RegisterOperand"))
161        OpR = OpR->getValueAsDef("RegClass");
162      if (OpR->isSubClassOf("RegisterClass"))
163        Res += getQualifiedName(OpR) + "RegClassID, ";
164      else if (OpR->isSubClassOf("PointerLikeRegClass"))
165        Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
166      else
167        // -1 means the operand does not have a fixed register class.
168        Res += "-1, ";
169
170      // Fill in applicable flags.
171      Res += "0";
172
173      // Ptr value whose register class is resolved via callback.
174      if (OpR->isSubClassOf("PointerLikeRegClass"))
175        Res += "|(1<<MCOI::LookupPtrRegClass)";
176
177      // Predicate operands.  Check to see if the original unexpanded operand
178      // was of type PredicateOp.
179      if (Op.Rec->isSubClassOf("PredicateOp"))
180        Res += "|(1<<MCOI::Predicate)";
181
182      // Optional def operands.  Check to see if the original unexpanded operand
183      // was of type OptionalDefOperand.
184      if (Op.Rec->isSubClassOf("OptionalDefOperand"))
185        Res += "|(1<<MCOI::OptionalDef)";
186
187      // Branch target operands.  Check to see if the original unexpanded
188      // operand was of type BranchTargetOperand.
189      if (Op.Rec->isSubClassOf("BranchTargetOperand"))
190        Res += "|(1<<MCOI::BranchTarget)";
191
192      // Fill in operand type.
193      Res += ", ";
194      assert(!Op.OperandType.empty() && "Invalid operand type.");
195      Res += Op.OperandType;
196
197      // Fill in constraint info.
198      Res += ", ";
199
200      const CGIOperandList::ConstraintInfo &Constraint =
201        Op.Constraints[j];
202      if (Constraint.isNone())
203        Res += "0";
204      else if (Constraint.isEarlyClobber())
205        Res += "MCOI_EARLY_CLOBBER";
206      else {
207        assert(Constraint.isTied());
208        Res += "MCOI_TIED_TO(" + utostr(Constraint.getTiedOperand()) + ")";
209      }
210
211      Result.push_back(Res);
212    }
213  }
214
215  return Result;
216}
217
218void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
219                                       OperandInfoMapTy &OperandInfoIDs) {
220  // ID #0 is for no operand info.
221  unsigned OperandListNum = 0;
222  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
223
224  OS << "\n";
225  const CodeGenTarget &Target = CDP.getTargetInfo();
226  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
227    std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
228    unsigned &N = OperandInfoIDs[OperandInfo];
229    if (N != 0) continue;
230
231    N = ++OperandListNum;
232    OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
233    for (const std::string &Info : OperandInfo)
234      OS << "{ " << Info << " }, ";
235    OS << "};\n";
236  }
237}
238
239/// Initialize data structures for generating operand name mappings.
240///
241/// \param Operands [out] A map used to generate the OpName enum with operand
242///        names as its keys and operand enum values as its values.
243/// \param OperandMap [out] A map for representing the operand name mappings for
244///        each instructions.  This is used to generate the OperandMap table as
245///        well as the getNamedOperandIdx() function.
246void InstrInfoEmitter::initOperandMapData(
247        ArrayRef<const CodeGenInstruction *> NumberedInstructions,
248        StringRef Namespace,
249        std::map<std::string, unsigned> &Operands,
250        OpNameMapTy &OperandMap) {
251  unsigned NumOperands = 0;
252  for (const CodeGenInstruction *Inst : NumberedInstructions) {
253    if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
254      continue;
255    std::map<unsigned, unsigned> OpList;
256    for (const auto &Info : Inst->Operands) {
257      StrUintMapIter I = Operands.find(Info.Name);
258
259      if (I == Operands.end()) {
260        I = Operands.insert(Operands.begin(),
261                    std::pair<std::string, unsigned>(Info.Name, NumOperands++));
262      }
263      OpList[I->second] = Info.MIOperandNo;
264    }
265    OperandMap[OpList].push_back(Namespace.str() + "::" +
266                                 Inst->TheDef->getName().str());
267  }
268}
269
270/// Generate a table and function for looking up the indices of operands by
271/// name.
272///
273/// This code generates:
274/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
275///   for each operand name.
276/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
277///   operand indices.
278/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
279///   for looking up the operand index for an instruction, given a value from
280///   OpName enum
281void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
282           const CodeGenTarget &Target,
283           ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
284  StringRef Namespace = Target.getInstNamespace();
285  std::string OpNameNS = "OpName";
286  // Map of operand names to their enumeration value.  This will be used to
287  // generate the OpName enum.
288  std::map<std::string, unsigned> Operands;
289  OpNameMapTy OperandMap;
290
291  initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
292
293  OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
294  OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
295  OS << "namespace llvm {\n";
296  OS << "namespace " << Namespace << " {\n";
297  OS << "namespace " << OpNameNS << " {\n";
298  OS << "enum {\n";
299  for (const auto &Op : Operands)
300    OS << "  " << Op.first << " = " << Op.second << ",\n";
301
302  OS << "  OPERAND_LAST";
303  OS << "\n};\n";
304  OS << "} // end namespace OpName\n";
305  OS << "} // end namespace " << Namespace << "\n";
306  OS << "} // end namespace llvm\n";
307  OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
308
309  OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
310  OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
311  OS << "namespace llvm {\n";
312  OS << "namespace " << Namespace << " {\n";
313  OS << "LLVM_READONLY\n";
314  OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
315  if (!Operands.empty()) {
316    OS << "  static const int16_t OperandMap [][" << Operands.size()
317       << "] = {\n";
318    for (const auto &Entry : OperandMap) {
319      const std::map<unsigned, unsigned> &OpList = Entry.first;
320      OS << "{";
321
322      // Emit a row of the OperandMap table
323      for (unsigned i = 0, e = Operands.size(); i != e; ++i)
324        OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
325
326      OS << "},\n";
327    }
328    OS << "};\n";
329
330    OS << "  switch(Opcode) {\n";
331    unsigned TableIndex = 0;
332    for (const auto &Entry : OperandMap) {
333      for (const std::string &Name : Entry.second)
334        OS << "  case " << Name << ":\n";
335
336      OS << "    return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
337    }
338    OS << "  default: return -1;\n";
339    OS << "  }\n";
340  } else {
341    // There are no operands, so no need to emit anything
342    OS << "  return -1;\n";
343  }
344  OS << "}\n";
345  OS << "} // end namespace " << Namespace << "\n";
346  OS << "} // end namespace llvm\n";
347  OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
348}
349
350/// Generate an enum for all the operand types for this target, under the
351/// llvm::TargetNamespace::OpTypes namespace.
352/// Operand types are all definitions derived of the Operand Target.td class.
353void InstrInfoEmitter::emitOperandTypeMappings(
354    raw_ostream &OS, const CodeGenTarget &Target,
355    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
356
357  StringRef Namespace = Target.getInstNamespace();
358  std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
359  std::vector<Record *> RegisterOperands =
360      Records.getAllDerivedDefinitions("RegisterOperand");
361  std::vector<Record *> RegisterClasses =
362      Records.getAllDerivedDefinitions("RegisterClass");
363
364  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
365  OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
366  OS << "namespace llvm {\n";
367  OS << "namespace " << Namespace << " {\n";
368  OS << "namespace OpTypes {\n";
369  OS << "enum OperandType {\n";
370
371  unsigned EnumVal = 0;
372  for (const std::vector<Record *> *RecordsToAdd :
373       {&Operands, &RegisterOperands, &RegisterClasses}) {
374    for (const Record *Op : *RecordsToAdd) {
375      if (!Op->isAnonymous())
376        OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
377      ++EnumVal;
378    }
379  }
380
381  OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
382  OS << "} // end namespace OpTypes\n";
383  OS << "} // end namespace " << Namespace << "\n";
384  OS << "} // end namespace llvm\n";
385  OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
386
387  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
388  OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
389  OS << "namespace llvm {\n";
390  OS << "namespace " << Namespace << " {\n";
391  OS << "LLVM_READONLY\n";
392  OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
393  auto getInstrName = [&](int I) -> StringRef {
394    return NumberedInstructions[I]->TheDef->getName();
395  };
396  // TODO: Factor out duplicate operand lists to compress the tables.
397  if (!NumberedInstructions.empty()) {
398    std::vector<int> OperandOffsets;
399    std::vector<Record *> OperandRecords;
400    int CurrentOffset = 0;
401    for (const CodeGenInstruction *Inst : NumberedInstructions) {
402      OperandOffsets.push_back(CurrentOffset);
403      for (const auto &Op : Inst->Operands) {
404        const DagInit *MIOI = Op.MIOperandInfo;
405        if (!ExpandMIOperandInfo || !MIOI || MIOI->getNumArgs() == 0) {
406          // Single, anonymous, operand.
407          OperandRecords.push_back(Op.Rec);
408          ++CurrentOffset;
409        } else {
410          for (Init *Arg : MIOI->getArgs()) {
411            OperandRecords.push_back(cast<DefInit>(Arg)->getDef());
412            ++CurrentOffset;
413          }
414        }
415      }
416    }
417
418    // Emit the table of offsets (indexes) into the operand type table.
419    // Size the unsigned integer offset to save space.
420    assert(OperandRecords.size() <= UINT32_MAX &&
421           "Too many operands for offset table");
422    OS << ((OperandRecords.size() <= UINT16_MAX) ? "  const uint16_t"
423                                                 : "  const uint32_t");
424    OS << " Offsets[] = {\n";
425    for (int I = 0, E = OperandOffsets.size(); I != E; ++I) {
426      OS << "    /* " << getInstrName(I) << " */\n";
427      OS << "    " << OperandOffsets[I] << ",\n";
428    }
429    OS << "  };\n";
430
431    // Add an entry for the end so that we don't need to special case it below.
432    OperandOffsets.push_back(OperandRecords.size());
433
434    // Emit the actual operand types in a flat table.
435    // Size the signed integer operand type to save space.
436    assert(EnumVal <= INT16_MAX &&
437           "Too many operand types for operand types table");
438    OS << "\n  using namespace OpTypes;\n";
439    OS << ((EnumVal <= INT8_MAX) ? "  const int8_t" : "  const int16_t");
440    OS << " OpcodeOperandTypes[] = {\n    ";
441    for (int I = 0, E = OperandRecords.size(), CurOffset = 0; I != E; ++I) {
442      // We print each Opcode's operands in its own row.
443      if (I == OperandOffsets[CurOffset]) {
444        OS << "\n    /* " << getInstrName(CurOffset) << " */\n    ";
445        while (OperandOffsets[++CurOffset] == I)
446          OS << "/* " << getInstrName(CurOffset) << " */\n    ";
447      }
448      Record *OpR = OperandRecords[I];
449      if ((OpR->isSubClassOf("Operand") ||
450           OpR->isSubClassOf("RegisterOperand") ||
451           OpR->isSubClassOf("RegisterClass")) &&
452          !OpR->isAnonymous())
453        OS << OpR->getName();
454      else
455        OS << -1;
456      OS << ", ";
457    }
458    OS << "\n  };\n";
459
460    OS << "  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
461  } else {
462    OS << "  llvm_unreachable(\"No instructions defined\");\n";
463  }
464  OS << "}\n";
465  OS << "} // end namespace " << Namespace << "\n";
466  OS << "} // end namespace llvm\n";
467  OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
468
469  OS << "#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE\n";
470  OS << "#undef GET_INSTRINFO_MEM_OPERAND_SIZE\n";
471  OS << "namespace llvm {\n";
472  OS << "namespace " << Namespace << " {\n";
473  OS << "LLVM_READONLY\n";
474  OS << "static int getMemOperandSize(int OpType) {\n";
475  OS << "  switch (OpType) {\n";
476  std::map<int, std::vector<StringRef>> SizeToOperandName;
477  for (const Record *Op : Operands) {
478    if (!Op->isSubClassOf("X86MemOperand"))
479      continue;
480    if (int Size = Op->getValueAsInt("Size"))
481      SizeToOperandName[Size].push_back(Op->getName());
482  }
483  OS << "  default: return 0;\n";
484  for (auto KV : SizeToOperandName) {
485    for (const StringRef &OperandName : KV.second)
486      OS << "  case OpTypes::" << OperandName << ":\n";
487    OS << "    return " << KV.first << ";\n\n";
488  }
489  OS << "  }\n}\n";
490  OS << "} // end namespace " << Namespace << "\n";
491  OS << "} // end namespace llvm\n";
492  OS << "#endif // GET_INSTRINFO_MEM_OPERAND_SIZE\n\n";
493}
494
495void InstrInfoEmitter::emitLogicalOperandSizeMappings(
496    raw_ostream &OS, StringRef Namespace,
497    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
498  std::map<std::vector<unsigned>, unsigned> LogicalOpSizeMap;
499
500  std::map<unsigned, std::vector<std::string>> InstMap;
501
502  size_t LogicalOpListSize = 0U;
503  std::vector<unsigned> LogicalOpList;
504  for (const auto *Inst : NumberedInstructions) {
505    if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
506      continue;
507
508    LogicalOpList.clear();
509    llvm::transform(Inst->Operands, std::back_inserter(LogicalOpList),
510                    [](const CGIOperandList::OperandInfo &Op) -> unsigned {
511                      auto *MIOI = Op.MIOperandInfo;
512                      if (!MIOI || MIOI->getNumArgs() == 0)
513                        return 1;
514                      return MIOI->getNumArgs();
515                    });
516    LogicalOpListSize = std::max(LogicalOpList.size(), LogicalOpListSize);
517
518    auto I =
519        LogicalOpSizeMap.insert({LogicalOpList, LogicalOpSizeMap.size()}).first;
520    InstMap[I->second].push_back(
521        (Namespace + "::" + Inst->TheDef->getName()).str());
522  }
523
524  OS << "#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n";
525  OS << "#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n";
526  OS << "namespace llvm {\n";
527  OS << "namespace " << Namespace << " {\n";
528  OS << "LLVM_READONLY static unsigned\n";
529  OS << "getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
530  if (!InstMap.empty()) {
531    std::vector<const std::vector<unsigned> *> LogicalOpSizeList(
532        LogicalOpSizeMap.size());
533    for (auto &P : LogicalOpSizeMap) {
534      LogicalOpSizeList[P.second] = &P.first;
535    }
536    OS << "  static const unsigned SizeMap[][" << LogicalOpListSize
537       << "] = {\n";
538    for (auto &R : LogicalOpSizeList) {
539      const auto &Row = *R;
540      OS << "   {";
541      int i;
542      for (i = 0; i < static_cast<int>(Row.size()); ++i) {
543        OS << Row[i] << ", ";
544      }
545      for (; i < static_cast<int>(LogicalOpListSize); ++i) {
546        OS << "0, ";
547      }
548      OS << "}, ";
549      OS << "\n";
550    }
551    OS << "  };\n";
552
553    OS << "  switch (Opcode) {\n";
554    OS << "  default: return LogicalOpIdx;\n";
555    for (auto &P : InstMap) {
556      auto OpMapIdx = P.first;
557      const auto &Insts = P.second;
558      for (const auto &Inst : Insts) {
559        OS << "  case " << Inst << ":\n";
560      }
561      OS << "    return SizeMap[" << OpMapIdx << "][LogicalOpIdx];\n";
562    }
563    OS << "  }\n";
564  } else {
565    OS << "  return LogicalOpIdx;\n";
566  }
567  OS << "}\n";
568
569  OS << "LLVM_READONLY static inline unsigned\n";
570  OS << "getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
571  OS << "  auto S = 0U;\n";
572  OS << "  for (auto i = 0U; i < LogicalOpIdx; ++i)\n";
573  OS << "    S += getLogicalOperandSize(Opcode, i);\n";
574  OS << "  return S;\n";
575  OS << "}\n";
576
577  OS << "} // end namespace " << Namespace << "\n";
578  OS << "} // end namespace llvm\n";
579  OS << "#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n\n";
580}
581
582void InstrInfoEmitter::emitLogicalOperandTypeMappings(
583    raw_ostream &OS, StringRef Namespace,
584    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
585  std::map<std::vector<std::string>, unsigned> LogicalOpTypeMap;
586
587  std::map<unsigned, std::vector<std::string>> InstMap;
588
589  size_t OpTypeListSize = 0U;
590  std::vector<std::string> LogicalOpTypeList;
591  for (const auto *Inst : NumberedInstructions) {
592    if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
593      continue;
594
595    LogicalOpTypeList.clear();
596    for (const auto &Op : Inst->Operands) {
597      auto *OpR = Op.Rec;
598      if ((OpR->isSubClassOf("Operand") ||
599           OpR->isSubClassOf("RegisterOperand") ||
600           OpR->isSubClassOf("RegisterClass")) &&
601          !OpR->isAnonymous()) {
602        LogicalOpTypeList.push_back(
603            (Namespace + "::OpTypes::" + Op.Rec->getName()).str());
604      } else {
605        LogicalOpTypeList.push_back("-1");
606      }
607    }
608    OpTypeListSize = std::max(LogicalOpTypeList.size(), OpTypeListSize);
609
610    auto I =
611        LogicalOpTypeMap.insert({LogicalOpTypeList, LogicalOpTypeMap.size()})
612            .first;
613    InstMap[I->second].push_back(
614        (Namespace + "::" + Inst->TheDef->getName()).str());
615  }
616
617  OS << "#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n";
618  OS << "#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n";
619  OS << "namespace llvm {\n";
620  OS << "namespace " << Namespace << " {\n";
621  OS << "LLVM_READONLY static int\n";
622  OS << "getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
623  if (!InstMap.empty()) {
624    std::vector<const std::vector<std::string> *> LogicalOpTypeList(
625        LogicalOpTypeMap.size());
626    for (auto &P : LogicalOpTypeMap) {
627      LogicalOpTypeList[P.second] = &P.first;
628    }
629    OS << "  static const int TypeMap[][" << OpTypeListSize << "] = {\n";
630    for (int r = 0, rs = LogicalOpTypeList.size(); r < rs; ++r) {
631      const auto &Row = *LogicalOpTypeList[r];
632      OS << "   {";
633      int i, s = Row.size();
634      for (i = 0; i < s; ++i) {
635        if (i > 0)
636          OS << ", ";
637        OS << Row[i];
638      }
639      for (; i < static_cast<int>(OpTypeListSize); ++i) {
640        if (i > 0)
641          OS << ", ";
642        OS << "-1";
643      }
644      OS << "}";
645      if (r != rs - 1)
646        OS << ",";
647      OS << "\n";
648    }
649    OS << "  };\n";
650
651    OS << "  switch (Opcode) {\n";
652    OS << "  default: return -1;\n";
653    for (auto &P : InstMap) {
654      auto OpMapIdx = P.first;
655      const auto &Insts = P.second;
656      for (const auto &Inst : Insts) {
657        OS << "  case " << Inst << ":\n";
658      }
659      OS << "    return TypeMap[" << OpMapIdx << "][LogicalOpIdx];\n";
660    }
661    OS << "  }\n";
662  } else {
663    OS << "  return -1;\n";
664  }
665  OS << "}\n";
666  OS << "} // end namespace " << Namespace << "\n";
667  OS << "} // end namespace llvm\n";
668  OS << "#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n\n";
669}
670
671void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
672                                             StringRef TargetName) {
673  RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
674
675  OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
676  OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
677
678  OS << "namespace llvm {\n";
679  OS << "class MCInst;\n";
680  OS << "class FeatureBitset;\n\n";
681
682  OS << "namespace " << TargetName << "_MC {\n\n";
683
684  for (const Record *Rec : TIIPredicates) {
685    OS << "bool " << Rec->getValueAsString("FunctionName")
686        << "(const MCInst &MI);\n";
687  }
688
689  OS << "void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset "
690        "&Features);\n";
691
692  OS << "\n} // end namespace " << TargetName << "_MC\n";
693  OS << "} // end namespace llvm\n\n";
694
695  OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
696
697  OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
698  OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
699
700  OS << "namespace llvm {\n";
701  OS << "namespace " << TargetName << "_MC {\n\n";
702
703  PredicateExpander PE(TargetName);
704  PE.setExpandForMC(true);
705
706  for (const Record *Rec : TIIPredicates) {
707    OS << "bool " << Rec->getValueAsString("FunctionName");
708    OS << "(const MCInst &MI) {\n";
709
710    OS.indent(PE.getIndentLevel() * 2);
711    PE.expandStatement(OS, Rec->getValueAsDef("Body"));
712    OS << "\n}\n\n";
713  }
714
715  OS << "} // end namespace " << TargetName << "_MC\n";
716  OS << "} // end namespace llvm\n\n";
717
718  OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n\n";
719}
720
721static std::string
722getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
723  std::string Name = "CEFBS";
724  for (const auto &Feature : FeatureBitset)
725    Name += ("_" + Feature->getName()).str();
726  return Name;
727}
728
729void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
730                                           const CodeGenTarget &Target) {
731  const auto &All = SubtargetFeatureInfo::getAll(Records);
732  std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
733  SubtargetFeatures.insert(All.begin(), All.end());
734
735  OS << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
736     << "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n"
737     << "#include <sstream>\n\n";
738
739  OS << "namespace llvm {\n";
740  OS << "namespace " << Target.getName() << "_MC {\n\n";
741
742  // Emit the subtarget feature enumeration.
743  SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
744                                                           OS);
745
746  // Emit the name table for error messages.
747  OS << "#ifndef NDEBUG\n";
748  SubtargetFeatureInfo::emitNameTable(SubtargetFeatures, OS);
749  OS << "#endif // NDEBUG\n\n";
750
751  // Emit the available features compute function.
752  SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
753      Target.getName(), "", "computeAvailableFeatures", SubtargetFeatures, OS);
754
755  std::vector<std::vector<Record *>> FeatureBitsets;
756  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
757    FeatureBitsets.emplace_back();
758    for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
759      const auto &I = SubtargetFeatures.find(Predicate);
760      if (I != SubtargetFeatures.end())
761        FeatureBitsets.back().push_back(I->second.TheDef);
762    }
763  }
764
765  llvm::sort(FeatureBitsets, [&](const std::vector<Record *> &A,
766                                 const std::vector<Record *> &B) {
767    if (A.size() < B.size())
768      return true;
769    if (A.size() > B.size())
770      return false;
771    for (auto Pair : zip(A, B)) {
772      if (std::get<0>(Pair)->getName() < std::get<1>(Pair)->getName())
773        return true;
774      if (std::get<0>(Pair)->getName() > std::get<1>(Pair)->getName())
775        return false;
776    }
777    return false;
778  });
779  FeatureBitsets.erase(
780      std::unique(FeatureBitsets.begin(), FeatureBitsets.end()),
781      FeatureBitsets.end());
782  OS << "#ifndef NDEBUG\n"
783     << "// Feature bitsets.\n"
784     << "enum : " << getMinimalTypeForRange(FeatureBitsets.size()) << " {\n"
785     << "  CEFBS_None,\n";
786  for (const auto &FeatureBitset : FeatureBitsets) {
787    if (FeatureBitset.empty())
788      continue;
789    OS << "  " << getNameForFeatureBitset(FeatureBitset) << ",\n";
790  }
791  OS << "};\n\n"
792     << "static constexpr FeatureBitset FeatureBitsets[] = {\n"
793     << "  {}, // CEFBS_None\n";
794  for (const auto &FeatureBitset : FeatureBitsets) {
795    if (FeatureBitset.empty())
796      continue;
797    OS << "  {";
798    for (const auto &Feature : FeatureBitset) {
799      const auto &I = SubtargetFeatures.find(Feature);
800      assert(I != SubtargetFeatures.end() && "Didn't import predicate?");
801      OS << I->second.getEnumBitName() << ", ";
802    }
803    OS << "},\n";
804  }
805  OS << "};\n"
806     << "#endif // NDEBUG\n\n";
807
808  // Emit the predicate verifier.
809  OS << "void verifyInstructionPredicates(\n"
810     << "    unsigned Opcode, const FeatureBitset &Features) {\n"
811     << "#ifndef NDEBUG\n"
812     << "  static " << getMinimalTypeForRange(FeatureBitsets.size())
813     << " RequiredFeaturesRefs[] = {\n";
814  unsigned InstIdx = 0;
815  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
816    OS << "    CEFBS";
817    unsigned NumPredicates = 0;
818    for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
819      const auto &I = SubtargetFeatures.find(Predicate);
820      if (I != SubtargetFeatures.end()) {
821        OS << '_' << I->second.TheDef->getName();
822        NumPredicates++;
823      }
824    }
825    if (!NumPredicates)
826      OS << "_None";
827    OS << ", // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
828    InstIdx++;
829  }
830  OS << "  };\n\n";
831  OS << "  assert(Opcode < " << InstIdx << ");\n";
832  OS << "  FeatureBitset AvailableFeatures = "
833        "computeAvailableFeatures(Features);\n";
834  OS << "  const FeatureBitset &RequiredFeatures = "
835        "FeatureBitsets[RequiredFeaturesRefs[Opcode]];\n";
836  OS << "  FeatureBitset MissingFeatures =\n"
837     << "      (AvailableFeatures & RequiredFeatures) ^\n"
838     << "      RequiredFeatures;\n"
839     << "  if (MissingFeatures.any()) {\n"
840     << "    std::ostringstream Msg;\n"
841     << "    Msg << \"Attempting to emit \" << &" << Target.getName()
842     << "InstrNameData[" << Target.getName() << "InstrNameIndices[Opcode]]\n"
843     << "        << \" instruction but the \";\n"
844     << "    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)\n"
845     << "      if (MissingFeatures.test(i))\n"
846     << "        Msg << SubtargetFeatureNames[i] << \" \";\n"
847     << "    Msg << \"predicate(s) are not met\";\n"
848     << "    report_fatal_error(Msg.str().c_str());\n"
849     << "  }\n"
850     << "#endif // NDEBUG\n";
851  OS << "}\n";
852  OS << "} // end namespace " << Target.getName() << "_MC\n";
853  OS << "} // end namespace llvm\n";
854  OS << "#endif // ENABLE_INSTR_PREDICATE_VERIFIER\n\n";
855}
856
857void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
858                                            StringRef TargetName,
859                                            bool ExpandDefinition) {
860  RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
861  if (TIIPredicates.empty())
862    return;
863
864  PredicateExpander PE(TargetName);
865  PE.setExpandForMC(false);
866
867  for (const Record *Rec : TIIPredicates) {
868    OS << (ExpandDefinition ? "" : "static ") << "bool ";
869    if (ExpandDefinition)
870      OS << TargetName << "InstrInfo::";
871    OS << Rec->getValueAsString("FunctionName");
872    OS << "(const MachineInstr &MI)";
873    if (!ExpandDefinition) {
874      OS << ";\n";
875      continue;
876    }
877
878    OS << " {\n";
879    OS.indent(PE.getIndentLevel() * 2);
880    PE.expandStatement(OS, Rec->getValueAsDef("Body"));
881    OS << "\n}\n\n";
882  }
883}
884
885//===----------------------------------------------------------------------===//
886// Main Output.
887//===----------------------------------------------------------------------===//
888
889// run - Emit the main instruction description records for the target...
890void InstrInfoEmitter::run(raw_ostream &OS) {
891  emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
892  emitEnums(OS);
893
894  OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
895  OS << "#undef GET_INSTRINFO_MC_DESC\n";
896
897  OS << "namespace llvm {\n\n";
898
899  CodeGenTarget &Target = CDP.getTargetInfo();
900  const std::string &TargetName = std::string(Target.getName());
901  Record *InstrInfo = Target.getInstructionSet();
902
903  // Keep track of all of the def lists we have emitted already.
904  std::map<std::vector<Record*>, unsigned> EmittedLists;
905  unsigned ListNumber = 0;
906
907  // Emit all of the instruction's implicit uses and defs.
908  Records.startTimer("Emit uses/defs");
909  for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
910    std::vector<Record *> ImplicitOps = II->ImplicitUses;
911    llvm::append_range(ImplicitOps, II->ImplicitDefs);
912    if (!ImplicitOps.empty()) {
913      unsigned &IL = EmittedLists[ImplicitOps];
914      if (!IL) {
915        IL = ++ListNumber;
916        PrintDefList(ImplicitOps, IL, OS);
917      }
918    }
919  }
920
921  OperandInfoMapTy OperandInfoIDs;
922
923  // Emit all of the operand info records.
924  Records.startTimer("Emit operand info");
925  EmitOperandInfo(OS, OperandInfoIDs);
926
927  // Emit all of the MCInstrDesc records in reverse ENUM ordering.
928  Records.startTimer("Emit InstrDesc records");
929  OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
930  ArrayRef<const CodeGenInstruction*> NumberedInstructions =
931    Target.getInstructionsByEnumValue();
932
933  SequenceToOffsetTable<std::string> InstrNames;
934  unsigned Num = NumberedInstructions.size();
935  for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
936    // Keep a list of the instruction names.
937    InstrNames.add(std::string(Inst->TheDef->getName()));
938    // Emit the record into the table.
939    emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoIDs, OS);
940  }
941  OS << "};\n\n";
942
943  // Emit the array of instruction names.
944  Records.startTimer("Emit instruction names");
945  InstrNames.layout();
946  InstrNames.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
947                                          "InstrNameData[]");
948
949  OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
950  Num = 0;
951  for (const CodeGenInstruction *Inst : NumberedInstructions) {
952    // Newline every eight entries.
953    if (Num % 8 == 0)
954      OS << "\n    ";
955    OS << InstrNames.get(std::string(Inst->TheDef->getName())) << "U, ";
956    ++Num;
957  }
958  OS << "\n};\n\n";
959
960  bool HasDeprecationFeatures =
961      llvm::any_of(NumberedInstructions, [](const CodeGenInstruction *Inst) {
962        return !Inst->HasComplexDeprecationPredicate &&
963               !Inst->DeprecatedReason.empty();
964      });
965  if (HasDeprecationFeatures) {
966    OS << "extern const uint8_t " << TargetName
967       << "InstrDeprecationFeatures[] = {";
968    Num = 0;
969    for (const CodeGenInstruction *Inst : NumberedInstructions) {
970      if (Num % 8 == 0)
971        OS << "\n    ";
972      if (!Inst->HasComplexDeprecationPredicate &&
973          !Inst->DeprecatedReason.empty())
974        OS << Target.getInstNamespace() << "::" << Inst->DeprecatedReason
975           << ", ";
976      else
977        OS << "uint8_t(-1), ";
978      ++Num;
979    }
980    OS << "\n};\n\n";
981  }
982
983  bool HasComplexDeprecationInfos =
984      llvm::any_of(NumberedInstructions, [](const CodeGenInstruction *Inst) {
985        return Inst->HasComplexDeprecationPredicate;
986      });
987  if (HasComplexDeprecationInfos) {
988    OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
989       << "InstrComplexDeprecationInfos[] = {";
990    Num = 0;
991    for (const CodeGenInstruction *Inst : NumberedInstructions) {
992      if (Num % 8 == 0)
993        OS << "\n    ";
994      if (Inst->HasComplexDeprecationPredicate)
995        // Emit a function pointer to the complex predicate method.
996        OS << "&get" << Inst->DeprecatedReason << "DeprecationInfo, ";
997      else
998        OS << "nullptr, ";
999      ++Num;
1000    }
1001    OS << "\n};\n\n";
1002  }
1003
1004  // MCInstrInfo initialization routine.
1005  Records.startTimer("Emit initialization routine");
1006  OS << "static inline void Init" << TargetName
1007     << "MCInstrInfo(MCInstrInfo *II) {\n";
1008  OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
1009     << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1010  if (HasDeprecationFeatures)
1011    OS << TargetName << "InstrDeprecationFeatures, ";
1012  else
1013    OS << "nullptr, ";
1014  if (HasComplexDeprecationInfos)
1015    OS << TargetName << "InstrComplexDeprecationInfos, ";
1016  else
1017    OS << "nullptr, ";
1018  OS << NumberedInstructions.size() << ");\n}\n\n";
1019
1020  OS << "} // end namespace llvm\n";
1021
1022  OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
1023
1024  // Create a TargetInstrInfo subclass to hide the MC layer initialization.
1025  OS << "#ifdef GET_INSTRINFO_HEADER\n";
1026  OS << "#undef GET_INSTRINFO_HEADER\n";
1027
1028  std::string ClassName = TargetName + "GenInstrInfo";
1029  OS << "namespace llvm {\n";
1030  OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
1031     << "  explicit " << ClassName
1032     << "(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, "
1033        "unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
1034     << "  ~" << ClassName << "() override = default;\n";
1035
1036
1037  OS << "\n};\n} // end namespace llvm\n";
1038
1039  OS << "#endif // GET_INSTRINFO_HEADER\n\n";
1040
1041  OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
1042  OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
1043  emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ false);
1044  OS << "\n";
1045  OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
1046
1047  OS << "#ifdef GET_INSTRINFO_HELPERS\n";
1048  OS << "#undef GET_INSTRINFO_HELPERS\n\n";
1049  emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ true);
1050  OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
1051
1052  OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
1053  OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
1054
1055  OS << "namespace llvm {\n";
1056  OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
1057  OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
1058  OS << "extern const char " << TargetName << "InstrNameData[];\n";
1059  if (HasDeprecationFeatures)
1060    OS << "extern const uint8_t " << TargetName
1061       << "InstrDeprecationFeatures[];\n";
1062  if (HasComplexDeprecationInfos)
1063    OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
1064       << "InstrComplexDeprecationInfos[];\n";
1065  OS << ClassName << "::" << ClassName
1066     << "(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned "
1067        "CatchRetOpcode, unsigned ReturnOpcode)\n"
1068     << "  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, "
1069        "ReturnOpcode) {\n"
1070     << "  InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
1071     << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1072  if (HasDeprecationFeatures)
1073    OS << TargetName << "InstrDeprecationFeatures, ";
1074  else
1075    OS << "nullptr, ";
1076  if (HasComplexDeprecationInfos)
1077    OS << TargetName << "InstrComplexDeprecationInfos, ";
1078  else
1079    OS << "nullptr, ";
1080  OS << NumberedInstructions.size() << ");\n}\n";
1081  OS << "} // end namespace llvm\n";
1082
1083  OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
1084
1085  Records.startTimer("Emit operand name mappings");
1086  emitOperandNameMappings(OS, Target, NumberedInstructions);
1087
1088  Records.startTimer("Emit operand type mappings");
1089  emitOperandTypeMappings(OS, Target, NumberedInstructions);
1090
1091  Records.startTimer("Emit logical operand size mappings");
1092  emitLogicalOperandSizeMappings(OS, TargetName, NumberedInstructions);
1093
1094  Records.startTimer("Emit logical operand type mappings");
1095  emitLogicalOperandTypeMappings(OS, TargetName, NumberedInstructions);
1096
1097  Records.startTimer("Emit helper methods");
1098  emitMCIIHelperMethods(OS, TargetName);
1099
1100  Records.startTimer("Emit verifier methods");
1101  emitFeatureVerifier(OS, Target);
1102}
1103
1104void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
1105                                  Record *InstrInfo,
1106                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
1107                                  const OperandInfoMapTy &OpInfo,
1108                                  raw_ostream &OS) {
1109  int MinOperands = 0;
1110  if (!Inst.Operands.empty())
1111    // Each logical operand can be multiple MI operands.
1112    MinOperands = Inst.Operands.back().MIOperandNo +
1113                  Inst.Operands.back().MINumOperands;
1114
1115  OS << "  { ";
1116  OS << Num << ",\t" << MinOperands << ",\t"
1117     << Inst.Operands.NumDefs << ",\t"
1118     << Inst.TheDef->getValueAsInt("Size") << ",\t"
1119     << SchedModels.getSchedClassIdx(Inst) << ",\t"
1120     << Inst.ImplicitUses.size() << ",\t"
1121     << Inst.ImplicitDefs.size() << ",\t0";
1122
1123  CodeGenTarget &Target = CDP.getTargetInfo();
1124
1125  // Emit all of the target independent flags...
1126  if (Inst.isPreISelOpcode)    OS << "|(1ULL<<MCID::PreISelOpcode)";
1127  if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
1128  if (Inst.isMeta)             OS << "|(1ULL<<MCID::Meta)";
1129  if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
1130  if (Inst.isEHScopeReturn)    OS << "|(1ULL<<MCID::EHScopeReturn)";
1131  if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
1132  if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
1133  if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
1134  if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
1135  if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
1136  if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
1137  if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
1138  if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
1139  if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
1140  if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
1141  if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
1142  if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
1143  if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
1144  if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
1145  if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
1146  if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
1147  if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
1148  if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
1149  if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
1150  if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";
1151  if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
1152  if (Inst.isNotDuplicable)    OS << "|(1ULL<<MCID::NotDuplicable)";
1153  if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
1154  if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
1155  if (Inst.hasPostISelHook)    OS << "|(1ULL<<MCID::HasPostISelHook)";
1156  if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
1157  if (Inst.hasSideEffects)     OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
1158  if (Inst.isAsCheapAsAMove)   OS << "|(1ULL<<MCID::CheapAsAMove)";
1159  if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
1160    OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
1161  if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
1162    OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
1163  if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
1164  if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
1165  if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
1166  if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
1167  if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
1168  if (Inst.isAuthenticated) OS << "|(1ULL<<MCID::Authenticated)";
1169
1170  // Emit all of the target-specific flags...
1171  BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
1172  if (!TSF)
1173    PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
1174  uint64_t Value = 0;
1175  for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
1176    if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
1177      Value |= uint64_t(Bit->getValue()) << i;
1178    else
1179      PrintFatalError(Inst.TheDef->getLoc(),
1180                      "Invalid TSFlags bit in " + Inst.TheDef->getName());
1181  }
1182  OS << ", 0x";
1183  OS.write_hex(Value);
1184  OS << "ULL, ";
1185
1186  // Emit the implicit use/def list...
1187  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
1188  llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
1189  if (ImplicitOps.empty())
1190    OS << "nullptr, ";
1191  else
1192    OS << "ImplicitList" << EmittedLists[ImplicitOps] << ", ";
1193
1194  // Emit the operand info.
1195  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
1196  if (OperandInfo.empty())
1197    OS << "nullptr";
1198  else
1199    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
1200
1201  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
1202}
1203
1204// emitEnums - Print out enum values for all of the instructions.
1205void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
1206  OS << "#ifdef GET_INSTRINFO_ENUM\n";
1207  OS << "#undef GET_INSTRINFO_ENUM\n";
1208
1209  OS << "namespace llvm {\n\n";
1210
1211  const CodeGenTarget &Target = CDP.getTargetInfo();
1212
1213  // We must emit the PHI opcode first...
1214  StringRef Namespace = Target.getInstNamespace();
1215
1216  if (Namespace.empty())
1217    PrintFatalError("No instructions defined!");
1218
1219  OS << "namespace " << Namespace << " {\n";
1220  OS << "  enum {\n";
1221  unsigned Num = 0;
1222  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
1223    OS << "    " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
1224  OS << "    INSTRUCTION_LIST_END = " << Num << "\n";
1225  OS << "  };\n\n";
1226  OS << "} // end namespace " << Namespace << "\n";
1227  OS << "} // end namespace llvm\n";
1228  OS << "#endif // GET_INSTRINFO_ENUM\n\n";
1229
1230  OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
1231  OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
1232  OS << "namespace llvm {\n\n";
1233  OS << "namespace " << Namespace << " {\n";
1234  OS << "namespace Sched {\n";
1235  OS << "  enum {\n";
1236  Num = 0;
1237  for (const auto &Class : SchedModels.explicit_classes())
1238    OS << "    " << Class.Name << "\t= " << Num++ << ",\n";
1239  OS << "    SCHED_LIST_END = " << Num << "\n";
1240  OS << "  };\n";
1241  OS << "} // end namespace Sched\n";
1242  OS << "} // end namespace " << Namespace << "\n";
1243  OS << "} // end namespace llvm\n";
1244
1245  OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
1246}
1247
1248namespace llvm {
1249
1250void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
1251  RK.startTimer("Analyze DAG patterns");
1252  InstrInfoEmitter(RK).run(OS);
1253  RK.startTimer("Emit map table");
1254  EmitMapTable(RK, OS);
1255}
1256
1257} // end namespace llvm
1258