1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonTargetMachine.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonLoopIdiomRecognition.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonMachineScheduler.h"
19#include "HexagonTargetObjectFile.h"
20#include "HexagonTargetTransformInfo.h"
21#include "HexagonVectorLoopCarriedReuse.h"
22#include "TargetInfo/HexagonTargetInfo.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/CodeGen/TargetPassConfig.h"
25#include "llvm/CodeGen/VLIWMachineScheduler.h"
26#include "llvm/IR/LegacyPassManager.h"
27#include "llvm/IR/Module.h"
28#include "llvm/MC/TargetRegistry.h"
29#include "llvm/Passes/PassBuilder.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Transforms/Scalar.h"
32#include <optional>
33
34using namespace llvm;
35
36static cl::opt<bool>
37    EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
38                  cl::desc("Enable Hexagon constant-extender optimization"));
39
40static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true),
41                                  cl::desc("Enable RDF-based optimizations"));
42
43static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
44  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
45
46static cl::opt<bool>
47    DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
48                    cl::desc("Disable Hexagon Addressing Mode Optimization"));
49
50static cl::opt<bool>
51    DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
52                         cl::desc("Disable Hexagon CFG Optimization"));
53
54static cl::opt<bool>
55    DisableHCP("disable-hcp", cl::Hidden,
56               cl::desc("Disable Hexagon constant propagation"));
57
58static cl::opt<bool> DisableStoreWidening("disable-store-widen",
59  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
60
61static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
62                                          cl::init(true), cl::Hidden,
63                                          cl::desc("Early expansion of MUX"));
64
65static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
66                                   cl::desc("Enable early if-conversion"));
67
68static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
69  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
70
71static cl::opt<bool>
72    EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
73                  cl::desc("Enable commoning of GEP instructions"));
74
75static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
76  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
77
78static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
79  cl::desc("Enable converting conditional transfers into MUX instructions"));
80
81static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
82  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
83  "predicate instructions"));
84
85static cl::opt<bool>
86    EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
87                       cl::desc("Enable loop data prefetch on Hexagon"));
88
89static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
90  cl::desc("Disable splitting double registers"));
91
92static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
93  cl::Hidden, cl::desc("Bit simplification"));
94
95static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
96  cl::Hidden, cl::desc("Loop rescheduling"));
97
98static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
99  cl::Hidden, cl::desc("Disable backend optimizations"));
100
101static cl::opt<bool>
102    EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
103                      cl::desc("Enable Hexagon Vector print instr pass"));
104
105static cl::opt<bool>
106    EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
107                      cl::desc("Enable vextract optimization"));
108
109static cl::opt<bool>
110    EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
111                        cl::desc("Enable HVX vector combining"));
112
113static cl::opt<bool> EnableInitialCFGCleanup(
114    "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
115    cl::desc("Simplify the CFG after atomic expansion pass"));
116
117static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
118                                        cl::init(true),
119                                        cl::desc("Enable instsimplify"));
120
121/// HexagonTargetMachineModule - Note that this is used on hosts that
122/// cannot link in a library unless there are references into the
123/// library.  In particular, it seems that it is not possible to get
124/// things to work on Win32 without this.  Though it is unused, do not
125/// remove it.
126extern "C" int HexagonTargetMachineModule;
127int HexagonTargetMachineModule = 0;
128
129static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
130  ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
131      C, std::make_unique<HexagonConvergingVLIWScheduler>());
132  DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
133  DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
134  DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
135  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
136  return DAG;
137}
138
139static MachineSchedRegistry
140SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
141                    createVLIWMachineSched);
142
143namespace llvm {
144  extern char &HexagonExpandCondsetsID;
145  void initializeHexagonBitSimplifyPass(PassRegistry&);
146  void initializeHexagonConstExtendersPass(PassRegistry&);
147  void initializeHexagonConstPropagationPass(PassRegistry&);
148  void initializeHexagonCopyToCombinePass(PassRegistry&);
149  void initializeHexagonEarlyIfConversionPass(PassRegistry&);
150  void initializeHexagonExpandCondsetsPass(PassRegistry&);
151  void initializeHexagonGenMuxPass(PassRegistry&);
152  void initializeHexagonHardwareLoopsPass(PassRegistry&);
153  void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
154  void initializeHexagonNewValueJumpPass(PassRegistry&);
155  void initializeHexagonOptAddrModePass(PassRegistry&);
156  void initializeHexagonPacketizerPass(PassRegistry&);
157  void initializeHexagonRDFOptPass(PassRegistry&);
158  void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
159  void initializeHexagonVExtractPass(PassRegistry &);
160  void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
161  void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
162  Pass *createHexagonLoopIdiomPass();
163  Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
164
165  FunctionPass *createHexagonBitSimplify();
166  FunctionPass *createHexagonBranchRelaxation();
167  FunctionPass *createHexagonCallFrameInformation();
168  FunctionPass *createHexagonCFGOptimizer();
169  FunctionPass *createHexagonCommonGEP();
170  FunctionPass *createHexagonConstExtenders();
171  FunctionPass *createHexagonConstPropagationPass();
172  FunctionPass *createHexagonCopyToCombine();
173  FunctionPass *createHexagonEarlyIfConversion();
174  FunctionPass *createHexagonFixupHwLoops();
175  FunctionPass *createHexagonGenExtract();
176  FunctionPass *createHexagonGenInsert();
177  FunctionPass *createHexagonGenMux();
178  FunctionPass *createHexagonGenPredicate();
179  FunctionPass *createHexagonHardwareLoops();
180  FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
181                                     CodeGenOpt::Level OptLevel);
182  FunctionPass *createHexagonLoopRescheduling();
183  FunctionPass *createHexagonNewValueJump();
184  FunctionPass *createHexagonOptAddrMode();
185  FunctionPass *createHexagonOptimizeSZextends();
186  FunctionPass *createHexagonPacketizer(bool Minimal);
187  FunctionPass *createHexagonPeephole();
188  FunctionPass *createHexagonRDFOpt();
189  FunctionPass *createHexagonSplitConst32AndConst64();
190  FunctionPass *createHexagonSplitDoubleRegs();
191  FunctionPass *createHexagonStoreWidening();
192  FunctionPass *createHexagonVectorCombineLegacyPass();
193  FunctionPass *createHexagonVectorPrint();
194  FunctionPass *createHexagonVExtract();
195} // end namespace llvm;
196
197static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
198  return RM.value_or(Reloc::Static);
199}
200
201extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
202  // Register the target.
203  RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
204
205  PassRegistry &PR = *PassRegistry::getPassRegistry();
206  initializeHexagonBitSimplifyPass(PR);
207  initializeHexagonConstExtendersPass(PR);
208  initializeHexagonConstPropagationPass(PR);
209  initializeHexagonCopyToCombinePass(PR);
210  initializeHexagonEarlyIfConversionPass(PR);
211  initializeHexagonGenMuxPass(PR);
212  initializeHexagonHardwareLoopsPass(PR);
213  initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
214  initializeHexagonNewValueJumpPass(PR);
215  initializeHexagonOptAddrModePass(PR);
216  initializeHexagonPacketizerPass(PR);
217  initializeHexagonRDFOptPass(PR);
218  initializeHexagonSplitDoubleRegsPass(PR);
219  initializeHexagonVectorCombineLegacyPass(PR);
220  initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
221  initializeHexagonVExtractPass(PR);
222  initializeHexagonDAGToDAGISelPass(PR);
223}
224
225HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
226                                           StringRef CPU, StringRef FS,
227                                           const TargetOptions &Options,
228                                           std::optional<Reloc::Model> RM,
229                                           std::optional<CodeModel::Model> CM,
230                                           CodeGenOpt::Level OL, bool JIT)
231    // Specify the vector alignment explicitly. For v512x1, the calculated
232    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
233    // the required minimum of 64 bytes.
234    : LLVMTargetMachine(
235          T,
236          "e-m:e-p:32:32:32-a:0-n16:32-"
237          "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
238          "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
239          TT, CPU, FS, Options, getEffectiveRelocModel(RM),
240          getEffectiveCodeModel(CM, CodeModel::Small),
241          (HexagonNoOpt ? CodeGenOpt::None : OL)),
242      TLOF(std::make_unique<HexagonTargetObjectFile>()) {
243  initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
244  initAsmInfo();
245}
246
247const HexagonSubtarget *
248HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
249  AttributeList FnAttrs = F.getAttributes();
250  Attribute CPUAttr =
251      FnAttrs.getFnAttr("target-cpu");
252  Attribute FSAttr =
253      FnAttrs.getFnAttr("target-features");
254
255  std::string CPU =
256      CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
257  std::string FS =
258      FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
259  // Append the preexisting target features last, so that +mattr overrides
260  // the "unsafe-fp-math" function attribute.
261  // Creating a separate target feature is not strictly necessary, it only
262  // exists to make "unsafe-fp-math" force creating a new subtarget.
263
264  if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
265    FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
266
267  auto &I = SubtargetMap[CPU + FS];
268  if (!I) {
269    // This needs to be done before we create a new subtarget since any
270    // creation will depend on the TM and the code generation flags on the
271    // function that reside in TargetOptions.
272    resetTargetOptions(F);
273    I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
274  }
275  return I.get();
276}
277
278void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
279  PB.registerLateLoopOptimizationsEPCallback(
280      [=](LoopPassManager &LPM, OptimizationLevel Level) {
281        LPM.addPass(HexagonLoopIdiomRecognitionPass());
282      });
283  PB.registerLoopOptimizerEndEPCallback(
284      [=](LoopPassManager &LPM, OptimizationLevel Level) {
285        LPM.addPass(HexagonVectorLoopCarriedReusePass());
286      });
287}
288
289TargetTransformInfo
290HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
291  return TargetTransformInfo(HexagonTTIImpl(this, F));
292}
293
294MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
295    BumpPtrAllocator &Allocator, const Function &F,
296    const TargetSubtargetInfo *STI) const {
297  return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
298      Allocator, F, STI);
299}
300
301HexagonTargetMachine::~HexagonTargetMachine() = default;
302
303namespace {
304/// Hexagon Code Generator Pass Configuration Options.
305class HexagonPassConfig : public TargetPassConfig {
306public:
307  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
308    : TargetPassConfig(TM, PM) {}
309
310  HexagonTargetMachine &getHexagonTargetMachine() const {
311    return getTM<HexagonTargetMachine>();
312  }
313
314  ScheduleDAGInstrs *
315  createMachineScheduler(MachineSchedContext *C) const override {
316    return createVLIWMachineSched(C);
317  }
318
319  void addIRPasses() override;
320  bool addInstSelector() override;
321  void addPreRegAlloc() override;
322  void addPostRegAlloc() override;
323  void addPreSched2() override;
324  void addPreEmitPass() override;
325};
326} // namespace
327
328TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
329  return new HexagonPassConfig(*this, PM);
330}
331
332void HexagonPassConfig::addIRPasses() {
333  TargetPassConfig::addIRPasses();
334  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
335
336  if (!NoOpt) {
337    if (EnableInstSimplify)
338      addPass(createInstSimplifyLegacyPass());
339    addPass(createDeadCodeEliminationPass());
340  }
341
342  addPass(createAtomicExpandPass());
343
344  if (!NoOpt) {
345    if (EnableInitialCFGCleanup)
346      addPass(createCFGSimplificationPass(SimplifyCFGOptions()
347                                              .forwardSwitchCondToPhi(true)
348                                              .convertSwitchRangeToICmp(true)
349                                              .convertSwitchToLookupTable(true)
350                                              .needCanonicalLoops(false)
351                                              .hoistCommonInsts(true)
352                                              .sinkCommonInsts(true)));
353    if (EnableLoopPrefetch)
354      addPass(createLoopDataPrefetchPass());
355    if (EnableVectorCombine)
356      addPass(createHexagonVectorCombineLegacyPass());
357    if (EnableCommGEP)
358      addPass(createHexagonCommonGEP());
359    // Replace certain combinations of shifts and ands with extracts.
360    if (EnableGenExtract)
361      addPass(createHexagonGenExtract());
362  }
363}
364
365bool HexagonPassConfig::addInstSelector() {
366  HexagonTargetMachine &TM = getHexagonTargetMachine();
367  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
368
369  if (!NoOpt)
370    addPass(createHexagonOptimizeSZextends());
371
372  addPass(createHexagonISelDag(TM, getOptLevel()));
373
374  if (!NoOpt) {
375    if (EnableVExtractOpt)
376      addPass(createHexagonVExtract());
377    // Create logical operations on predicate registers.
378    if (EnableGenPred)
379      addPass(createHexagonGenPredicate());
380    // Rotate loops to expose bit-simplification opportunities.
381    if (EnableLoopResched)
382      addPass(createHexagonLoopRescheduling());
383    // Split double registers.
384    if (!DisableHSDR)
385      addPass(createHexagonSplitDoubleRegs());
386    // Bit simplification.
387    if (EnableBitSimplify)
388      addPass(createHexagonBitSimplify());
389    addPass(createHexagonPeephole());
390    // Constant propagation.
391    if (!DisableHCP) {
392      addPass(createHexagonConstPropagationPass());
393      addPass(&UnreachableMachineBlockElimID);
394    }
395    if (EnableGenInsert)
396      addPass(createHexagonGenInsert());
397    if (EnableEarlyIf)
398      addPass(createHexagonEarlyIfConversion());
399  }
400
401  return false;
402}
403
404void HexagonPassConfig::addPreRegAlloc() {
405  if (getOptLevel() != CodeGenOpt::None) {
406    if (EnableCExtOpt)
407      addPass(createHexagonConstExtenders());
408    if (EnableExpandCondsets)
409      insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
410    if (!DisableStoreWidening)
411      addPass(createHexagonStoreWidening());
412    if (!DisableHardwareLoops)
413      addPass(createHexagonHardwareLoops());
414  }
415  if (TM->getOptLevel() >= CodeGenOpt::Default)
416    addPass(&MachinePipelinerID);
417}
418
419void HexagonPassConfig::addPostRegAlloc() {
420  if (getOptLevel() != CodeGenOpt::None) {
421    if (EnableRDFOpt)
422      addPass(createHexagonRDFOpt());
423    if (!DisableHexagonCFGOpt)
424      addPass(createHexagonCFGOptimizer());
425    if (!DisableAModeOpt)
426      addPass(createHexagonOptAddrMode());
427  }
428}
429
430void HexagonPassConfig::addPreSched2() {
431  addPass(createHexagonCopyToCombine());
432  if (getOptLevel() != CodeGenOpt::None)
433    addPass(&IfConverterID);
434  addPass(createHexagonSplitConst32AndConst64());
435}
436
437void HexagonPassConfig::addPreEmitPass() {
438  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
439
440  if (!NoOpt)
441    addPass(createHexagonNewValueJump());
442
443  addPass(createHexagonBranchRelaxation());
444
445  if (!NoOpt) {
446    if (!DisableHardwareLoops)
447      addPass(createHexagonFixupHwLoops());
448    // Generate MUX from pairs of conditional transfers.
449    if (EnableGenMux)
450      addPass(createHexagonGenMux());
451  }
452
453  // Packetization is mandatory: it handles gather/scatter at all opt levels.
454  addPass(createHexagonPacketizer(NoOpt));
455
456  if (EnableVectorPrint)
457    addPass(createHexagonVectorPrint());
458
459  // Add CFI instructions if necessary.
460  addPass(createHexagonCallFrameInformation());
461}
462