1/* Definitions of target machine for GNU compiler, 2 for Motorola M*CORE Processor. 3 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 2, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street, Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23#ifndef GCC_MCORE_H 24#define GCC_MCORE_H 25 26/* RBE: need to move these elsewhere. */ 27#undef LIKE_PPC_ABI 28#define MCORE_STRUCT_ARGS 29/* RBE: end of "move elsewhere". */ 30 31/* Run-time Target Specification. */ 32#define TARGET_MCORE 33 34/* Get tree.c to declare a target-specific specialization of 35 merge_decl_attributes. */ 36#define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1 37 38#define TARGET_CPU_CPP_BUILTINS() \ 39 do \ 40 { \ 41 builtin_define ("__mcore__"); \ 42 builtin_define ("__MCORE__"); \ 43 if (TARGET_LITTLE_END) \ 44 builtin_define ("__MCORELE__"); \ 45 else \ 46 builtin_define ("__MCOREBE__"); \ 47 if (TARGET_M340) \ 48 builtin_define ("__M340__"); \ 49 else \ 50 builtin_define ("__M210__"); \ 51 } \ 52 while (0) 53 54/* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC 55 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */ 56#undef CPP_SPEC 57#define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" 58 59/* We don't have a -lg library, so don't put it in the list. */ 60#undef LIB_SPEC 61#define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" 62 63#undef ASM_SPEC 64#define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" 65 66#undef LINK_SPEC 67#define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" 68 69#define TARGET_DEFAULT \ 70 (MASK_HARDLIT \ 71 | MASK_8ALIGN \ 72 | MASK_DIV \ 73 | MASK_RELAX_IMM \ 74 | MASK_M340 \ 75 | MASK_LITTLE_END) 76 77#ifndef MULTILIB_DEFAULTS 78#define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } 79#endif 80 81/* The ability to have 4 byte alignment is being suppressed for now. 82 If this ability is reenabled, you must disable the definition below 83 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ 84#undef TARGET_8ALIGN 85#define TARGET_8ALIGN 1 86 87extern char * mcore_current_function_name; 88 89/* The MCore ABI says that bitfields are unsigned by default. */ 90#define CC1_SPEC "-funsigned-bitfields" 91 92/* What options are we going to default to specific settings when 93 -O* happens; the user can subsequently override these settings. 94 95 Omitting the frame pointer is a very good idea on the MCore. 96 Scheduling isn't worth anything on the current MCore implementation. */ 97#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 98{ \ 99 if (LEVEL) \ 100 { \ 101 flag_no_function_cse = 1; \ 102 flag_omit_frame_pointer = 1; \ 103 \ 104 if (LEVEL >= 2) \ 105 { \ 106 flag_caller_saves = 0; \ 107 flag_schedule_insns = 0; \ 108 flag_schedule_insns_after_reload = 0; \ 109 } \ 110 } \ 111 if (SIZE) \ 112 { \ 113 target_flags &= ~MASK_HARDLIT; \ 114 } \ 115} 116 117/* What options are we going to force to specific settings, 118 regardless of what the user thought he wanted. 119 We also use this for some post-processing of options. */ 120#define OVERRIDE_OPTIONS mcore_override_options () 121 122/* Target machine storage Layout. */ 123 124#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 125 if (GET_MODE_CLASS (MODE) == MODE_INT \ 126 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 127 { \ 128 (MODE) = SImode; \ 129 (UNSIGNEDP) = 1; \ 130 } 131 132/* Define this if most significant bit is lowest numbered 133 in instructions that operate on numbered bit-fields. */ 134#define BITS_BIG_ENDIAN 0 135 136/* Define this if most significant byte of a word is the lowest numbered. */ 137#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) 138 139/* Define this if most significant word of a multiword number is the lowest 140 numbered. */ 141#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) 142 143#define LIBGCC2_WORDS_BIG_ENDIAN 1 144#ifdef __MCORELE__ 145#undef LIBGCC2_WORDS_BIG_ENDIAN 146#define LIBGCC2_WORDS_BIG_ENDIAN 0 147#endif 148 149#define MAX_BITS_PER_WORD 32 150 151/* Width of a word, in units (bytes). */ 152#define UNITS_PER_WORD 4 153 154/* A C expression for the size in bits of the type `long long' on the 155 target machine. If you don't define this, the default is two 156 words. */ 157#define LONG_LONG_TYPE_SIZE 64 158 159/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 160#define PARM_BOUNDARY 32 161 162/* Doubles must be aligned to an 8 byte boundary. */ 163#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 164 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \ 165 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY) 166 167/* Boundary (in *bits*) on which stack pointer should be aligned. */ 168#define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) 169 170/* Largest increment in UNITS we allow the stack to grow in a single operation. */ 171extern int mcore_stack_increment; 172#define STACK_UNITS_MAXSTEP 4096 173 174/* Allocation boundary (in *bits*) for the code of a function. */ 175#define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) 176 177/* Alignment of field after `int : 0' in a structure. */ 178#define EMPTY_FIELD_BOUNDARY 32 179 180/* No data type wants to be aligned rounder than this. */ 181#define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) 182 183/* The best alignment to use in cases where we have a choice. */ 184#define FASTEST_ALIGNMENT 32 185 186/* Every structures size must be a multiple of 8 bits. */ 187#define STRUCTURE_SIZE_BOUNDARY 8 188 189/* Look at the fundamental type that is used for a bit-field and use 190 that to impose alignment on the enclosing structure. 191 struct s {int a:8}; should have same alignment as "int", not "char". */ 192#define PCC_BITFIELD_TYPE_MATTERS 1 193 194/* Largest integer machine mode for structures. If undefined, the default 195 is GET_MODE_SIZE(DImode). */ 196#define MAX_FIXED_MODE_SIZE 32 197 198/* Make strings word-aligned so strcpy from constants will be faster. */ 199#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 200 ((TREE_CODE (EXP) == STRING_CST \ 201 && (ALIGN) < FASTEST_ALIGNMENT) \ 202 ? FASTEST_ALIGNMENT : (ALIGN)) 203 204/* Make arrays of chars word-aligned for the same reasons. */ 205#define DATA_ALIGNMENT(TYPE, ALIGN) \ 206 (TREE_CODE (TYPE) == ARRAY_TYPE \ 207 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 208 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 209 210/* Set this nonzero if move instructions will actually fail to work 211 when given unaligned data. */ 212#define STRICT_ALIGNMENT 1 213 214/* Standard register usage. */ 215 216/* Register allocation for our first guess 217 218 r0 stack pointer 219 r1 scratch, target reg for xtrb? 220 r2-r7 arguments. 221 r8-r14 call saved 222 r15 link register 223 ap arg pointer (doesn't really exist, always eliminated) 224 c c bit 225 fp frame pointer (doesn't really exist, always eliminated) 226 x19 two control registers. */ 227 228/* Number of actual hardware registers. 229 The hardware registers are assigned numbers for the compiler 230 from 0 to just below FIRST_PSEUDO_REGISTER. 231 All registers that the compiler knows about must be given numbers, 232 even those that are not normally considered general registers. 233 234 MCore has 16 integer registers and 2 control registers + the arg 235 pointer. */ 236 237#define FIRST_PSEUDO_REGISTER 20 238 239#define R1_REG 1 /* Where literals are forced. */ 240#define LK_REG 15 /* Overloaded on general register. */ 241#define AP_REG 16 /* Fake arg pointer register. */ 242/* RBE: mcore.md depends on CC_REG being set to 17. */ 243#define CC_REG 17 /* Can't name it C_REG. */ 244#define FP_REG 18 /* Fake frame pointer register. */ 245 246/* Specify the registers used for certain standard purposes. 247 The values of these macros are register numbers. */ 248 249 250#undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ 251#define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ 252#define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ 253 254/* The assembler's names for the registers. RFP need not always be used as 255 the Real framepointer; it can also be used as a normal general register. 256 Note that the name `fp' is horribly misleading since `fp' is in fact only 257 the argument-and-return-context pointer. */ 258#define REGISTER_NAMES \ 259{ \ 260 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 261 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 262 "apvirtual", "c", "fpvirtual", "x19" \ 263} 264 265/* 1 for registers that have pervasive standard uses 266 and are not available for the register allocator. */ 267#define FIXED_REGISTERS \ 268 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ 269 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} 270 271/* 1 for registers not available across function calls. 272 These must include the FIXED_REGISTERS and also any 273 registers that can be used without being saved. 274 The latter must include the registers where values are returned 275 and the register where structure-value addresses are passed. 276 Aside from that, you can include as many other registers as you like. */ 277 278/* RBE: r15 {link register} not available across calls, 279 But we don't mark it that way here.... */ 280#define CALL_USED_REGISTERS \ 281 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ 282 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} 283 284/* The order in which register should be allocated. */ 285#define REG_ALLOC_ORDER \ 286 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ 287 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} 288 289/* Return number of consecutive hard regs needed starting at reg REGNO 290 to hold something of mode MODE. 291 This is ordinarily the length in words of a value of mode MODE 292 but can be less for certain modes in special long registers. 293 294 On the MCore regs are UNITS_PER_WORD bits wide; */ 295#define HARD_REGNO_NREGS(REGNO, MODE) \ 296 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 297 298/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 299 We may keep double values in even registers. */ 300#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 301 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18)) 302 303/* Value is 1 if it is a good idea to tie two pseudo registers 304 when one has mode MODE1 and one has mode MODE2. 305 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 306 for any hard reg, then this must be 0 for correct output. */ 307#define MODES_TIEABLE_P(MODE1, MODE2) \ 308 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 309 310/* Value should be nonzero if functions must have frame pointers. 311 Zero means the frame pointer need not be set up (and parms may be accessed 312 via the stack pointer) in functions that seem suitable. */ 313#define FRAME_POINTER_REQUIRED 0 314 315/* Definitions for register eliminations. 316 317 We have two registers that can be eliminated on the MCore. First, the 318 frame pointer register can often be eliminated in favor of the stack 319 pointer register. Secondly, the argument pointer register can always be 320 eliminated; it is replaced with either the stack or frame pointer. */ 321 322/* Base register for access to arguments of the function. */ 323#define ARG_POINTER_REGNUM 16 324 325/* Register in which the static-chain is passed to a function. */ 326#define STATIC_CHAIN_REGNUM 1 327 328/* This is an array of structures. Each structure initializes one pair 329 of eliminable registers. The "from" register number is given first, 330 followed by "to". Eliminations of the same "from" register are listed 331 in order of preference. */ 332#define ELIMINABLE_REGS \ 333{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 334 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 335 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} 336 337/* Given FROM and TO register numbers, say whether this elimination 338 is allowed. */ 339#define CAN_ELIMINATE(FROM, TO) \ 340 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) 341 342/* Define the offset between two registers, one to be eliminated, and the other 343 its replacement, at the start of a routine. */ 344#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 345 OFFSET = mcore_initial_elimination_offset (FROM, TO) 346 347/* Define the classes of registers for register constraints in the 348 machine description. Also define ranges of constants. 349 350 One of the classes must always be named ALL_REGS and include all hard regs. 351 If there is more than one class, another class must be named NO_REGS 352 and contain no registers. 353 354 The name GENERAL_REGS must be the name of a class (or an alias for 355 another name such as ALL_REGS). This is the class of registers 356 that is allowed by "g" or "r" in a register constraint. 357 Also, registers outside this class are allocated only when 358 instructions express preferences for them. 359 360 The classes must be numbered in nondecreasing order; that is, 361 a larger-numbered class must never be contained completely 362 in a smaller-numbered class. 363 364 For any two classes, it is very desirable that there be another 365 class that represents their union. */ 366 367/* The MCore has only general registers. There are 368 also some special purpose registers: the T bit register, the 369 procedure Link and the Count Registers. */ 370enum reg_class 371{ 372 NO_REGS, 373 ONLYR1_REGS, 374 LRW_REGS, 375 GENERAL_REGS, 376 C_REGS, 377 ALL_REGS, 378 LIM_REG_CLASSES 379}; 380 381#define N_REG_CLASSES (int) LIM_REG_CLASSES 382 383/* Give names of register classes as strings for dump file. */ 384#define REG_CLASS_NAMES \ 385{ \ 386 "NO_REGS", \ 387 "ONLYR1_REGS", \ 388 "LRW_REGS", \ 389 "GENERAL_REGS", \ 390 "C_REGS", \ 391 "ALL_REGS", \ 392} 393 394/* Define which registers fit in which classes. 395 This is an initializer for a vector of HARD_REG_SET 396 of length N_REG_CLASSES. */ 397 398/* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ 399#define REG_CLASS_CONTENTS \ 400{ \ 401 {0x000000}, /* NO_REGS */ \ 402 {0x000002}, /* ONLYR1_REGS */ \ 403 {0x007FFE}, /* LRW_REGS */ \ 404 {0x01FFFF}, /* GENERAL_REGS */ \ 405 {0x020000}, /* C_REGS */ \ 406 {0x0FFFFF} /* ALL_REGS */ \ 407} 408 409/* The same information, inverted: 410 Return the class number of the smallest class containing 411 reg number REGNO. This could be a conditional expression 412 or could index an array. */ 413 414extern const int regno_reg_class[FIRST_PSEUDO_REGISTER]; 415#define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] 416 417/* When defined, the compiler allows registers explicitly used in the 418 rtl to be used as spill registers but prevents the compiler from 419 extending the lifetime of these registers. */ 420#define SMALL_REGISTER_CLASSES 1 421 422/* The class value for index registers, and the one for base regs. */ 423#define INDEX_REG_CLASS NO_REGS 424#define BASE_REG_CLASS GENERAL_REGS 425 426/* Get reg_class from a letter such as appears in the machine 427 description. */ 428extern const enum reg_class reg_class_from_letter[]; 429 430#define REG_CLASS_FROM_LETTER(C) \ 431 (ISLOWER (C) ? reg_class_from_letter[(C) - 'a'] : NO_REGS) 432 433/* The letters I, J, K, L, M, N, O, and P in a register constraint string 434 can be used to stand for particular ranges of immediate operands. 435 This macro defines what the ranges are. 436 C is the letter, and VALUE is a constant value. 437 Return 1 if VALUE is in the range specified by C. 438 I: loadable by movi (0..127) 439 J: arithmetic operand 1..32 440 K: shift operand 0..31 441 L: negative arithmetic operand -1..-32 442 M: powers of two, constants loadable by bgeni 443 N: powers of two minus 1, constants loadable by bmaski, including -1 444 O: allowed by cmov with two constants +/- 1 of each other 445 P: values we will generate 'inline' -- without an 'lrw' 446 447 Others defined for use after reload 448 Q: constant 1 449 R: a label 450 S: 0/1/2 cleared bits out of 32 [for bclri's] 451 T: 2 set bits out of 32 [for bseti's] 452 U: constant 0 453 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri 454 xxxT: 2 cleared bits out of 32. for pairs of bclris. */ 455#define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f) 456#define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32) 457#define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32) 458#define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31) 459#define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0) 460#define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0) 461#define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \ 462 CONST_OK_FOR_M(VALUE) || \ 463 CONST_OK_FOR_N(VALUE) || \ 464 CONST_OK_FOR_M((int)(VALUE) - 1) || \ 465 CONST_OK_FOR_N((int)(VALUE) + 1)) 466 467#define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE)) 468 469#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 470 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ 471 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ 472 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ 473 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ 474 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 475 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ 476 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ 477 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ 478 : 0) 479 480/* Similar, but for floating constants, and defining letters G and H. 481 Here VALUE is the CONST_DOUBLE rtx itself. */ 482#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 483 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \ 484 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \ 485 : 0) 486 487/* Letters in the range `Q' through `U' in a register constraint string 488 may be defined in a machine-dependent fashion to stand for arbitrary 489 operand types. */ 490#define EXTRA_CONSTRAINT(OP, C) \ 491 ((C) == 'R' ? (GET_CODE (OP) == MEM \ 492 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ 493 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ 494 && mcore_num_zeros (INTVAL (OP)) <= 2) \ 495 : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \ 496 && mcore_num_ones (INTVAL (OP)) == 2) \ 497 : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \ 498 && INTVAL(OP) == 1) \ 499 : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \ 500 && INTVAL(OP) == 0) \ 501 : 0) 502 503/* Given an rtx X being reloaded into a reg required to be 504 in class CLASS, return the class of reg to actually use. 505 In general this is just CLASS; but on some machines 506 in some cases it is preferable to use a more restrictive class. */ 507#define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) 508 509/* Return the register class of a scratch register needed to copy IN into 510 or out of a register in CLASS in MODE. If it can be done directly, 511 NO_REGS is returned. */ 512#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 513 mcore_secondary_reload_class (CLASS, MODE, X) 514 515/* Return the maximum number of consecutive registers 516 needed to represent mode MODE in a register of class CLASS. 517 518 On MCore this is the size of MODE in words. */ 519#define CLASS_MAX_NREGS(CLASS, MODE) \ 520 (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 521 522/* Stack layout; function entry, exit and calling. */ 523 524/* Define the number of register that can hold parameters. 525 These two macros are used only in other macro definitions below. */ 526#define NPARM_REGS 6 527#define FIRST_PARM_REG 2 528#define FIRST_RET_REG 2 529 530/* Define this if pushing a word on the stack 531 makes the stack pointer a smaller address. */ 532#define STACK_GROWS_DOWNWARD 533 534/* Offset within stack frame to start allocating local variables at. 535 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 536 first local allocated. Otherwise, it is the offset to the BEGINNING 537 of the first local allocated. */ 538#define STARTING_FRAME_OFFSET 0 539 540/* If defined, the maximum amount of space required for outgoing arguments 541 will be computed and placed into the variable 542 `current_function_outgoing_args_size'. No space will be pushed 543 onto the stack for each call; instead, the function prologue should 544 increase the stack frame size by this amount. */ 545#define ACCUMULATE_OUTGOING_ARGS 1 546 547/* Offset of first parameter from the argument pointer register value. */ 548#define FIRST_PARM_OFFSET(FNDECL) 0 549 550/* Value is the number of byte of arguments automatically 551 popped when returning from a subroutine call. 552 FUNTYPE is the data type of the function (as a tree), 553 or for a library call it is an identifier node for the subroutine name. 554 SIZE is the number of bytes of arguments passed on the stack. 555 556 On the MCore, the callee does not pop any of its arguments that were passed 557 on the stack. */ 558#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 559 560/* Define how to find the value returned by a function. 561 VALTYPE is the data type of the value (as a tree). 562 If the precise function being called is known, FUNC is its FUNCTION_DECL; 563 otherwise, FUNC is 0. */ 564#define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) 565 566/* Don't default to pcc-struct-return, because gcc is the only compiler, and 567 we want to retain compatibility with older gcc versions. */ 568#define DEFAULT_PCC_STRUCT_RETURN 0 569 570/* Define how to find the value returned by a library function 571 assuming the value has mode MODE. */ 572#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG) 573 574/* 1 if N is a possible register number for a function value. 575 On the MCore, only r4 can return results. */ 576#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) 577 578/* 1 if N is a possible register number for function argument passing. */ 579#define FUNCTION_ARG_REGNO_P(REGNO) \ 580 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) 581 582/* Define a data type for recording info about an argument list 583 during the scan of that argument list. This data type should 584 hold all necessary information about the function itself 585 and about the args processed so far, enough to enable macros 586 such as FUNCTION_ARG to determine where the next arg should go. 587 588 On MCore, this is a single integer, which is a number of words 589 of arguments scanned so far (including the invisible argument, 590 if any, which holds the structure-value-address). 591 Thus NARGREGS or more means all following args should go on the stack. */ 592#define CUMULATIVE_ARGS int 593 594#define ROUND_ADVANCE(SIZE) \ 595 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 596 597/* Round a register number up to a proper boundary for an arg of mode 598 MODE. 599 600 We round to an even reg for things larger than a word. */ 601#define ROUND_REG(X, MODE) \ 602 ((TARGET_8ALIGN \ 603 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 604 ? ((X) + ((X) & 1)) : (X)) 605 606 607/* Initialize a variable CUM of type CUMULATIVE_ARGS 608 for a call to a function whose data type is FNTYPE. 609 For a library call, FNTYPE is 0. 610 611 On MCore, the offset always starts at 0: the first parm reg is always 612 the same reg. */ 613#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 614 ((CUM) = 0) 615 616/* Update the data in CUM to advance over an argument 617 of mode MODE and data type TYPE. 618 (TYPE is null for libcalls where that information may not be 619 available.) */ 620#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 621 ((CUM) = (ROUND_REG ((CUM), (MODE)) \ 622 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \ 623 624/* Define where to put the arguments to a function. */ 625#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 626 mcore_function_arg (CUM, MODE, TYPE, NAMED) 627 628/* Call the function profiler with a given profile label. */ 629#define FUNCTION_PROFILER(STREAM,LABELNO) \ 630{ \ 631 fprintf (STREAM, " trap 1\n"); \ 632 fprintf (STREAM, " .align 2\n"); \ 633 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ 634} 635 636/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 637 the stack pointer does not matter. The value is tested only in 638 functions that have frame pointers. 639 No definition is equivalent to always zero. */ 640#define EXIT_IGNORE_STACK 0 641 642/* Output assembler code for a block containing the constant parts 643 of a trampoline, leaving space for the variable parts. 644 645 On the MCore, the trampoline looks like: 646 lrw r1, function 647 lrw r13, area 648 jmp r13 649 or r0, r0 650 .literals */ 651#define TRAMPOLINE_TEMPLATE(FILE) \ 652{ \ 653 fprintf ((FILE), " .short 0x7102\n"); \ 654 fprintf ((FILE), " .short 0x7d02\n"); \ 655 fprintf ((FILE), " .short 0x00cd\n"); \ 656 fprintf ((FILE), " .short 0x1e00\n"); \ 657 fprintf ((FILE), " .long 0\n"); \ 658 fprintf ((FILE), " .long 0\n"); \ 659} 660 661/* Length in units of the trampoline for entering a nested function. */ 662#define TRAMPOLINE_SIZE 12 663 664/* Alignment required for a trampoline in bits. */ 665#define TRAMPOLINE_ALIGNMENT 32 666 667/* Emit RTL insns to initialize the variable parts of a trampoline. 668 FNADDR is an RTX for the address of the function's pure code. 669 CXT is an RTX for the static chain value for the function. */ 670#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 671{ \ 672 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \ 673 (CXT)); \ 674 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \ 675 (FNADDR)); \ 676} 677 678/* Macros to check register numbers against specific register classes. */ 679 680/* These assume that REGNO is a hard or pseudo reg number. 681 They give nonzero only if REGNO is a hard reg of the suitable class 682 or a pseudo reg currently allocated to a suitable hard reg. 683 Since they use reg_renumber, they are safe only once reg_renumber 684 has been allocated, which happens in local-alloc.c. */ 685#define REGNO_OK_FOR_BASE_P(REGNO) \ 686 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) 687 688#define REGNO_OK_FOR_INDEX_P(REGNO) 0 689 690/* Maximum number of registers that can appear in a valid memory 691 address. */ 692#define MAX_REGS_PER_ADDRESS 1 693 694/* Recognize any constant value that is a valid address. */ 695#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 696 697/* Nonzero if the constant value X is a legitimate general operand. 698 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 699 700 On the MCore, allow anything but a double. */ 701#define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE) 702 703/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 704 and check its validity for a certain class. 705 We have two alternate definitions for each of them. 706 The usual definition accepts all pseudo regs; the other rejects 707 them unless they have been allocated suitable hard regs. 708 The symbol REG_OK_STRICT causes the latter definition to be used. */ 709#ifndef REG_OK_STRICT 710 711/* Nonzero if X is a hard reg that can be used as a base reg 712 or if it is a pseudo reg. */ 713#define REG_OK_FOR_BASE_P(X) \ 714 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 715 716/* Nonzero if X is a hard reg that can be used as an index 717 or if it is a pseudo reg. */ 718#define REG_OK_FOR_INDEX_P(X) 0 719 720#else 721 722/* Nonzero if X is a hard reg that can be used as a base reg. */ 723#define REG_OK_FOR_BASE_P(X) \ 724 REGNO_OK_FOR_BASE_P (REGNO (X)) 725 726/* Nonzero if X is a hard reg that can be used as an index. */ 727#define REG_OK_FOR_INDEX_P(X) 0 728 729#endif 730/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 731 that is a valid memory address for an instruction. 732 The MODE argument is the machine mode for the MEM expression 733 that wants to use this address. 734 735 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 736#define BASE_REGISTER_RTX_P(X) \ 737 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 738 739#define INDEX_REGISTER_RTX_P(X) \ 740 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 741 742 743/* Jump to LABEL if X is a valid address RTX. This must also take 744 REG_OK_STRICT into account when deciding about valid registers, but it uses 745 the above macros so we are in luck. 746 747 Allow REG 748 REG+disp 749 750 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, 751 and for DI is 0..56 because we use two SI loads, etc. */ 752#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ 753 do \ 754 { \ 755 if (GET_CODE (OP) == CONST_INT) \ 756 { \ 757 if (GET_MODE_SIZE (MODE) >= 4 \ 758 && (((unsigned)INTVAL (OP)) % 4) == 0 \ 759 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \ 760 goto LABEL; \ 761 if (GET_MODE_SIZE (MODE) == 2 \ 762 && (((unsigned)INTVAL (OP)) % 2) == 0 \ 763 && ((unsigned)INTVAL (OP)) <= 30) \ 764 goto LABEL; \ 765 if (GET_MODE_SIZE (MODE) == 1 \ 766 && ((unsigned)INTVAL (OP)) <= 15) \ 767 goto LABEL; \ 768 } \ 769 } \ 770 while (0) 771 772#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 773{ \ 774 if (BASE_REGISTER_RTX_P (X)) \ 775 goto LABEL; \ 776 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \ 777 { \ 778 rtx xop0 = XEXP (X,0); \ 779 rtx xop1 = XEXP (X,1); \ 780 if (BASE_REGISTER_RTX_P (xop0)) \ 781 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 782 if (BASE_REGISTER_RTX_P (xop1)) \ 783 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 784 } \ 785} 786 787/* Go to LABEL if ADDR (a legitimate address expression) 788 has an effect that depends on the machine mode it is used for. */ 789#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 790{ \ 791 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 792 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 793 goto LABEL; \ 794} 795 796/* Specify the machine mode that this machine uses 797 for the index in the tablejump instruction. */ 798#define CASE_VECTOR_MODE SImode 799 800/* 'char' is signed by default. */ 801#define DEFAULT_SIGNED_CHAR 0 802 803/* The type of size_t unsigned int. */ 804#define SIZE_TYPE "unsigned int" 805 806/* Max number of bytes we can move from memory to memory 807 in one reasonably fast instruction. */ 808#define MOVE_MAX 4 809 810/* Define if operations between registers always perform the operation 811 on the full register even if a narrower mode is specified. */ 812#define WORD_REGISTER_OPERATIONS 813 814/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 815 will either zero-extend or sign-extend. The value of this macro should 816 be the code that says which one of the two operations is implicitly 817 done, UNKNOWN if none. */ 818#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 819 820/* Nonzero if access to memory by bytes is slow and undesirable. */ 821#define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES 822 823/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected 824 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this 825 target. */ 826#define SHIFT_COUNT_TRUNCATED 0 827 828/* All integers have the same format so truncation is easy. */ 829#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 830 831/* Define this if addresses of constant functions 832 shouldn't be put through pseudo regs where they can be cse'd. 833 Desirable on machines where ordinary constants are expensive 834 but a CALL with constant address is cheap. */ 835/* Why is this defined??? -- dac */ 836#define NO_FUNCTION_CSE 1 837 838/* The machine modes of pointers and functions. */ 839#define Pmode SImode 840#define FUNCTION_MODE Pmode 841 842/* Compute extra cost of moving data between one register class 843 and another. All register moves are cheap. */ 844#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 845 846#define WORD_REGISTER_OPERATIONS 847 848/* Assembler output control. */ 849#define ASM_COMMENT_START "\t//" 850 851#define ASM_APP_ON "// inline asm begin\n" 852#define ASM_APP_OFF "// inline asm end\n" 853 854#define FILE_ASM_OP "\t.file\n" 855 856/* Switch to the text or data segment. */ 857#define TEXT_SECTION_ASM_OP "\t.text" 858#define DATA_SECTION_ASM_OP "\t.data" 859 860/* Switch into a generic section. */ 861#undef TARGET_ASM_NAMED_SECTION 862#define TARGET_ASM_NAMED_SECTION mcore_asm_named_section 863 864/* This is how to output an insn to push a register on the stack. 865 It need not be very fast code. */ 866#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 867 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ 868 reg_names[STACK_POINTER_REGNUM], \ 869 (STACK_BOUNDARY / BITS_PER_UNIT), \ 870 reg_names[REGNO], \ 871 reg_names[STACK_POINTER_REGNUM]) 872 873/* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ 874#define REG_PUSH_LENGTH 2 875 876/* This is how to output an insn to pop a register from the stack. */ 877#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 878 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ 879 reg_names[REGNO], \ 880 reg_names[STACK_POINTER_REGNUM], \ 881 reg_names[STACK_POINTER_REGNUM], \ 882 (STACK_BOUNDARY / BITS_PER_UNIT)) 883 884 885/* Output a reference to a label. */ 886#undef ASM_OUTPUT_LABELREF 887#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 888 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ 889 (* targetm.strip_name_encoding) (NAME)) 890 891/* This is how to output an assembler line 892 that says to advance the location counter 893 to a multiple of 2**LOG bytes. */ 894#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 895 if ((LOG) != 0) \ 896 fprintf (FILE, "\t.align\t%d\n", LOG) 897 898#ifndef ASM_DECLARE_RESULT 899#define ASM_DECLARE_RESULT(FILE, RESULT) 900#endif 901 902#define MULTIPLE_SYMBOL_SPACES 1 903 904#define SUPPORTS_ONE_ONLY 1 905 906/* A pair of macros to output things for the callgraph data. 907 VALUE means (to the tools that reads this info later): 908 0 a call from src to dst 909 1 the call is special (e.g. dst is "unknown" or "alloca") 910 2 the call is special (e.g., the src is a table instead of routine) 911 912 Frame sizes are augmented with timestamps to help later tools 913 differentiate between static entities with same names in different 914 files. */ 915extern long mcore_current_compilation_timestamp; 916#define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ 917 do \ 918 { \ 919 if (mcore_current_compilation_timestamp == 0) \ 920 mcore_current_compilation_timestamp = time (0); \ 921 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ 922 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ 923 } \ 924 while (0) 925 926#define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ 927 do \ 928 { \ 929 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ 930 (SRCNAME), (DSTNAME), (VALUE)); \ 931 } \ 932 while (0) 933 934/* Globalizing directive for a label. */ 935#define GLOBAL_ASM_OP "\t.export\t" 936 937/* The prefix to add to user-visible assembler symbols. */ 938#undef USER_LABEL_PREFIX 939#define USER_LABEL_PREFIX "" 940 941/* Make an internal label into a string. */ 942#undef ASM_GENERATE_INTERNAL_LABEL 943#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 944 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) 945 946/* Jump tables must be 32 bit aligned. */ 947#undef ASM_OUTPUT_CASE_LABEL 948#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ 949 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); 950 951/* Output a relative address. Not needed since jump tables are absolute 952 but we must define it anyway. */ 953#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 954 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) 955 956/* Output an element of a dispatch table. */ 957#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 958 fprintf (STREAM, "\t.long\t.L%d\n", VALUE) 959 960/* Output various types of constants. */ 961 962/* This is how to output an assembler line 963 that says to advance the location counter by SIZE bytes. */ 964#undef ASM_OUTPUT_SKIP 965#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 966 fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE)) 967 968/* This says how to output an assembler line 969 to define a global common symbol, with alignment information. */ 970/* XXX - for now we ignore the alignment. */ 971#undef ASM_OUTPUT_ALIGNED_COMMON 972#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 973 do \ 974 { \ 975 if (mcore_dllexport_name_p (NAME)) \ 976 MCORE_EXPORT_NAME (FILE, NAME) \ 977 if (! mcore_dllimport_name_p (NAME)) \ 978 { \ 979 fputs ("\t.comm\t", FILE); \ 980 assemble_name (FILE, NAME); \ 981 fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \ 982 } \ 983 } \ 984 while (0) 985 986/* This says how to output an assembler line 987 to define a local common symbol.... */ 988#undef ASM_OUTPUT_LOCAL 989#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 990 (fputs ("\t.lcomm\t", FILE), \ 991 assemble_name (FILE, NAME), \ 992 fprintf (FILE, ",%d\n", (int)SIZE)) 993 994/* ... and how to define a local common symbol whose alignment 995 we wish to specify. ALIGN comes in as bits, we have to turn 996 it into bytes. */ 997#undef ASM_OUTPUT_ALIGNED_LOCAL 998#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 999 do \ 1000 { \ 1001 fputs ("\t.bss\t", (FILE)); \ 1002 assemble_name ((FILE), (NAME)); \ 1003 fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 1004 } \ 1005 while (0) 1006 1007/* Print operand X (an rtx) in assembler syntax to file FILE. 1008 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1009 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1010#define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE) 1011 1012/* Print a memory address as an operand to reference that memory location. */ 1013#define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X) 1014 1015#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1016 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!') 1017 1018#endif /* ! GCC_MCORE_H */ 1019