1/* 2 * ALSA modem driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version 7 * of ALSA ICH sound driver intel8x0.c . 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26#include <sound/driver.h> 27#include <asm/io.h> 28#include <linux/delay.h> 29#include <linux/interrupt.h> 30#include <linux/init.h> 31#include <linux/pci.h> 32#include <linux/slab.h> 33#include <linux/moduleparam.h> 34#include <sound/core.h> 35#include <sound/pcm.h> 36#include <sound/ac97_codec.h> 37#include <sound/info.h> 38#include <sound/initval.h> 39 40MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 41MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " 42 "SiS 7013; NVidia MCP/2/2S/3 modems"); 43MODULE_LICENSE("GPL"); 44MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 45 "{Intel,82901AB-ICH0}," 46 "{Intel,82801BA-ICH2}," 47 "{Intel,82801CA-ICH3}," 48 "{Intel,82801DB-ICH4}," 49 "{Intel,ICH5}," 50 "{Intel,ICH6}," 51 "{Intel,ICH7}," 52 "{Intel,MX440}," 53 "{SiS,7013}," 54 "{NVidia,NForce Modem}," 55 "{NVidia,NForce2 Modem}," 56 "{NVidia,NForce2s Modem}," 57 "{NVidia,NForce3 Modem}," 58 "{AMD,AMD768}}"); 59 60static int index = -2; /* Exclude the first card */ 61static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 62static int ac97_clock; 63 64module_param(index, int, 0444); 65MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 66module_param(id, charp, 0444); 67MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 68module_param(ac97_clock, int, 0444); 69MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 70 71/* just for backward compatibility */ 72static int enable; 73module_param(enable, bool, 0444); 74 75/* 76 * Direct registers 77 */ 78enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 79 80#define ICHREG(x) ICH_REG_##x 81 82#define DEFINE_REGSET(name,base) \ 83enum { \ 84 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 85 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 86 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 87 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 88 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 89 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 90 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 91}; 92 93/* busmaster blocks */ 94DEFINE_REGSET(OFF, 0); /* offset */ 95 96/* values for each busmaster block */ 97 98/* LVI */ 99#define ICH_REG_LVI_MASK 0x1f 100 101/* SR */ 102#define ICH_FIFOE 0x10 /* FIFO error */ 103#define ICH_BCIS 0x08 /* buffer completion interrupt status */ 104#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 105#define ICH_CELV 0x02 /* current equals last valid */ 106#define ICH_DCH 0x01 /* DMA controller halted */ 107 108/* PIV */ 109#define ICH_REG_PIV_MASK 0x1f /* mask */ 110 111/* CR */ 112#define ICH_IOCE 0x10 /* interrupt on completion enable */ 113#define ICH_FEIE 0x08 /* fifo error interrupt enable */ 114#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 115#define ICH_RESETREGS 0x02 /* reset busmaster registers */ 116#define ICH_STARTBM 0x01 /* start busmaster operation */ 117 118 119/* global block */ 120#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 121#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 122#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 123#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 124#define ICH_ACLINK 0x00000008 /* AClink shut off */ 125#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 126#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 127#define ICH_GIE 0x00000001 /* GPI interrupt enable */ 128#define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 129#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 130#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 131#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 132#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 133#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 134#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 135#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 136#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 137#define ICH_MD3 0x00020000 /* modem power down semaphore */ 138#define ICH_AD3 0x00010000 /* audio power down semaphore */ 139#define ICH_RCS 0x00008000 /* read completion status */ 140#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 141#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 142#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 143#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 144#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 145#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 146#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 147#define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 148#define ICH_POINT 0x00000040 /* playback interrupt */ 149#define ICH_PIINT 0x00000020 /* capture interrupt */ 150#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 151#define ICH_MOINT 0x00000004 /* modem playback interrupt */ 152#define ICH_MIINT 0x00000002 /* modem capture interrupt */ 153#define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 154#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 155#define ICH_CAS 0x01 /* codec access semaphore */ 156 157#define ICH_MAX_FRAGS 32 /* max hw frags */ 158 159 160/* 161 * 162 */ 163 164enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 165enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 166 167#define get_ichdev(substream) (substream->runtime->private_data) 168 169struct ichdev { 170 unsigned int ichd; /* ich device number */ 171 unsigned long reg_offset; /* offset to bmaddr */ 172 u32 *bdbar; /* CPU address (32bit) */ 173 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 174 struct snd_pcm_substream *substream; 175 unsigned int physbuf; /* physical address (32bit) */ 176 unsigned int size; 177 unsigned int fragsize; 178 unsigned int fragsize1; 179 unsigned int position; 180 int frags; 181 int lvi; 182 int lvi_frag; 183 int civ; 184 int ack; 185 int ack_reload; 186 unsigned int ack_bit; 187 unsigned int roff_sr; 188 unsigned int roff_picb; 189 unsigned int int_sta_mask; /* interrupt status mask */ 190 unsigned int ali_slot; /* ALI DMA slot */ 191 struct snd_ac97 *ac97; 192}; 193 194struct intel8x0m { 195 unsigned int device_type; 196 197 int irq; 198 199 void __iomem *addr; 200 void __iomem *bmaddr; 201 202 struct pci_dev *pci; 203 struct snd_card *card; 204 205 int pcm_devs; 206 struct snd_pcm *pcm[2]; 207 struct ichdev ichd[2]; 208 209 unsigned int in_ac97_init: 1; 210 211 struct snd_ac97_bus *ac97_bus; 212 struct snd_ac97 *ac97; 213 214 spinlock_t reg_lock; 215 216 struct snd_dma_buffer bdbars; 217 u32 bdbars_count; 218 u32 int_sta_reg; /* interrupt status register */ 219 u32 int_sta_mask; /* interrupt status mask */ 220 unsigned int pcm_pos_shift; 221}; 222 223static struct pci_device_id snd_intel8x0m_ids[] = { 224 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 225 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 226 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 227 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 228 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */ 229 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */ 230 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */ 231 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */ 232 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 233 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 234 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */ 235 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 236 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 237 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */ 238 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 239 { 0, } 240}; 241 242MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 243 244/* 245 * Lowlevel I/O - busmaster 246 */ 247 248static inline u8 igetbyte(struct intel8x0m *chip, u32 offset) 249{ 250 return ioread8(chip->bmaddr + offset); 251} 252 253static inline u16 igetword(struct intel8x0m *chip, u32 offset) 254{ 255 return ioread16(chip->bmaddr + offset); 256} 257 258static inline u32 igetdword(struct intel8x0m *chip, u32 offset) 259{ 260 return ioread32(chip->bmaddr + offset); 261} 262 263static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) 264{ 265 iowrite8(val, chip->bmaddr + offset); 266} 267 268static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) 269{ 270 iowrite16(val, chip->bmaddr + offset); 271} 272 273static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) 274{ 275 iowrite32(val, chip->bmaddr + offset); 276} 277 278/* 279 * Lowlevel I/O - AC'97 registers 280 */ 281 282static inline u16 iagetword(struct intel8x0m *chip, u32 offset) 283{ 284 return ioread16(chip->addr + offset); 285} 286 287static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) 288{ 289 iowrite16(val, chip->addr + offset); 290} 291 292/* 293 * Basic I/O 294 */ 295 296/* 297 * access to AC97 codec via normal i/o (for ICH and SIS7013) 298 */ 299 300/* return the GLOB_STA bit for the corresponding codec */ 301static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) 302{ 303 static unsigned int codec_bit[3] = { 304 ICH_PCR, ICH_SCR, ICH_TCR 305 }; 306 snd_assert(codec < 3, return ICH_PCR); 307 return codec_bit[codec]; 308} 309 310static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) 311{ 312 int time; 313 314 if (codec > 1) 315 return -EIO; 316 codec = get_ich_codec_bit(chip, codec); 317 318 /* codec ready ? */ 319 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 320 return -EIO; 321 322 /* Anyone holding a semaphore for 1 msec should be shot... */ 323 time = 100; 324 do { 325 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 326 return 0; 327 udelay(10); 328 } while (time--); 329 330 /* access to some forbidden (non existant) ac97 registers will not 331 * reset the semaphore. So even if you don't get the semaphore, still 332 * continue the access. We don't need the semaphore anyway. */ 333 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 334 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 335 iagetword(chip, 0); /* clear semaphore flag */ 336 /* I don't care about the semaphore */ 337 return -EBUSY; 338} 339 340static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 341 unsigned short reg, 342 unsigned short val) 343{ 344 struct intel8x0m *chip = ac97->private_data; 345 346 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 347 if (! chip->in_ac97_init) 348 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 349 } 350 iaputword(chip, reg + ac97->num * 0x80, val); 351} 352 353static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 354 unsigned short reg) 355{ 356 struct intel8x0m *chip = ac97->private_data; 357 unsigned short res; 358 unsigned int tmp; 359 360 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 361 if (! chip->in_ac97_init) 362 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 363 res = 0xffff; 364 } else { 365 res = iagetword(chip, reg + ac97->num * 0x80); 366 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 367 /* reset RCS and preserve other R/WC bits */ 368 iputdword(chip, ICHREG(GLOB_STA), 369 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 370 if (! chip->in_ac97_init) 371 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 372 res = 0xffff; 373 } 374 } 375 if (reg == AC97_GPIO_STATUS) 376 iagetword(chip, 0); /* clear semaphore */ 377 return res; 378} 379 380 381/* 382 * DMA I/O 383 */ 384static void snd_intel8x0_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) 385{ 386 int idx; 387 u32 *bdbar = ichdev->bdbar; 388 unsigned long port = ichdev->reg_offset; 389 390 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 391 if (ichdev->size == ichdev->fragsize) { 392 ichdev->ack_reload = ichdev->ack = 2; 393 ichdev->fragsize1 = ichdev->fragsize >> 1; 394 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 395 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 396 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 397 ichdev->fragsize1 >> chip->pcm_pos_shift); 398 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 399 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 400 ichdev->fragsize1 >> chip->pcm_pos_shift); 401 } 402 ichdev->frags = 2; 403 } else { 404 ichdev->ack_reload = ichdev->ack = 1; 405 ichdev->fragsize1 = ichdev->fragsize; 406 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 407 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 408 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 409 ichdev->fragsize >> chip->pcm_pos_shift); 410 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 411 } 412 ichdev->frags = ichdev->size / ichdev->fragsize; 413 } 414 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 415 ichdev->civ = 0; 416 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 417 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 418 ichdev->position = 0; 419 /* clear interrupts */ 420 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 421} 422 423/* 424 * Interrupt handler 425 */ 426 427static inline void snd_intel8x0_update(struct intel8x0m *chip, struct ichdev *ichdev) 428{ 429 unsigned long port = ichdev->reg_offset; 430 int civ, i, step; 431 int ack = 0; 432 433 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 434 if (civ == ichdev->civ) { 435 // snd_printd("civ same %d\n", civ); 436 step = 1; 437 ichdev->civ++; 438 ichdev->civ &= ICH_REG_LVI_MASK; 439 } else { 440 step = civ - ichdev->civ; 441 if (step < 0) 442 step += ICH_REG_LVI_MASK + 1; 443 // if (step != 1) 444 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 445 ichdev->civ = civ; 446 } 447 448 ichdev->position += step * ichdev->fragsize1; 449 ichdev->position %= ichdev->size; 450 ichdev->lvi += step; 451 ichdev->lvi &= ICH_REG_LVI_MASK; 452 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 453 for (i = 0; i < step; i++) { 454 ichdev->lvi_frag++; 455 ichdev->lvi_frag %= ichdev->frags; 456 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + 457 ichdev->lvi_frag * 458 ichdev->fragsize1); 459 if (--ichdev->ack == 0) { 460 ichdev->ack = ichdev->ack_reload; 461 ack = 1; 462 } 463 } 464 if (ack && ichdev->substream) { 465 spin_unlock(&chip->reg_lock); 466 snd_pcm_period_elapsed(ichdev->substream); 467 spin_lock(&chip->reg_lock); 468 } 469 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 470} 471 472static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 473{ 474 struct intel8x0m *chip = dev_id; 475 struct ichdev *ichdev; 476 unsigned int status; 477 unsigned int i; 478 479 spin_lock(&chip->reg_lock); 480 status = igetdword(chip, chip->int_sta_reg); 481 if (status == 0xffffffff) { /* we are not yet resumed */ 482 spin_unlock(&chip->reg_lock); 483 return IRQ_NONE; 484 } 485 if ((status & chip->int_sta_mask) == 0) { 486 if (status) 487 iputdword(chip, chip->int_sta_reg, status); 488 spin_unlock(&chip->reg_lock); 489 return IRQ_NONE; 490 } 491 492 for (i = 0; i < chip->bdbars_count; i++) { 493 ichdev = &chip->ichd[i]; 494 if (status & ichdev->int_sta_mask) 495 snd_intel8x0_update(chip, ichdev); 496 } 497 498 /* ack them */ 499 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 500 spin_unlock(&chip->reg_lock); 501 502 return IRQ_HANDLED; 503} 504 505/* 506 * PCM part 507 */ 508 509static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 510{ 511 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 512 struct ichdev *ichdev = get_ichdev(substream); 513 unsigned char val = 0; 514 unsigned long port = ichdev->reg_offset; 515 516 switch (cmd) { 517 case SNDRV_PCM_TRIGGER_START: 518 case SNDRV_PCM_TRIGGER_RESUME: 519 val = ICH_IOCE | ICH_STARTBM; 520 break; 521 case SNDRV_PCM_TRIGGER_STOP: 522 case SNDRV_PCM_TRIGGER_SUSPEND: 523 val = 0; 524 break; 525 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 526 val = ICH_IOCE; 527 break; 528 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 529 val = ICH_IOCE | ICH_STARTBM; 530 break; 531 default: 532 return -EINVAL; 533 } 534 iputbyte(chip, port + ICH_REG_OFF_CR, val); 535 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 536 /* wait until DMA stopped */ 537 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 538 /* reset whole DMA things */ 539 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 540 } 541 return 0; 542} 543 544static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 545 struct snd_pcm_hw_params *hw_params) 546{ 547 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 548} 549 550static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 551{ 552 return snd_pcm_lib_free_pages(substream); 553} 554 555static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 556{ 557 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 558 struct ichdev *ichdev = get_ichdev(substream); 559 size_t ptr1, ptr; 560 561 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 562 if (ptr1 != 0) 563 ptr = ichdev->fragsize1 - ptr1; 564 else 565 ptr = 0; 566 ptr += ichdev->position; 567 if (ptr >= ichdev->size) 568 return 0; 569 return bytes_to_frames(substream->runtime, ptr); 570} 571 572static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) 573{ 574 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 575 struct snd_pcm_runtime *runtime = substream->runtime; 576 struct ichdev *ichdev = get_ichdev(substream); 577 578 ichdev->physbuf = runtime->dma_addr; 579 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 580 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 581 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 582 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 583 snd_intel8x0_setup_periods(chip, ichdev); 584 return 0; 585} 586 587static struct snd_pcm_hardware snd_intel8x0m_stream = 588{ 589 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 590 SNDRV_PCM_INFO_BLOCK_TRANSFER | 591 SNDRV_PCM_INFO_MMAP_VALID | 592 SNDRV_PCM_INFO_PAUSE | 593 SNDRV_PCM_INFO_RESUME), 594 .formats = SNDRV_PCM_FMTBIT_S16_LE, 595 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 596 .rate_min = 8000, 597 .rate_max = 16000, 598 .channels_min = 1, 599 .channels_max = 1, 600 .buffer_bytes_max = 64 * 1024, 601 .period_bytes_min = 32, 602 .period_bytes_max = 64 * 1024, 603 .periods_min = 1, 604 .periods_max = 1024, 605 .fifo_size = 0, 606}; 607 608 609static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 610{ 611 static unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 612 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 613 .count = ARRAY_SIZE(rates), 614 .list = rates, 615 .mask = 0, 616 }; 617 struct snd_pcm_runtime *runtime = substream->runtime; 618 int err; 619 620 ichdev->substream = substream; 621 runtime->hw = snd_intel8x0m_stream; 622 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 623 &hw_constraints_rates); 624 if ( err < 0 ) 625 return err; 626 runtime->private_data = ichdev; 627 return 0; 628} 629 630static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) 631{ 632 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 633 634 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 635} 636 637static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) 638{ 639 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 640 641 chip->ichd[ICHD_MDMOUT].substream = NULL; 642 return 0; 643} 644 645static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) 646{ 647 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 648 649 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 650} 651 652static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) 653{ 654 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 655 656 chip->ichd[ICHD_MDMIN].substream = NULL; 657 return 0; 658} 659 660 661static struct snd_pcm_ops snd_intel8x0m_playback_ops = { 662 .open = snd_intel8x0m_playback_open, 663 .close = snd_intel8x0m_playback_close, 664 .ioctl = snd_pcm_lib_ioctl, 665 .hw_params = snd_intel8x0_hw_params, 666 .hw_free = snd_intel8x0_hw_free, 667 .prepare = snd_intel8x0m_pcm_prepare, 668 .trigger = snd_intel8x0_pcm_trigger, 669 .pointer = snd_intel8x0_pcm_pointer, 670}; 671 672static struct snd_pcm_ops snd_intel8x0m_capture_ops = { 673 .open = snd_intel8x0m_capture_open, 674 .close = snd_intel8x0m_capture_close, 675 .ioctl = snd_pcm_lib_ioctl, 676 .hw_params = snd_intel8x0_hw_params, 677 .hw_free = snd_intel8x0_hw_free, 678 .prepare = snd_intel8x0m_pcm_prepare, 679 .trigger = snd_intel8x0_pcm_trigger, 680 .pointer = snd_intel8x0_pcm_pointer, 681}; 682 683 684struct ich_pcm_table { 685 char *suffix; 686 struct snd_pcm_ops *playback_ops; 687 struct snd_pcm_ops *capture_ops; 688 size_t prealloc_size; 689 size_t prealloc_max_size; 690 int ac97_idx; 691}; 692 693static int __devinit snd_intel8x0_pcm1(struct intel8x0m *chip, int device, 694 struct ich_pcm_table *rec) 695{ 696 struct snd_pcm *pcm; 697 int err; 698 char name[32]; 699 700 if (rec->suffix) 701 sprintf(name, "Intel ICH - %s", rec->suffix); 702 else 703 strcpy(name, "Intel ICH"); 704 err = snd_pcm_new(chip->card, name, device, 705 rec->playback_ops ? 1 : 0, 706 rec->capture_ops ? 1 : 0, &pcm); 707 if (err < 0) 708 return err; 709 710 if (rec->playback_ops) 711 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 712 if (rec->capture_ops) 713 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 714 715 pcm->private_data = chip; 716 pcm->info_flags = 0; 717 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 718 if (rec->suffix) 719 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 720 else 721 strcpy(pcm->name, chip->card->shortname); 722 chip->pcm[device] = pcm; 723 724 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 725 snd_dma_pci_data(chip->pci), 726 rec->prealloc_size, 727 rec->prealloc_max_size); 728 729 return 0; 730} 731 732static struct ich_pcm_table intel_pcms[] __devinitdata = { 733 { 734 .suffix = "Modem", 735 .playback_ops = &snd_intel8x0m_playback_ops, 736 .capture_ops = &snd_intel8x0m_capture_ops, 737 .prealloc_size = 32 * 1024, 738 .prealloc_max_size = 64 * 1024, 739 }, 740}; 741 742static int __devinit snd_intel8x0_pcm(struct intel8x0m *chip) 743{ 744 int i, tblsize, device, err; 745 struct ich_pcm_table *tbl, *rec; 746 747 tbl = intel_pcms; 748 tblsize = 1; 749 device = 0; 750 for (i = 0; i < tblsize; i++) { 751 rec = tbl + i; 752 if (i > 0 && rec->ac97_idx) { 753 /* activate PCM only when associated AC'97 codec */ 754 if (! chip->ichd[rec->ac97_idx].ac97) 755 continue; 756 } 757 err = snd_intel8x0_pcm1(chip, device, rec); 758 if (err < 0) 759 return err; 760 device++; 761 } 762 763 chip->pcm_devs = device; 764 return 0; 765} 766 767 768/* 769 * Mixer part 770 */ 771 772static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 773{ 774 struct intel8x0m *chip = bus->private_data; 775 chip->ac97_bus = NULL; 776} 777 778static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 779{ 780 struct intel8x0m *chip = ac97->private_data; 781 chip->ac97 = NULL; 782} 783 784 785static int __devinit snd_intel8x0_mixer(struct intel8x0m *chip, int ac97_clock) 786{ 787 struct snd_ac97_bus *pbus; 788 struct snd_ac97_template ac97; 789 struct snd_ac97 *x97; 790 int err; 791 unsigned int glob_sta = 0; 792 static struct snd_ac97_bus_ops ops = { 793 .write = snd_intel8x0_codec_write, 794 .read = snd_intel8x0_codec_read, 795 }; 796 797 chip->in_ac97_init = 1; 798 799 memset(&ac97, 0, sizeof(ac97)); 800 ac97.private_data = chip; 801 ac97.private_free = snd_intel8x0_mixer_free_ac97; 802 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; 803 804 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 805 806 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 807 goto __err; 808 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 809 if (ac97_clock >= 8000 && ac97_clock <= 48000) 810 pbus->clock = ac97_clock; 811 chip->ac97_bus = pbus; 812 813 ac97.pci = chip->pci; 814 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 815 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 816 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num); 817 if (ac97.num == 0) 818 goto __err; 819 return err; 820 } 821 chip->ac97 = x97; 822 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 823 chip->ichd[ICHD_MDMIN].ac97 = x97; 824 chip->ichd[ICHD_MDMOUT].ac97 = x97; 825 } 826 827 chip->in_ac97_init = 0; 828 return 0; 829 830 __err: 831 /* clear the cold-reset bit for the next chance */ 832 if (chip->device_type != DEVICE_ALI) 833 iputdword(chip, ICHREG(GLOB_CNT), 834 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 835 return err; 836} 837 838 839/* 840 * 841 */ 842 843static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) 844{ 845 unsigned long end_time; 846 unsigned int cnt, status, nstatus; 847 848 /* put logic to right state */ 849 /* first clear status bits */ 850 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 851 cnt = igetdword(chip, ICHREG(GLOB_STA)); 852 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 853 854 /* ACLink on, 2 channels */ 855 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 856 cnt &= ~(ICH_ACLINK); 857 /* finish cold or do warm reset */ 858 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 859 iputdword(chip, ICHREG(GLOB_CNT), cnt); 860 end_time = (jiffies + (HZ / 4)) + 1; 861 do { 862 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 863 goto __ok; 864 schedule_timeout_uninterruptible(1); 865 } while (time_after_eq(end_time, jiffies)); 866 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", 867 igetdword(chip, ICHREG(GLOB_CNT))); 868 return -EIO; 869 870 __ok: 871 if (probing) { 872 /* wait for any codec ready status. 873 * Once it becomes ready it should remain ready 874 * as long as we do not disable the ac97 link. 875 */ 876 end_time = jiffies + HZ; 877 do { 878 status = igetdword(chip, ICHREG(GLOB_STA)) & 879 (ICH_PCR | ICH_SCR | ICH_TCR); 880 if (status) 881 break; 882 schedule_timeout_uninterruptible(1); 883 } while (time_after_eq(end_time, jiffies)); 884 if (! status) { 885 /* no codec is found */ 886 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", 887 igetdword(chip, ICHREG(GLOB_STA))); 888 return -EIO; 889 } 890 891 /* up to two codecs (modem cannot be tertiary with ICH4) */ 892 nstatus = ICH_PCR | ICH_SCR; 893 894 /* wait for other codecs ready status. */ 895 end_time = jiffies + HZ / 4; 896 while (status != nstatus && time_after_eq(end_time, jiffies)) { 897 schedule_timeout_uninterruptible(1); 898 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 899 } 900 901 } else { 902 /* resume phase */ 903 status = 0; 904 if (chip->ac97) 905 status |= get_ich_codec_bit(chip, chip->ac97->num); 906 /* wait until all the probed codecs are ready */ 907 end_time = jiffies + HZ; 908 do { 909 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 910 (ICH_PCR | ICH_SCR | ICH_TCR); 911 if (status == nstatus) 912 break; 913 schedule_timeout_uninterruptible(1); 914 } while (time_after_eq(end_time, jiffies)); 915 } 916 917 if (chip->device_type == DEVICE_SIS) { 918 /* unmute the output on SIS7012 */ 919 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 920 } 921 922 return 0; 923} 924 925static int snd_intel8x0_chip_init(struct intel8x0m *chip, int probing) 926{ 927 unsigned int i; 928 int err; 929 930 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 931 return err; 932 iagetword(chip, 0); /* clear semaphore flag */ 933 934 /* disable interrupts */ 935 for (i = 0; i < chip->bdbars_count; i++) 936 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 937 /* reset channels */ 938 for (i = 0; i < chip->bdbars_count; i++) 939 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 940 /* initialize Buffer Descriptor Lists */ 941 for (i = 0; i < chip->bdbars_count; i++) 942 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 943 return 0; 944} 945 946static int snd_intel8x0_free(struct intel8x0m *chip) 947{ 948 unsigned int i; 949 950 if (chip->irq < 0) 951 goto __hw_end; 952 /* disable interrupts */ 953 for (i = 0; i < chip->bdbars_count; i++) 954 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 955 /* reset channels */ 956 for (i = 0; i < chip->bdbars_count; i++) 957 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 958 /* --- */ 959 synchronize_irq(chip->irq); 960 __hw_end: 961 if (chip->bdbars.area) 962 snd_dma_free_pages(&chip->bdbars); 963 if (chip->addr) 964 pci_iounmap(chip->pci, chip->addr); 965 if (chip->bmaddr) 966 pci_iounmap(chip->pci, chip->bmaddr); 967 if (chip->irq >= 0) 968 free_irq(chip->irq, chip); 969 pci_release_regions(chip->pci); 970 pci_disable_device(chip->pci); 971 kfree(chip); 972 return 0; 973} 974 975#ifdef CONFIG_PM 976/* 977 * power management 978 */ 979static int intel8x0m_suspend(struct pci_dev *pci, pm_message_t state) 980{ 981 struct snd_card *card = pci_get_drvdata(pci); 982 struct intel8x0m *chip = card->private_data; 983 int i; 984 985 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 986 for (i = 0; i < chip->pcm_devs; i++) 987 snd_pcm_suspend_all(chip->pcm[i]); 988 snd_ac97_suspend(chip->ac97); 989 if (chip->irq >= 0) { 990 synchronize_irq(chip->irq); 991 free_irq(chip->irq, chip); 992 chip->irq = -1; 993 } 994 pci_disable_device(pci); 995 pci_save_state(pci); 996 pci_set_power_state(pci, pci_choose_state(pci, state)); 997 return 0; 998} 999 1000static int intel8x0m_resume(struct pci_dev *pci) 1001{ 1002 struct snd_card *card = pci_get_drvdata(pci); 1003 struct intel8x0m *chip = card->private_data; 1004 1005 pci_set_power_state(pci, PCI_D0); 1006 pci_restore_state(pci); 1007 if (pci_enable_device(pci) < 0) { 1008 printk(KERN_ERR "intel8x0m: pci_enable_device failed, " 1009 "disabling device\n"); 1010 snd_card_disconnect(card); 1011 return -EIO; 1012 } 1013 pci_set_master(pci); 1014 if (request_irq(pci->irq, snd_intel8x0_interrupt, 1015 IRQF_SHARED, card->shortname, chip)) { 1016 printk(KERN_ERR "intel8x0m: unable to grab IRQ %d, " 1017 "disabling device\n", pci->irq); 1018 snd_card_disconnect(card); 1019 return -EIO; 1020 } 1021 chip->irq = pci->irq; 1022 snd_intel8x0_chip_init(chip, 0); 1023 snd_ac97_resume(chip->ac97); 1024 1025 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1026 return 0; 1027} 1028#endif /* CONFIG_PM */ 1029 1030#ifdef CONFIG_PROC_FS 1031static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, 1032 struct snd_info_buffer *buffer) 1033{ 1034 struct intel8x0m *chip = entry->private_data; 1035 unsigned int tmp; 1036 1037 snd_iprintf(buffer, "Intel8x0m\n\n"); 1038 if (chip->device_type == DEVICE_ALI) 1039 return; 1040 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1041 snd_iprintf(buffer, "Global control : 0x%08x\n", 1042 igetdword(chip, ICHREG(GLOB_CNT))); 1043 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1044 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1045 tmp & ICH_PCR ? " primary" : "", 1046 tmp & ICH_SCR ? " secondary" : "", 1047 tmp & ICH_TCR ? " tertiary" : "", 1048 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1049} 1050 1051static void __devinit snd_intel8x0m_proc_init(struct intel8x0m * chip) 1052{ 1053 struct snd_info_entry *entry; 1054 1055 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry)) 1056 snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read); 1057} 1058#else /* !CONFIG_PROC_FS */ 1059#define snd_intel8x0m_proc_init(chip) 1060#endif /* CONFIG_PROC_FS */ 1061 1062 1063static int snd_intel8x0_dev_free(struct snd_device *device) 1064{ 1065 struct intel8x0m *chip = device->device_data; 1066 return snd_intel8x0_free(chip); 1067} 1068 1069struct ich_reg_info { 1070 unsigned int int_sta_mask; 1071 unsigned int offset; 1072}; 1073 1074static int __devinit snd_intel8x0m_create(struct snd_card *card, 1075 struct pci_dev *pci, 1076 unsigned long device_type, 1077 struct intel8x0m ** r_intel8x0) 1078{ 1079 struct intel8x0m *chip; 1080 int err; 1081 unsigned int i; 1082 unsigned int int_sta_masks; 1083 struct ichdev *ichdev; 1084 static struct snd_device_ops ops = { 1085 .dev_free = snd_intel8x0_dev_free, 1086 }; 1087 static struct ich_reg_info intel_regs[2] = { 1088 { ICH_MIINT, 0 }, 1089 { ICH_MOINT, 0x10 }, 1090 }; 1091 struct ich_reg_info *tbl; 1092 1093 *r_intel8x0 = NULL; 1094 1095 if ((err = pci_enable_device(pci)) < 0) 1096 return err; 1097 1098 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1099 if (chip == NULL) { 1100 pci_disable_device(pci); 1101 return -ENOMEM; 1102 } 1103 spin_lock_init(&chip->reg_lock); 1104 chip->device_type = device_type; 1105 chip->card = card; 1106 chip->pci = pci; 1107 chip->irq = -1; 1108 1109 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1110 kfree(chip); 1111 pci_disable_device(pci); 1112 return err; 1113 } 1114 1115 if (device_type == DEVICE_ALI) { 1116 /* ALI5455 has no ac97 region */ 1117 chip->bmaddr = pci_iomap(pci, 0, 0); 1118 goto port_inited; 1119 } 1120 1121 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 1122 chip->addr = pci_iomap(pci, 2, 0); 1123 else 1124 chip->addr = pci_iomap(pci, 0, 0); 1125 if (!chip->addr) { 1126 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 1127 snd_intel8x0_free(chip); 1128 return -EIO; 1129 } 1130 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 1131 chip->bmaddr = pci_iomap(pci, 3, 0); 1132 else 1133 chip->bmaddr = pci_iomap(pci, 1, 0); 1134 if (!chip->bmaddr) { 1135 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 1136 snd_intel8x0_free(chip); 1137 return -EIO; 1138 } 1139 1140 port_inited: 1141 if (request_irq(pci->irq, snd_intel8x0_interrupt, IRQF_SHARED, 1142 card->shortname, chip)) { 1143 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1144 snd_intel8x0_free(chip); 1145 return -EBUSY; 1146 } 1147 chip->irq = pci->irq; 1148 pci_set_master(pci); 1149 synchronize_irq(chip->irq); 1150 1151 /* initialize offsets */ 1152 chip->bdbars_count = 2; 1153 tbl = intel_regs; 1154 1155 for (i = 0; i < chip->bdbars_count; i++) { 1156 ichdev = &chip->ichd[i]; 1157 ichdev->ichd = i; 1158 ichdev->reg_offset = tbl[i].offset; 1159 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1160 if (device_type == DEVICE_SIS) { 1161 /* SiS 7013 swaps the registers */ 1162 ichdev->roff_sr = ICH_REG_OFF_PICB; 1163 ichdev->roff_picb = ICH_REG_OFF_SR; 1164 } else { 1165 ichdev->roff_sr = ICH_REG_OFF_SR; 1166 ichdev->roff_picb = ICH_REG_OFF_PICB; 1167 } 1168 if (device_type == DEVICE_ALI) 1169 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1170 } 1171 /* SIS7013 handles the pcm data in bytes, others are in words */ 1172 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1173 1174 /* allocate buffer descriptor lists */ 1175 /* the start of each lists must be aligned to 8 bytes */ 1176 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1177 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1178 &chip->bdbars) < 0) { 1179 snd_intel8x0_free(chip); 1180 return -ENOMEM; 1181 } 1182 /* tables must be aligned to 8 bytes here, but the kernel pages 1183 are much bigger, so we don't care (on i386) */ 1184 int_sta_masks = 0; 1185 for (i = 0; i < chip->bdbars_count; i++) { 1186 ichdev = &chip->ichd[i]; 1187 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1188 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1189 int_sta_masks |= ichdev->int_sta_mask; 1190 } 1191 chip->int_sta_reg = ICH_REG_GLOB_STA; 1192 chip->int_sta_mask = int_sta_masks; 1193 1194 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 1195 snd_intel8x0_free(chip); 1196 return err; 1197 } 1198 1199 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1200 snd_intel8x0_free(chip); 1201 return err; 1202 } 1203 1204 snd_card_set_dev(card, &pci->dev); 1205 1206 *r_intel8x0 = chip; 1207 return 0; 1208} 1209 1210static struct shortname_table { 1211 unsigned int id; 1212 const char *s; 1213} shortnames[] __devinitdata = { 1214 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, 1215 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, 1216 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1217 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1218 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, 1219 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, 1220 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, 1221 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, 1222 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, 1223 { 0x7446, "AMD AMD768" }, 1224 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1225 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, 1226 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1227 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1228 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1229 { 0 }, 1230}; 1231 1232static int __devinit snd_intel8x0m_probe(struct pci_dev *pci, 1233 const struct pci_device_id *pci_id) 1234{ 1235 struct snd_card *card; 1236 struct intel8x0m *chip; 1237 int err; 1238 struct shortname_table *name; 1239 1240 card = snd_card_new(index, id, THIS_MODULE, 0); 1241 if (card == NULL) 1242 return -ENOMEM; 1243 1244 strcpy(card->driver, "ICH-MODEM"); 1245 strcpy(card->shortname, "Intel ICH"); 1246 for (name = shortnames; name->id; name++) { 1247 if (pci->device == name->id) { 1248 strcpy(card->shortname, name->s); 1249 break; 1250 } 1251 } 1252 strcat(card->shortname," Modem"); 1253 1254 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1255 snd_card_free(card); 1256 return err; 1257 } 1258 card->private_data = chip; 1259 1260 if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) { 1261 snd_card_free(card); 1262 return err; 1263 } 1264 if ((err = snd_intel8x0_pcm(chip)) < 0) { 1265 snd_card_free(card); 1266 return err; 1267 } 1268 1269 snd_intel8x0m_proc_init(chip); 1270 1271 sprintf(card->longname, "%s at irq %i", 1272 card->shortname, chip->irq); 1273 1274 if ((err = snd_card_register(card)) < 0) { 1275 snd_card_free(card); 1276 return err; 1277 } 1278 pci_set_drvdata(pci, card); 1279 return 0; 1280} 1281 1282static void __devexit snd_intel8x0m_remove(struct pci_dev *pci) 1283{ 1284 snd_card_free(pci_get_drvdata(pci)); 1285 pci_set_drvdata(pci, NULL); 1286} 1287 1288static struct pci_driver driver = { 1289 .name = "Intel ICH Modem", 1290 .id_table = snd_intel8x0m_ids, 1291 .probe = snd_intel8x0m_probe, 1292 .remove = __devexit_p(snd_intel8x0m_remove), 1293#ifdef CONFIG_PM 1294 .suspend = intel8x0m_suspend, 1295 .resume = intel8x0m_resume, 1296#endif 1297}; 1298 1299 1300static int __init alsa_card_intel8x0m_init(void) 1301{ 1302 return pci_register_driver(&driver); 1303} 1304 1305static void __exit alsa_card_intel8x0m_exit(void) 1306{ 1307 pci_unregister_driver(&driver); 1308} 1309 1310module_init(alsa_card_intel8x0m_init) 1311module_exit(alsa_card_intel8x0m_exit) 1312