1/* 2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) 3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>. 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the driver code comes from Zach Brown(zab@redhat.com) 7 * Alan Cox OSS Driver 8 * Rewritted from card-es1938.c source. 9 * 10 * TODO: 11 * Perhaps Synth 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * 27 * 28 * Notes from Zach Brown about the driver code 29 * 30 * Hardware Description 31 * 32 * A working Maestro setup contains the Maestro chip wired to a 33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the 34 * Wavecache. The APUs can be though of as virtual audio routing 35 * channels. They can take data from a number of sources and perform 36 * basic encodings of the data. The wavecache is a storehouse for 37 * PCM data. Typically it deals with PCI and interracts with the 38 * APUs. The ASSP is a wacky DSP like device that ESS is loth 39 * to release docs on. Thankfully it isn't required on the Maestro 40 * until you start doing insane things like FM emulation and surround 41 * encoding. The codecs are almost always AC-97 compliant codecs, 42 * but it appears that early Maestros may have had PT101 (an ESS 43 * part?) wired to them. The only real difference in the Maestro 44 * families is external goop like docking capability, memory for 45 * the ASSP, and initialization differences. 46 * 47 * Driver Operation 48 * 49 * We only drive the APU/Wavecache as typical DACs and drive the 50 * mixers in the codecs. There are 64 APUs. We assign 6 to each 51 * /dev/dsp? device. 2 channels for output, and 4 channels for 52 * input. 53 * 54 * Each APU can do a number of things, but we only really use 55 * 3 basic functions. For playback we use them to convert PCM 56 * data fetched over PCI by the wavecahche into analog data that 57 * is handed to the codec. One APU for mono, and a pair for stereo. 58 * When in stereo, the combination of smarts in the APU and Wavecache 59 * decide which wavecache gets the left or right channel. 60 * 61 * For record we still use the old overly mono system. For each in 62 * coming channel the data comes in from the codec, through a 'input' 63 * APU, through another rate converter APU, and then into memory via 64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in 65 * software. The pass between the 2 APUs is supposedly what requires us 66 * to have a 512 byte buffer sitting around in wavecache/memory. 67 * 68 * The wavecache makes our life even more fun. First off, it can 69 * only address the first 28 bits of PCI address space, making it 70 * useless on quite a few architectures. Secondly, its insane. 71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length. 72 * But that doesn't really work. You can only use 1 region. So all our 73 * allocations have to be in 4meg of each other. Booo. Hiss. 74 * So we have a module parameter, dsps_order, that is the order of 75 * the number of dsps to provide. All their buffer space is allocated 76 * on open time. The sonicvibes OSS routines we inherited really want 77 * power of 2 buffers, so we have all those next to each other, then 78 * 512 byte regions for the recording wavecaches. This ends up 79 * wasting quite a bit of memory. The only fixes I can see would be 80 * getting a kernel allocator that could work in zones, or figuring out 81 * just how to coerce the WP into doing what we want. 82 * 83 * The indirection of the various registers means we have to spinlock 84 * nearly all register accesses. We have the main register indirection 85 * like the wave cache, maestro registers, etc. Then we have beasts 86 * like the APU interface that is indirect registers gotten at through 87 * the main maestro indirection. Ouch. We spinlock around the actual 88 * ports on a per card basis. This means spinlock activity at each IO 89 * operation, but the only IO operation clusters are in non critical 90 * paths and it makes the code far easier to follow. Interrupts are 91 * blocked while holding the locks because the int handler has to 92 * get at some of them :(. The mixer interface doesn't, however. 93 * We also have an OSS state lock that is thrown around in a few 94 * places. 95 */ 96 97#include <sound/driver.h> 98#include <asm/io.h> 99#include <linux/delay.h> 100#include <linux/interrupt.h> 101#include <linux/init.h> 102#include <linux/pci.h> 103#include <linux/dma-mapping.h> 104#include <linux/slab.h> 105#include <linux/gameport.h> 106#include <linux/moduleparam.h> 107#include <linux/mutex.h> 108 109#include <sound/core.h> 110#include <sound/pcm.h> 111#include <sound/mpu401.h> 112#include <sound/ac97_codec.h> 113#include <sound/initval.h> 114 115#define CARD_NAME "ESS Maestro1/2" 116#define DRIVER_NAME "ES1968" 117 118MODULE_DESCRIPTION("ESS Maestro"); 119MODULE_LICENSE("GPL"); 120MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e}," 121 "{ESS,Maestro 2}," 122 "{ESS,Maestro 1}," 123 "{TerraTec,DMX}}"); 124 125#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 126#define SUPPORT_JOYSTICK 1 127#endif 128 129static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ 130static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 131static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 132static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; 133static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; 134static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; 135static int clock[SNDRV_CARDS]; 136static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 137static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 138#ifdef SUPPORT_JOYSTICK 139static int joystick[SNDRV_CARDS]; 140#endif 141 142module_param_array(index, int, NULL, 0444); 143MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 144module_param_array(id, charp, NULL, 0444); 145MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 146module_param_array(enable, bool, NULL, 0444); 147MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 148module_param_array(total_bufsize, int, NULL, 0444); 149MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); 150module_param_array(pcm_substreams_p, int, NULL, 0444); 151MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); 152module_param_array(pcm_substreams_c, int, NULL, 0444); 153MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); 154module_param_array(clock, int, NULL, 0444); 155MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); 156module_param_array(use_pm, int, NULL, 0444); 157MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); 158module_param_array(enable_mpu, int, NULL, 0444); 159MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); 160#ifdef SUPPORT_JOYSTICK 161module_param_array(joystick, bool, NULL, 0444); 162MODULE_PARM_DESC(joystick, "Enable joystick."); 163#endif 164 165 166#define NR_APUS 64 167#define NR_APU_REGS 16 168 169/* NEC Versas ? */ 170#define NEC_VERSA_SUBID1 0x80581033 171#define NEC_VERSA_SUBID2 0x803c1033 172 173/* Mode Flags */ 174#define ESS_FMT_STEREO 0x01 175#define ESS_FMT_16BIT 0x02 176 177#define DAC_RUNNING 1 178#define ADC_RUNNING 2 179 180/* Values for the ESM_LEGACY_AUDIO_CONTROL */ 181 182#define ESS_DISABLE_AUDIO 0x8000 183#define ESS_ENABLE_SERIAL_IRQ 0x4000 184#define IO_ADRESS_ALIAS 0x0020 185#define MPU401_IRQ_ENABLE 0x0010 186#define MPU401_IO_ENABLE 0x0008 187#define GAME_IO_ENABLE 0x0004 188#define FM_IO_ENABLE 0x0002 189#define SB_IO_ENABLE 0x0001 190 191/* Values for the ESM_CONFIG_A */ 192 193#define PIC_SNOOP1 0x4000 194#define PIC_SNOOP2 0x2000 195#define SAFEGUARD 0x0800 196#define DMA_CLEAR 0x0700 197#define DMA_DDMA 0x0000 198#define DMA_TDMA 0x0100 199#define DMA_PCPCI 0x0200 200#define POST_WRITE 0x0080 201#define PCI_TIMING 0x0040 202#define SWAP_LR 0x0020 203#define SUBTR_DECODE 0x0002 204 205/* Values for the ESM_CONFIG_B */ 206 207#define SPDIF_CONFB 0x0100 208#define HWV_CONFB 0x0080 209#define DEBOUNCE 0x0040 210#define GPIO_CONFB 0x0020 211#define CHI_CONFB 0x0010 212#define IDMA_CONFB 0x0008 /*undoc */ 213#define MIDI_FIX 0x0004 /*undoc */ 214#define IRQ_TO_ISA 0x0001 /*undoc */ 215 216/* Values for Ring Bus Control B */ 217#define RINGB_2CODEC_ID_MASK 0x0003 218#define RINGB_DIS_VALIDATION 0x0008 219#define RINGB_EN_SPDIF 0x0010 220#define RINGB_EN_2CODEC 0x0020 221#define RINGB_SING_BIT_DUAL 0x0040 222 223/* ****Port Adresses**** */ 224 225/* Write & Read */ 226#define ESM_INDEX 0x02 227#define ESM_DATA 0x00 228 229/* AC97 + RingBus */ 230#define ESM_AC97_INDEX 0x30 231#define ESM_AC97_DATA 0x32 232#define ESM_RING_BUS_DEST 0x34 233#define ESM_RING_BUS_CONTR_A 0x36 234#define ESM_RING_BUS_CONTR_B 0x38 235#define ESM_RING_BUS_SDO 0x3A 236 237/* WaveCache*/ 238#define WC_INDEX 0x10 239#define WC_DATA 0x12 240#define WC_CONTROL 0x14 241 242/* ASSP*/ 243#define ASSP_INDEX 0x80 244#define ASSP_MEMORY 0x82 245#define ASSP_DATA 0x84 246#define ASSP_CONTROL_A 0xA2 247#define ASSP_CONTROL_B 0xA4 248#define ASSP_CONTROL_C 0xA6 249#define ASSP_HOSTW_INDEX 0xA8 250#define ASSP_HOSTW_DATA 0xAA 251#define ASSP_HOSTW_IRQ 0xAC 252/* Midi */ 253#define ESM_MPU401_PORT 0x98 254/* Others */ 255#define ESM_PORT_HOST_IRQ 0x18 256 257#define IDR0_DATA_PORT 0x00 258#define IDR1_CRAM_POINTER 0x01 259#define IDR2_CRAM_DATA 0x02 260#define IDR3_WAVE_DATA 0x03 261#define IDR4_WAVE_PTR_LOW 0x04 262#define IDR5_WAVE_PTR_HI 0x05 263#define IDR6_TIMER_CTRL 0x06 264#define IDR7_WAVE_ROMRAM 0x07 265 266#define WRITEABLE_MAP 0xEFFFFF 267#define READABLE_MAP 0x64003F 268 269/* PCI Register */ 270 271#define ESM_LEGACY_AUDIO_CONTROL 0x40 272#define ESM_ACPI_COMMAND 0x54 273#define ESM_CONFIG_A 0x50 274#define ESM_CONFIG_B 0x52 275#define ESM_DDMA 0x60 276 277/* Bob Bits */ 278#define ESM_BOB_ENABLE 0x0001 279#define ESM_BOB_START 0x0001 280 281/* Host IRQ Control Bits */ 282#define ESM_RESET_MAESTRO 0x8000 283#define ESM_RESET_DIRECTSOUND 0x4000 284#define ESM_HIRQ_ClkRun 0x0100 285#define ESM_HIRQ_HW_VOLUME 0x0040 286#define ESM_HIRQ_HARPO 0x0030 /* What's that? */ 287#define ESM_HIRQ_ASSP 0x0010 288#define ESM_HIRQ_DSIE 0x0004 289#define ESM_HIRQ_MPU401 0x0002 290#define ESM_HIRQ_SB 0x0001 291 292/* Host IRQ Status Bits */ 293#define ESM_MPU401_IRQ 0x02 294#define ESM_SB_IRQ 0x01 295#define ESM_SOUND_IRQ 0x04 296#define ESM_ASSP_IRQ 0x10 297#define ESM_HWVOL_IRQ 0x40 298 299#define ESS_SYSCLK 50000000 300#define ESM_BOB_FREQ 200 301#define ESM_BOB_FREQ_MAX 800 302 303#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ 304#define ESM_FREQ_ESM2 (50000000L / 1024L) 305 306/* APU Modes: reg 0x00, bit 4-7 */ 307#define ESM_APU_MODE_SHIFT 4 308#define ESM_APU_MODE_MASK (0xf << 4) 309#define ESM_APU_OFF 0x00 310#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ 311#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ 312#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ 313#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ 314#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ 315#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ 316#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ 317#define ESM_APU_CORRELATOR 0x08 /* Correlator */ 318#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ 319#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ 320#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ 321#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ 322#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ 323#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ 324#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ 325 326/* reg 0x00 */ 327#define ESM_APU_FILTER_Q_SHIFT 0 328#define ESM_APU_FILTER_Q_MASK (3 << 0) 329/* APU Filtey Q Control */ 330#define ESM_APU_FILTER_LESSQ 0x00 331#define ESM_APU_FILTER_MOREQ 0x03 332 333#define ESM_APU_FILTER_TYPE_SHIFT 2 334#define ESM_APU_FILTER_TYPE_MASK (3 << 2) 335#define ESM_APU_ENV_TYPE_SHIFT 8 336#define ESM_APU_ENV_TYPE_MASK (3 << 8) 337#define ESM_APU_ENV_STATE_SHIFT 10 338#define ESM_APU_ENV_STATE_MASK (3 << 10) 339#define ESM_APU_END_CURVE (1 << 12) 340#define ESM_APU_INT_ON_LOOP (1 << 13) 341#define ESM_APU_DMA_ENABLE (1 << 14) 342 343/* reg 0x02 */ 344#define ESM_APU_SUBMIX_GROUP_SHIRT 0 345#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) 346#define ESM_APU_SUBMIX_MODE (1 << 3) 347#define ESM_APU_6dB (1 << 4) 348#define ESM_APU_DUAL_EFFECT (1 << 5) 349#define ESM_APU_EFFECT_CHANNELS_SHIFT 6 350#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) 351 352/* reg 0x03 */ 353#define ESM_APU_STEP_SIZE_MASK 0x0fff 354 355/* reg 0x04 */ 356#define ESM_APU_PHASE_SHIFT 0 357#define ESM_APU_PHASE_MASK (0xff << 0) 358#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ 359#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) 360 361/* reg 0x05 - wave start offset */ 362/* reg 0x06 - wave end offset */ 363/* reg 0x07 - wave loop length */ 364 365/* reg 0x08 */ 366#define ESM_APU_EFFECT_GAIN_SHIFT 0 367#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) 368#define ESM_APU_TREMOLO_DEPTH_SHIFT 8 369#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) 370#define ESM_APU_TREMOLO_RATE_SHIFT 12 371#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) 372 373/* reg 0x09 */ 374/* bit 0-7 amplitude dest? */ 375#define ESM_APU_AMPLITUDE_NOW_SHIFT 8 376#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) 377 378/* reg 0x0a */ 379#define ESM_APU_POLAR_PAN_SHIFT 0 380#define ESM_APU_POLAR_PAN_MASK (0x3f << 0) 381/* Polar Pan Control */ 382#define ESM_APU_PAN_CENTER_CIRCLE 0x00 383#define ESM_APU_PAN_MIDDLE_RADIUS 0x01 384#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 385 386#define ESM_APU_FILTER_TUNING_SHIFT 8 387#define ESM_APU_FILTER_TUNING_MASK (0xff << 8) 388 389/* reg 0x0b */ 390#define ESM_APU_DATA_SRC_A_SHIFT 0 391#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) 392#define ESM_APU_INV_POL_A (1 << 7) 393#define ESM_APU_DATA_SRC_B_SHIFT 8 394#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) 395#define ESM_APU_INV_POL_B (1 << 15) 396 397#define ESM_APU_VIBRATO_RATE_SHIFT 0 398#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) 399#define ESM_APU_VIBRATO_DEPTH_SHIFT 4 400#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) 401#define ESM_APU_VIBRATO_PHASE_SHIFT 8 402#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) 403 404/* reg 0x0c */ 405#define ESM_APU_RADIUS_SELECT (1 << 6) 406 407/* APU Filter Control */ 408#define ESM_APU_FILTER_2POLE_LOPASS 0x00 409#define ESM_APU_FILTER_2POLE_BANDPASS 0x01 410#define ESM_APU_FILTER_2POLE_HIPASS 0x02 411#define ESM_APU_FILTER_1POLE_LOPASS 0x03 412#define ESM_APU_FILTER_1POLE_HIPASS 0x04 413#define ESM_APU_FILTER_OFF 0x05 414 415/* APU ATFP Type */ 416#define ESM_APU_ATFP_AMPLITUDE 0x00 417#define ESM_APU_ATFP_TREMELO 0x01 418#define ESM_APU_ATFP_FILTER 0x02 419#define ESM_APU_ATFP_PAN 0x03 420 421/* APU ATFP Flags */ 422#define ESM_APU_ATFP_FLG_OFF 0x00 423#define ESM_APU_ATFP_FLG_WAIT 0x01 424#define ESM_APU_ATFP_FLG_DONE 0x02 425#define ESM_APU_ATFP_FLG_INPROCESS 0x03 426 427 428/* capture mixing buffer size */ 429#define ESM_MEM_ALIGN 0x1000 430#define ESM_MIXBUF_SIZE 0x400 431 432#define ESM_MODE_PLAY 0 433#define ESM_MODE_CAPTURE 1 434 435 436/* APU use in the driver */ 437enum snd_enum_apu_type { 438 ESM_APU_PCM_PLAY, 439 ESM_APU_PCM_CAPTURE, 440 ESM_APU_PCM_RATECONV, 441 ESM_APU_FREE 442}; 443 444/* chip type */ 445enum { 446 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E 447}; 448 449/* DMA Hack! */ 450struct esm_memory { 451 struct snd_dma_buffer buf; 452 int empty; /* status */ 453 struct list_head list; 454}; 455 456/* Playback Channel */ 457struct esschan { 458 int running; 459 460 u8 apu[4]; 461 u8 apu_mode[4]; 462 463 /* playback/capture pcm buffer */ 464 struct esm_memory *memory; 465 /* capture mixer buffer */ 466 struct esm_memory *mixbuf; 467 468 unsigned int hwptr; /* current hw pointer in bytes */ 469 unsigned int count; /* sample counter in bytes */ 470 unsigned int dma_size; /* total buffer size in bytes */ 471 unsigned int frag_size; /* period size in bytes */ 472 unsigned int wav_shift; 473 u16 base[4]; /* offset for ptr */ 474 475 /* stereo/16bit flag */ 476 unsigned char fmt; 477 int mode; /* playback / capture */ 478 479 int bob_freq; /* required timer frequency */ 480 481 struct snd_pcm_substream *substream; 482 483 /* linked list */ 484 struct list_head list; 485 486#ifdef CONFIG_PM 487 u16 wc_map[4]; 488#endif 489}; 490 491struct es1968 { 492 /* Module Config */ 493 int total_bufsize; /* in bytes */ 494 495 int playback_streams, capture_streams; 496 497 unsigned int clock; /* clock */ 498 /* for clock measurement */ 499 unsigned int in_measurement: 1; 500 unsigned int measure_apu; 501 unsigned int measure_lastpos; 502 unsigned int measure_count; 503 504 /* buffer */ 505 struct snd_dma_buffer dma; 506 507 /* Resources... */ 508 int irq; 509 unsigned long io_port; 510 int type; 511 struct pci_dev *pci; 512 struct snd_card *card; 513 struct snd_pcm *pcm; 514 int do_pm; /* power-management enabled */ 515 516 /* DMA memory block */ 517 struct list_head buf_list; 518 519 /* ALSA Stuff */ 520 struct snd_ac97 *ac97; 521 struct snd_kcontrol *master_switch; /* for h/w volume control */ 522 struct snd_kcontrol *master_volume; 523 524 struct snd_rawmidi *rmidi; 525 526 spinlock_t reg_lock; 527 spinlock_t ac97_lock; 528 struct tasklet_struct hwvol_tq; 529 unsigned int in_suspend; 530 531 /* Maestro Stuff */ 532 u16 maestro_map[32]; 533 int bobclient; /* active timer instancs */ 534 int bob_freq; /* timer frequency */ 535 struct mutex memory_mutex; /* memory lock */ 536 537 /* APU states */ 538 unsigned char apu[NR_APUS]; 539 540 /* active substreams */ 541 struct list_head substream_list; 542 spinlock_t substream_lock; 543 544#ifdef CONFIG_PM 545 u16 apu_map[NR_APUS][NR_APU_REGS]; 546#endif 547 548#ifdef SUPPORT_JOYSTICK 549 struct gameport *gameport; 550#endif 551}; 552 553static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id); 554 555static struct pci_device_id snd_es1968_ids[] = { 556 /* Maestro 1 */ 557 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, 558 /* Maestro 2 */ 559 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, 560 /* Maestro 2E */ 561 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, 562 { 0, } 563}; 564 565MODULE_DEVICE_TABLE(pci, snd_es1968_ids); 566 567/* ********************* 568 * Low Level Funcs! * 569 *********************/ 570 571/* no spinlock */ 572static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) 573{ 574 outw(reg, chip->io_port + ESM_INDEX); 575 outw(data, chip->io_port + ESM_DATA); 576 chip->maestro_map[reg] = data; 577} 578 579static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) 580{ 581 unsigned long flags; 582 spin_lock_irqsave(&chip->reg_lock, flags); 583 __maestro_write(chip, reg, data); 584 spin_unlock_irqrestore(&chip->reg_lock, flags); 585} 586 587/* no spinlock */ 588static u16 __maestro_read(struct es1968 *chip, u16 reg) 589{ 590 if (READABLE_MAP & (1 << reg)) { 591 outw(reg, chip->io_port + ESM_INDEX); 592 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); 593 } 594 return chip->maestro_map[reg]; 595} 596 597static inline u16 maestro_read(struct es1968 *chip, u16 reg) 598{ 599 unsigned long flags; 600 u16 result; 601 spin_lock_irqsave(&chip->reg_lock, flags); 602 result = __maestro_read(chip, reg); 603 spin_unlock_irqrestore(&chip->reg_lock, flags); 604 return result; 605} 606 607/* Wait for the codec bus to be free */ 608static int snd_es1968_ac97_wait(struct es1968 *chip) 609{ 610 int timeout = 100000; 611 612 while (timeout-- > 0) { 613 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 614 return 0; 615 cond_resched(); 616 } 617 snd_printd("es1968: ac97 timeout\n"); 618 return 1; /* timeout */ 619} 620 621static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 622{ 623 struct es1968 *chip = ac97->private_data; 624 unsigned long flags; 625 626 snd_es1968_ac97_wait(chip); 627 628 /* Write the bus */ 629 spin_lock_irqsave(&chip->ac97_lock, flags); 630 outw(val, chip->io_port + ESM_AC97_DATA); 631 /*msleep(1);*/ 632 outb(reg, chip->io_port + ESM_AC97_INDEX); 633 /*msleep(1);*/ 634 spin_unlock_irqrestore(&chip->ac97_lock, flags); 635} 636 637static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 638{ 639 u16 data = 0; 640 struct es1968 *chip = ac97->private_data; 641 unsigned long flags; 642 643 snd_es1968_ac97_wait(chip); 644 645 spin_lock_irqsave(&chip->ac97_lock, flags); 646 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); 647 /*msleep(1);*/ 648 649 if (! snd_es1968_ac97_wait(chip)) { 650 data = inw(chip->io_port + ESM_AC97_DATA); 651 /*msleep(1);*/ 652 } 653 spin_unlock_irqrestore(&chip->ac97_lock, flags); 654 655 return data; 656} 657 658/* no spinlock */ 659static void apu_index_set(struct es1968 *chip, u16 index) 660{ 661 int i; 662 __maestro_write(chip, IDR1_CRAM_POINTER, index); 663 for (i = 0; i < 1000; i++) 664 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) 665 return; 666 snd_printd("es1968: APU register select failed. (Timeout)\n"); 667} 668 669/* no spinlock */ 670static void apu_data_set(struct es1968 *chip, u16 data) 671{ 672 int i; 673 for (i = 0; i < 1000; i++) { 674 if (__maestro_read(chip, IDR0_DATA_PORT) == data) 675 return; 676 __maestro_write(chip, IDR0_DATA_PORT, data); 677 } 678 snd_printd("es1968: APU register set probably failed (Timeout)!\n"); 679} 680 681/* no spinlock */ 682static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 683{ 684 snd_assert(channel < NR_APUS, return); 685#ifdef CONFIG_PM 686 chip->apu_map[channel][reg] = data; 687#endif 688 reg |= (channel << 4); 689 apu_index_set(chip, reg); 690 apu_data_set(chip, data); 691} 692 693static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 694{ 695 unsigned long flags; 696 spin_lock_irqsave(&chip->reg_lock, flags); 697 __apu_set_register(chip, channel, reg, data); 698 spin_unlock_irqrestore(&chip->reg_lock, flags); 699} 700 701static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 702{ 703 snd_assert(channel < NR_APUS, return 0); 704 reg |= (channel << 4); 705 apu_index_set(chip, reg); 706 return __maestro_read(chip, IDR0_DATA_PORT); 707} 708 709static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 710{ 711 unsigned long flags; 712 u16 v; 713 spin_lock_irqsave(&chip->reg_lock, flags); 714 v = __apu_get_register(chip, channel, reg); 715 spin_unlock_irqrestore(&chip->reg_lock, flags); 716 return v; 717} 718 719 720static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) 721{ 722 unsigned long flags; 723 724 spin_lock_irqsave(&chip->reg_lock, flags); 725 outw(reg, chip->io_port + WC_INDEX); 726 outw(value, chip->io_port + WC_DATA); 727 spin_unlock_irqrestore(&chip->reg_lock, flags); 728} 729 730static u16 wave_get_register(struct es1968 *chip, u16 reg) 731{ 732 unsigned long flags; 733 u16 value; 734 735 spin_lock_irqsave(&chip->reg_lock, flags); 736 outw(reg, chip->io_port + WC_INDEX); 737 value = inw(chip->io_port + WC_DATA); 738 spin_unlock_irqrestore(&chip->reg_lock, flags); 739 740 return value; 741} 742 743/* ******************* 744 * Bob the Timer! * 745 *******************/ 746 747static void snd_es1968_bob_stop(struct es1968 *chip) 748{ 749 u16 reg; 750 751 reg = __maestro_read(chip, 0x11); 752 reg &= ~ESM_BOB_ENABLE; 753 __maestro_write(chip, 0x11, reg); 754 reg = __maestro_read(chip, 0x17); 755 reg &= ~ESM_BOB_START; 756 __maestro_write(chip, 0x17, reg); 757} 758 759static void snd_es1968_bob_start(struct es1968 *chip) 760{ 761 int prescale; 762 int divide; 763 764 /* compute ideal interrupt frequency for buffer size & play rate */ 765 /* first, find best prescaler value to match freq */ 766 for (prescale = 5; prescale < 12; prescale++) 767 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) 768 break; 769 770 /* next, back off prescaler whilst getting divider into optimum range */ 771 divide = 1; 772 while ((prescale > 5) && (divide < 32)) { 773 prescale--; 774 divide <<= 1; 775 } 776 divide >>= 1; 777 778 /* now fine-tune the divider for best match */ 779 for (; divide < 31; divide++) 780 if (chip->bob_freq > 781 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; 782 783 /* divide = 0 is illegal, but don't let prescale = 4! */ 784 if (divide == 0) { 785 divide++; 786 if (prescale > 5) 787 prescale--; 788 } else if (divide > 1) 789 divide--; 790 791 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ 792 793 /* Now set IDR 11/17 */ 794 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); 795 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); 796} 797 798/* call with substream spinlock */ 799static void snd_es1968_bob_inc(struct es1968 *chip, int freq) 800{ 801 chip->bobclient++; 802 if (chip->bobclient == 1) { 803 chip->bob_freq = freq; 804 snd_es1968_bob_start(chip); 805 } else if (chip->bob_freq < freq) { 806 snd_es1968_bob_stop(chip); 807 chip->bob_freq = freq; 808 snd_es1968_bob_start(chip); 809 } 810} 811 812/* call with substream spinlock */ 813static void snd_es1968_bob_dec(struct es1968 *chip) 814{ 815 chip->bobclient--; 816 if (chip->bobclient <= 0) 817 snd_es1968_bob_stop(chip); 818 else if (chip->bob_freq > ESM_BOB_FREQ) { 819 /* check reduction of timer frequency */ 820 struct list_head *p; 821 int max_freq = ESM_BOB_FREQ; 822 list_for_each(p, &chip->substream_list) { 823 struct esschan *es = list_entry(p, struct esschan, list); 824 if (max_freq < es->bob_freq) 825 max_freq = es->bob_freq; 826 } 827 if (max_freq != chip->bob_freq) { 828 snd_es1968_bob_stop(chip); 829 chip->bob_freq = max_freq; 830 snd_es1968_bob_start(chip); 831 } 832 } 833} 834 835static int 836snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es, 837 struct snd_pcm_runtime *runtime) 838{ 839 /* we acquire 4 interrupts per period for precise control.. */ 840 int freq = runtime->rate * 4; 841 if (es->fmt & ESS_FMT_STEREO) 842 freq <<= 1; 843 if (es->fmt & ESS_FMT_16BIT) 844 freq <<= 1; 845 freq /= es->frag_size; 846 if (freq < ESM_BOB_FREQ) 847 freq = ESM_BOB_FREQ; 848 else if (freq > ESM_BOB_FREQ_MAX) 849 freq = ESM_BOB_FREQ_MAX; 850 return freq; 851} 852 853 854/************* 855 * PCM Part * 856 *************/ 857 858static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq) 859{ 860 u32 rate = (freq << 16) / chip->clock; 861 return rate; 862} 863 864/* get current pointer */ 865static inline unsigned int 866snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es) 867{ 868 unsigned int offset; 869 870 offset = apu_get_register(chip, es->apu[0], 5); 871 872 offset -= es->base[0]; 873 874 return (offset & 0xFFFE); /* hardware is in words */ 875} 876 877static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq) 878{ 879 apu_set_register(chip, apu, 2, 880 (apu_get_register(chip, apu, 2) & 0x00FF) | 881 ((freq & 0xff) << 8) | 0x10); 882 apu_set_register(chip, apu, 3, freq >> 8); 883} 884 885/* spin lock held */ 886static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode) 887{ 888 /* set the APU mode */ 889 __apu_set_register(esm, apu, 0, 890 (__apu_get_register(esm, apu, 0) & 0xff0f) | 891 (mode << 4)); 892} 893 894static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es) 895{ 896 spin_lock(&chip->reg_lock); 897 __apu_set_register(chip, es->apu[0], 5, es->base[0]); 898 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); 899 if (es->mode == ESM_MODE_CAPTURE) { 900 __apu_set_register(chip, es->apu[2], 5, es->base[2]); 901 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); 902 } 903 if (es->fmt & ESS_FMT_STEREO) { 904 __apu_set_register(chip, es->apu[1], 5, es->base[1]); 905 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); 906 if (es->mode == ESM_MODE_CAPTURE) { 907 __apu_set_register(chip, es->apu[3], 5, es->base[3]); 908 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); 909 } 910 } 911 spin_unlock(&chip->reg_lock); 912} 913 914static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es) 915{ 916 spin_lock(&chip->reg_lock); 917 snd_es1968_trigger_apu(chip, es->apu[0], 0); 918 snd_es1968_trigger_apu(chip, es->apu[1], 0); 919 if (es->mode == ESM_MODE_CAPTURE) { 920 snd_es1968_trigger_apu(chip, es->apu[2], 0); 921 snd_es1968_trigger_apu(chip, es->apu[3], 0); 922 } 923 spin_unlock(&chip->reg_lock); 924} 925 926/* set the wavecache control reg */ 927static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es, 928 int channel, u32 addr, int capture) 929{ 930 u32 tmpval = (addr - 0x10) & 0xFFF8; 931 932 if (! capture) { 933 if (!(es->fmt & ESS_FMT_16BIT)) 934 tmpval |= 4; /* 8bit */ 935 if (es->fmt & ESS_FMT_STEREO) 936 tmpval |= 2; /* stereo */ 937 } 938 939 /* set the wavecache control reg */ 940 wave_set_register(chip, es->apu[channel] << 3, tmpval); 941 942#ifdef CONFIG_PM 943 es->wc_map[channel] = tmpval; 944#endif 945} 946 947 948static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es, 949 struct snd_pcm_runtime *runtime) 950{ 951 u32 pa; 952 int high_apu = 0; 953 int channel, apu; 954 int i, size; 955 unsigned long flags; 956 u32 freq; 957 958 size = es->dma_size >> es->wav_shift; 959 960 if (es->fmt & ESS_FMT_STEREO) 961 high_apu++; 962 963 for (channel = 0; channel <= high_apu; channel++) { 964 apu = es->apu[channel]; 965 966 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); 967 968 /* Offset to PCMBAR */ 969 pa = es->memory->buf.addr; 970 pa -= chip->dma.addr; 971 pa >>= 1; /* words */ 972 973 pa |= 0x00400000; /* System RAM (Bit 22) */ 974 975 if (es->fmt & ESS_FMT_STEREO) { 976 /* Enable stereo */ 977 if (channel) 978 pa |= 0x00800000; /* (Bit 23) */ 979 if (es->fmt & ESS_FMT_16BIT) 980 pa >>= 1; 981 } 982 983 /* base offset of dma calcs when reading the pointer 984 on this left one */ 985 es->base[channel] = pa & 0xFFFF; 986 987 for (i = 0; i < 16; i++) 988 apu_set_register(chip, apu, i, 0x0000); 989 990 /* Load the buffer into the wave engine */ 991 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 992 apu_set_register(chip, apu, 5, pa & 0xFFFF); 993 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); 994 /* setting loop == sample len */ 995 apu_set_register(chip, apu, 7, size); 996 997 /* clear effects/env.. */ 998 apu_set_register(chip, apu, 8, 0x0000); 999 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ 1000 apu_set_register(chip, apu, 9, 0xD000); 1001 1002 /* clear routing stuff */ 1003 apu_set_register(chip, apu, 11, 0x0000); 1004 /* dma on, no envelopes, filter to all 1s) */ 1005 apu_set_register(chip, apu, 0, 0x400F); 1006 1007 if (es->fmt & ESS_FMT_16BIT) 1008 es->apu_mode[channel] = ESM_APU_16BITLINEAR; 1009 else 1010 es->apu_mode[channel] = ESM_APU_8BITLINEAR; 1011 1012 if (es->fmt & ESS_FMT_STEREO) { 1013 /* set panning: left or right */ 1014 /* Check: different panning. On my Canyon 3D Chipset the 1015 Channels are swapped. I don't know, about the output 1016 to the SPDif Link. Perhaps you have to change this 1017 and not the APU Regs 4-5. */ 1018 apu_set_register(chip, apu, 10, 1019 0x8F00 | (channel ? 0 : 0x10)); 1020 es->apu_mode[channel] += 1; /* stereo */ 1021 } else 1022 apu_set_register(chip, apu, 10, 0x8F08); 1023 } 1024 1025 spin_lock_irqsave(&chip->reg_lock, flags); 1026 /* clear WP interrupts */ 1027 outw(1, chip->io_port + 0x04); 1028 /* enable WP ints */ 1029 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1030 spin_unlock_irqrestore(&chip->reg_lock, flags); 1031 1032 freq = runtime->rate; 1033 /* set frequency */ 1034 if (freq > 48000) 1035 freq = 48000; 1036 if (freq < 4000) 1037 freq = 4000; 1038 1039 /* hmmm.. */ 1040 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) 1041 freq >>= 1; 1042 1043 freq = snd_es1968_compute_rate(chip, freq); 1044 1045 /* Load the frequency, turn on 6dB */ 1046 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1047 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1048} 1049 1050 1051static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel, 1052 unsigned int pa, unsigned int bsize, 1053 int mode, int route) 1054{ 1055 int i, apu = es->apu[channel]; 1056 1057 es->apu_mode[channel] = mode; 1058 1059 /* set the wavecache control reg */ 1060 snd_es1968_program_wavecache(chip, es, channel, pa, 1); 1061 1062 /* Offset to PCMBAR */ 1063 pa -= chip->dma.addr; 1064 pa >>= 1; /* words */ 1065 1066 /* base offset of dma calcs when reading the pointer 1067 on this left one */ 1068 es->base[channel] = pa & 0xFFFF; 1069 pa |= 0x00400000; /* bit 22 -> System RAM */ 1070 1071 /* Begin loading the APU */ 1072 for (i = 0; i < 16; i++) 1073 apu_set_register(chip, apu, i, 0x0000); 1074 1075 /* need to enable subgroups.. and we should probably 1076 have different groups for different /dev/dsps.. */ 1077 apu_set_register(chip, apu, 2, 0x8); 1078 1079 /* Load the buffer into the wave engine */ 1080 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1081 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1082 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); 1083 apu_set_register(chip, apu, 7, bsize); 1084 /* clear effects/env.. */ 1085 apu_set_register(chip, apu, 8, 0x00F0); 1086 /* amplitude now? sure. why not. */ 1087 apu_set_register(chip, apu, 9, 0x0000); 1088 /* set filter tune, radius, polar pan */ 1089 apu_set_register(chip, apu, 10, 0x8F08); 1090 /* route input */ 1091 apu_set_register(chip, apu, 11, route); 1092 /* dma on, no envelopes, filter to all 1s) */ 1093 apu_set_register(chip, apu, 0, 0x400F); 1094} 1095 1096static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es, 1097 struct snd_pcm_runtime *runtime) 1098{ 1099 int size; 1100 u32 freq; 1101 unsigned long flags; 1102 1103 size = es->dma_size >> es->wav_shift; 1104 1105 /* APU assignments: 1106 0 = mono/left SRC 1107 1 = right SRC 1108 2 = mono/left Input Mixer 1109 3 = right Input Mixer 1110 */ 1111 /* data seems to flow from the codec, through an apu into 1112 the 'mixbuf' bit of page, then through the SRC apu 1113 and out to the real 'buffer'. ok. sure. */ 1114 1115 /* input mixer (left/mono) */ 1116 /* parallel in crap, see maestro reg 0xC [8-11] */ 1117 init_capture_apu(chip, es, 2, 1118 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ 1119 ESM_APU_INPUTMIXER, 0x14); 1120 /* SRC (left/mono); get input from inputing apu */ 1121 init_capture_apu(chip, es, 0, es->memory->buf.addr, size, 1122 ESM_APU_SRCONVERTOR, es->apu[2]); 1123 if (es->fmt & ESS_FMT_STEREO) { 1124 /* input mixer (right) */ 1125 init_capture_apu(chip, es, 3, 1126 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, 1127 ESM_MIXBUF_SIZE/4, /* in words */ 1128 ESM_APU_INPUTMIXER, 0x15); 1129 /* SRC (right) */ 1130 init_capture_apu(chip, es, 1, 1131 es->memory->buf.addr + size*2, size, 1132 ESM_APU_SRCONVERTOR, es->apu[3]); 1133 } 1134 1135 freq = runtime->rate; 1136 /* Sample Rate conversion APUs don't like 0x10000 for their rate */ 1137 if (freq > 47999) 1138 freq = 47999; 1139 if (freq < 4000) 1140 freq = 4000; 1141 1142 freq = snd_es1968_compute_rate(chip, freq); 1143 1144 /* Load the frequency, turn on 6dB */ 1145 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1146 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1147 1148 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ 1149 freq = 0x10000; 1150 snd_es1968_apu_set_freq(chip, es->apu[2], freq); 1151 snd_es1968_apu_set_freq(chip, es->apu[3], freq); 1152 1153 spin_lock_irqsave(&chip->reg_lock, flags); 1154 /* clear WP interrupts */ 1155 outw(1, chip->io_port + 0x04); 1156 /* enable WP ints */ 1157 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1158 spin_unlock_irqrestore(&chip->reg_lock, flags); 1159} 1160 1161/******************* 1162 * ALSA Interface * 1163 *******************/ 1164 1165static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream) 1166{ 1167 struct es1968 *chip = snd_pcm_substream_chip(substream); 1168 struct snd_pcm_runtime *runtime = substream->runtime; 1169 struct esschan *es = runtime->private_data; 1170 1171 es->dma_size = snd_pcm_lib_buffer_bytes(substream); 1172 es->frag_size = snd_pcm_lib_period_bytes(substream); 1173 1174 es->wav_shift = 1; /* maestro handles always 16bit */ 1175 es->fmt = 0; 1176 if (snd_pcm_format_width(runtime->format) == 16) 1177 es->fmt |= ESS_FMT_16BIT; 1178 if (runtime->channels > 1) { 1179 es->fmt |= ESS_FMT_STEREO; 1180 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ 1181 es->wav_shift++; 1182 } 1183 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); 1184 1185 switch (es->mode) { 1186 case ESM_MODE_PLAY: 1187 snd_es1968_playback_setup(chip, es, runtime); 1188 break; 1189 case ESM_MODE_CAPTURE: 1190 snd_es1968_capture_setup(chip, es, runtime); 1191 break; 1192 } 1193 1194 return 0; 1195} 1196 1197static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1198{ 1199 struct es1968 *chip = snd_pcm_substream_chip(substream); 1200 struct esschan *es = substream->runtime->private_data; 1201 1202 spin_lock(&chip->substream_lock); 1203 switch (cmd) { 1204 case SNDRV_PCM_TRIGGER_START: 1205 case SNDRV_PCM_TRIGGER_RESUME: 1206 if (es->running) 1207 break; 1208 snd_es1968_bob_inc(chip, es->bob_freq); 1209 es->count = 0; 1210 es->hwptr = 0; 1211 snd_es1968_pcm_start(chip, es); 1212 es->running = 1; 1213 break; 1214 case SNDRV_PCM_TRIGGER_STOP: 1215 case SNDRV_PCM_TRIGGER_SUSPEND: 1216 if (! es->running) 1217 break; 1218 snd_es1968_pcm_stop(chip, es); 1219 es->running = 0; 1220 snd_es1968_bob_dec(chip); 1221 break; 1222 } 1223 spin_unlock(&chip->substream_lock); 1224 return 0; 1225} 1226 1227static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream) 1228{ 1229 struct es1968 *chip = snd_pcm_substream_chip(substream); 1230 struct esschan *es = substream->runtime->private_data; 1231 unsigned int ptr; 1232 1233 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1234 1235 return bytes_to_frames(substream->runtime, ptr % es->dma_size); 1236} 1237 1238static struct snd_pcm_hardware snd_es1968_playback = { 1239 .info = (SNDRV_PCM_INFO_MMAP | 1240 SNDRV_PCM_INFO_MMAP_VALID | 1241 SNDRV_PCM_INFO_INTERLEAVED | 1242 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1243 /*SNDRV_PCM_INFO_PAUSE |*/ 1244 SNDRV_PCM_INFO_RESUME), 1245 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1246 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1247 .rate_min = 4000, 1248 .rate_max = 48000, 1249 .channels_min = 1, 1250 .channels_max = 2, 1251 .buffer_bytes_max = 65536, 1252 .period_bytes_min = 256, 1253 .period_bytes_max = 65536, 1254 .periods_min = 1, 1255 .periods_max = 1024, 1256 .fifo_size = 0, 1257}; 1258 1259static struct snd_pcm_hardware snd_es1968_capture = { 1260 .info = (SNDRV_PCM_INFO_NONINTERLEAVED | 1261 SNDRV_PCM_INFO_MMAP | 1262 SNDRV_PCM_INFO_MMAP_VALID | 1263 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1264 /*SNDRV_PCM_INFO_PAUSE |*/ 1265 SNDRV_PCM_INFO_RESUME), 1266 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, 1267 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1268 .rate_min = 4000, 1269 .rate_max = 48000, 1270 .channels_min = 1, 1271 .channels_max = 2, 1272 .buffer_bytes_max = 65536, 1273 .period_bytes_min = 256, 1274 .period_bytes_max = 65536, 1275 .periods_min = 1, 1276 .periods_max = 1024, 1277 .fifo_size = 0, 1278}; 1279 1280/* ************************* 1281 * DMA memory management * 1282 *************************/ 1283 1284/* Because the Maestro can only take addresses relative to the PCM base address 1285 register :( */ 1286 1287static int calc_available_memory_size(struct es1968 *chip) 1288{ 1289 struct list_head *p; 1290 int max_size = 0; 1291 1292 mutex_lock(&chip->memory_mutex); 1293 list_for_each(p, &chip->buf_list) { 1294 struct esm_memory *buf = list_entry(p, struct esm_memory, list); 1295 if (buf->empty && buf->buf.bytes > max_size) 1296 max_size = buf->buf.bytes; 1297 } 1298 mutex_unlock(&chip->memory_mutex); 1299 if (max_size >= 128*1024) 1300 max_size = 127*1024; 1301 return max_size; 1302} 1303 1304/* allocate a new memory chunk with the specified size */ 1305static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size) 1306{ 1307 struct esm_memory *buf; 1308 struct list_head *p; 1309 1310 size = ALIGN(size, ESM_MEM_ALIGN); 1311 mutex_lock(&chip->memory_mutex); 1312 list_for_each(p, &chip->buf_list) { 1313 buf = list_entry(p, struct esm_memory, list); 1314 if (buf->empty && buf->buf.bytes >= size) 1315 goto __found; 1316 } 1317 mutex_unlock(&chip->memory_mutex); 1318 return NULL; 1319 1320__found: 1321 if (buf->buf.bytes > size) { 1322 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1323 if (chunk == NULL) { 1324 mutex_unlock(&chip->memory_mutex); 1325 return NULL; 1326 } 1327 chunk->buf = buf->buf; 1328 chunk->buf.bytes -= size; 1329 chunk->buf.area += size; 1330 chunk->buf.addr += size; 1331 chunk->empty = 1; 1332 buf->buf.bytes = size; 1333 list_add(&chunk->list, &buf->list); 1334 } 1335 buf->empty = 0; 1336 mutex_unlock(&chip->memory_mutex); 1337 return buf; 1338} 1339 1340/* free a memory chunk */ 1341static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf) 1342{ 1343 struct esm_memory *chunk; 1344 1345 mutex_lock(&chip->memory_mutex); 1346 buf->empty = 1; 1347 if (buf->list.prev != &chip->buf_list) { 1348 chunk = list_entry(buf->list.prev, struct esm_memory, list); 1349 if (chunk->empty) { 1350 chunk->buf.bytes += buf->buf.bytes; 1351 list_del(&buf->list); 1352 kfree(buf); 1353 buf = chunk; 1354 } 1355 } 1356 if (buf->list.next != &chip->buf_list) { 1357 chunk = list_entry(buf->list.next, struct esm_memory, list); 1358 if (chunk->empty) { 1359 buf->buf.bytes += chunk->buf.bytes; 1360 list_del(&chunk->list); 1361 kfree(chunk); 1362 } 1363 } 1364 mutex_unlock(&chip->memory_mutex); 1365} 1366 1367static void snd_es1968_free_dmabuf(struct es1968 *chip) 1368{ 1369 struct list_head *p; 1370 1371 if (! chip->dma.area) 1372 return; 1373 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci)); 1374 while ((p = chip->buf_list.next) != &chip->buf_list) { 1375 struct esm_memory *chunk = list_entry(p, struct esm_memory, list); 1376 list_del(p); 1377 kfree(chunk); 1378 } 1379} 1380 1381static int __devinit 1382snd_es1968_init_dmabuf(struct es1968 *chip) 1383{ 1384 int err; 1385 struct esm_memory *chunk; 1386 1387 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV; 1388 chip->dma.dev.dev = snd_dma_pci_data(chip->pci); 1389 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) { 1390 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, 1391 snd_dma_pci_data(chip->pci), 1392 chip->total_bufsize, &chip->dma); 1393 if (err < 0 || ! chip->dma.area) { 1394 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n", 1395 chip->total_bufsize); 1396 return -ENOMEM; 1397 } 1398 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { 1399 snd_dma_free_pages(&chip->dma); 1400 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n"); 1401 return -ENOMEM; 1402 } 1403 } 1404 1405 INIT_LIST_HEAD(&chip->buf_list); 1406 /* allocate an empty chunk */ 1407 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1408 if (chunk == NULL) { 1409 snd_es1968_free_dmabuf(chip); 1410 return -ENOMEM; 1411 } 1412 memset(chip->dma.area, 0, ESM_MEM_ALIGN); 1413 chunk->buf = chip->dma; 1414 chunk->buf.area += ESM_MEM_ALIGN; 1415 chunk->buf.addr += ESM_MEM_ALIGN; 1416 chunk->buf.bytes -= ESM_MEM_ALIGN; 1417 chunk->empty = 1; 1418 list_add(&chunk->list, &chip->buf_list); 1419 1420 return 0; 1421} 1422 1423/* setup the dma_areas */ 1424/* buffer is extracted from the pre-allocated memory chunk */ 1425static int snd_es1968_hw_params(struct snd_pcm_substream *substream, 1426 struct snd_pcm_hw_params *hw_params) 1427{ 1428 struct es1968 *chip = snd_pcm_substream_chip(substream); 1429 struct snd_pcm_runtime *runtime = substream->runtime; 1430 struct esschan *chan = runtime->private_data; 1431 int size = params_buffer_bytes(hw_params); 1432 1433 if (chan->memory) { 1434 if (chan->memory->buf.bytes >= size) { 1435 runtime->dma_bytes = size; 1436 return 0; 1437 } 1438 snd_es1968_free_memory(chip, chan->memory); 1439 } 1440 chan->memory = snd_es1968_new_memory(chip, size); 1441 if (chan->memory == NULL) { 1442 // snd_printd("cannot allocate dma buffer: size = %d\n", size); 1443 return -ENOMEM; 1444 } 1445 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); 1446 return 1; /* area was changed */ 1447} 1448 1449/* remove dma areas if allocated */ 1450static int snd_es1968_hw_free(struct snd_pcm_substream *substream) 1451{ 1452 struct es1968 *chip = snd_pcm_substream_chip(substream); 1453 struct snd_pcm_runtime *runtime = substream->runtime; 1454 struct esschan *chan; 1455 1456 if (runtime->private_data == NULL) 1457 return 0; 1458 chan = runtime->private_data; 1459 if (chan->memory) { 1460 snd_es1968_free_memory(chip, chan->memory); 1461 chan->memory = NULL; 1462 } 1463 return 0; 1464} 1465 1466 1467/* 1468 * allocate APU pair 1469 */ 1470static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type) 1471{ 1472 int apu; 1473 1474 for (apu = 0; apu < NR_APUS; apu += 2) { 1475 if (chip->apu[apu] == ESM_APU_FREE && 1476 chip->apu[apu + 1] == ESM_APU_FREE) { 1477 chip->apu[apu] = chip->apu[apu + 1] = type; 1478 return apu; 1479 } 1480 } 1481 return -EBUSY; 1482} 1483 1484/* 1485 * release APU pair 1486 */ 1487static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu) 1488{ 1489 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; 1490} 1491 1492 1493/****************** 1494 * PCM open/close * 1495 ******************/ 1496 1497static int snd_es1968_playback_open(struct snd_pcm_substream *substream) 1498{ 1499 struct es1968 *chip = snd_pcm_substream_chip(substream); 1500 struct snd_pcm_runtime *runtime = substream->runtime; 1501 struct esschan *es; 1502 int apu1; 1503 1504 /* search 2 APUs */ 1505 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); 1506 if (apu1 < 0) 1507 return apu1; 1508 1509 es = kzalloc(sizeof(*es), GFP_KERNEL); 1510 if (!es) { 1511 snd_es1968_free_apu_pair(chip, apu1); 1512 return -ENOMEM; 1513 } 1514 1515 es->apu[0] = apu1; 1516 es->apu[1] = apu1 + 1; 1517 es->apu_mode[0] = 0; 1518 es->apu_mode[1] = 0; 1519 es->running = 0; 1520 es->substream = substream; 1521 es->mode = ESM_MODE_PLAY; 1522 1523 runtime->private_data = es; 1524 runtime->hw = snd_es1968_playback; 1525 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1526 calc_available_memory_size(chip); 1527 1528 spin_lock_irq(&chip->substream_lock); 1529 list_add(&es->list, &chip->substream_list); 1530 spin_unlock_irq(&chip->substream_lock); 1531 1532 return 0; 1533} 1534 1535static int snd_es1968_capture_open(struct snd_pcm_substream *substream) 1536{ 1537 struct snd_pcm_runtime *runtime = substream->runtime; 1538 struct es1968 *chip = snd_pcm_substream_chip(substream); 1539 struct esschan *es; 1540 int apu1, apu2; 1541 1542 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); 1543 if (apu1 < 0) 1544 return apu1; 1545 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); 1546 if (apu2 < 0) { 1547 snd_es1968_free_apu_pair(chip, apu1); 1548 return apu2; 1549 } 1550 1551 es = kzalloc(sizeof(*es), GFP_KERNEL); 1552 if (!es) { 1553 snd_es1968_free_apu_pair(chip, apu1); 1554 snd_es1968_free_apu_pair(chip, apu2); 1555 return -ENOMEM; 1556 } 1557 1558 es->apu[0] = apu1; 1559 es->apu[1] = apu1 + 1; 1560 es->apu[2] = apu2; 1561 es->apu[3] = apu2 + 1; 1562 es->apu_mode[0] = 0; 1563 es->apu_mode[1] = 0; 1564 es->apu_mode[2] = 0; 1565 es->apu_mode[3] = 0; 1566 es->running = 0; 1567 es->substream = substream; 1568 es->mode = ESM_MODE_CAPTURE; 1569 1570 /* get mixbuffer */ 1571 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) { 1572 snd_es1968_free_apu_pair(chip, apu1); 1573 snd_es1968_free_apu_pair(chip, apu2); 1574 kfree(es); 1575 return -ENOMEM; 1576 } 1577 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); 1578 1579 runtime->private_data = es; 1580 runtime->hw = snd_es1968_capture; 1581 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1582 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ 1583 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); 1584 1585 spin_lock_irq(&chip->substream_lock); 1586 list_add(&es->list, &chip->substream_list); 1587 spin_unlock_irq(&chip->substream_lock); 1588 1589 return 0; 1590} 1591 1592static int snd_es1968_playback_close(struct snd_pcm_substream *substream) 1593{ 1594 struct es1968 *chip = snd_pcm_substream_chip(substream); 1595 struct esschan *es; 1596 1597 if (substream->runtime->private_data == NULL) 1598 return 0; 1599 es = substream->runtime->private_data; 1600 spin_lock_irq(&chip->substream_lock); 1601 list_del(&es->list); 1602 spin_unlock_irq(&chip->substream_lock); 1603 snd_es1968_free_apu_pair(chip, es->apu[0]); 1604 kfree(es); 1605 1606 return 0; 1607} 1608 1609static int snd_es1968_capture_close(struct snd_pcm_substream *substream) 1610{ 1611 struct es1968 *chip = snd_pcm_substream_chip(substream); 1612 struct esschan *es; 1613 1614 if (substream->runtime->private_data == NULL) 1615 return 0; 1616 es = substream->runtime->private_data; 1617 spin_lock_irq(&chip->substream_lock); 1618 list_del(&es->list); 1619 spin_unlock_irq(&chip->substream_lock); 1620 snd_es1968_free_memory(chip, es->mixbuf); 1621 snd_es1968_free_apu_pair(chip, es->apu[0]); 1622 snd_es1968_free_apu_pair(chip, es->apu[2]); 1623 kfree(es); 1624 1625 return 0; 1626} 1627 1628static struct snd_pcm_ops snd_es1968_playback_ops = { 1629 .open = snd_es1968_playback_open, 1630 .close = snd_es1968_playback_close, 1631 .ioctl = snd_pcm_lib_ioctl, 1632 .hw_params = snd_es1968_hw_params, 1633 .hw_free = snd_es1968_hw_free, 1634 .prepare = snd_es1968_pcm_prepare, 1635 .trigger = snd_es1968_pcm_trigger, 1636 .pointer = snd_es1968_pcm_pointer, 1637}; 1638 1639static struct snd_pcm_ops snd_es1968_capture_ops = { 1640 .open = snd_es1968_capture_open, 1641 .close = snd_es1968_capture_close, 1642 .ioctl = snd_pcm_lib_ioctl, 1643 .hw_params = snd_es1968_hw_params, 1644 .hw_free = snd_es1968_hw_free, 1645 .prepare = snd_es1968_pcm_prepare, 1646 .trigger = snd_es1968_pcm_trigger, 1647 .pointer = snd_es1968_pcm_pointer, 1648}; 1649 1650 1651/* 1652 * measure clock 1653 */ 1654#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ 1655 1656static void __devinit es1968_measure_clock(struct es1968 *chip) 1657{ 1658 int i, apu; 1659 unsigned int pa, offset, t; 1660 struct esm_memory *memory; 1661 struct timeval start_time, stop_time; 1662 1663 if (chip->clock == 0) 1664 chip->clock = 48000; /* default clock value */ 1665 1666 /* search 2 APUs (although one apu is enough) */ 1667 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) { 1668 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n"); 1669 return; 1670 } 1671 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) { 1672 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock); 1673 snd_es1968_free_apu_pair(chip, apu); 1674 return; 1675 } 1676 1677 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); 1678 1679 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); 1680 1681 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); 1682 pa |= 0x00400000; /* System RAM (Bit 22) */ 1683 1684 /* initialize apu */ 1685 for (i = 0; i < 16; i++) 1686 apu_set_register(chip, apu, i, 0x0000); 1687 1688 apu_set_register(chip, apu, 0, 0x400f); 1689 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); 1690 apu_set_register(chip, apu, 5, pa & 0xffff); 1691 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); 1692 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); 1693 apu_set_register(chip, apu, 8, 0x0000); 1694 apu_set_register(chip, apu, 9, 0xD000); 1695 apu_set_register(chip, apu, 10, 0x8F08); 1696 apu_set_register(chip, apu, 11, 0x0000); 1697 spin_lock_irq(&chip->reg_lock); 1698 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 1699 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ 1700 spin_unlock_irq(&chip->reg_lock); 1701 1702 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ 1703 1704 chip->in_measurement = 1; 1705 chip->measure_apu = apu; 1706 spin_lock_irq(&chip->reg_lock); 1707 snd_es1968_bob_inc(chip, ESM_BOB_FREQ); 1708 __apu_set_register(chip, apu, 5, pa & 0xffff); 1709 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1710 do_gettimeofday(&start_time); 1711 spin_unlock_irq(&chip->reg_lock); 1712 msleep(50); 1713 spin_lock_irq(&chip->reg_lock); 1714 offset = __apu_get_register(chip, apu, 5); 1715 do_gettimeofday(&stop_time); 1716 snd_es1968_trigger_apu(chip, apu, 0); /* stop */ 1717 snd_es1968_bob_dec(chip); 1718 chip->in_measurement = 0; 1719 spin_unlock_irq(&chip->reg_lock); 1720 1721 /* check the current position */ 1722 offset -= (pa & 0xffff); 1723 offset &= 0xfffe; 1724 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); 1725 1726 t = stop_time.tv_sec - start_time.tv_sec; 1727 t *= 1000000; 1728 if (stop_time.tv_usec < start_time.tv_usec) 1729 t -= start_time.tv_usec - stop_time.tv_usec; 1730 else 1731 t += stop_time.tv_usec - start_time.tv_usec; 1732 if (t == 0) { 1733 snd_printk(KERN_ERR "?? calculation error..\n"); 1734 } else { 1735 offset *= 1000; 1736 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; 1737 if (offset < 47500 || offset > 48500) { 1738 if (offset >= 40000 && offset <= 50000) 1739 chip->clock = (chip->clock * offset) / 48000; 1740 } 1741 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock); 1742 } 1743 snd_es1968_free_memory(chip, memory); 1744 snd_es1968_free_apu_pair(chip, apu); 1745} 1746 1747 1748/* 1749 */ 1750 1751static void snd_es1968_pcm_free(struct snd_pcm *pcm) 1752{ 1753 struct es1968 *esm = pcm->private_data; 1754 snd_es1968_free_dmabuf(esm); 1755 esm->pcm = NULL; 1756} 1757 1758static int __devinit 1759snd_es1968_pcm(struct es1968 *chip, int device) 1760{ 1761 struct snd_pcm *pcm; 1762 int err; 1763 1764 /* get DMA buffer */ 1765 if ((err = snd_es1968_init_dmabuf(chip)) < 0) 1766 return err; 1767 1768 /* set PCMBAR */ 1769 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 1770 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); 1771 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); 1772 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); 1773 1774 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device, 1775 chip->playback_streams, 1776 chip->capture_streams, &pcm)) < 0) 1777 return err; 1778 1779 pcm->private_data = chip; 1780 pcm->private_free = snd_es1968_pcm_free; 1781 1782 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); 1783 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); 1784 1785 pcm->info_flags = 0; 1786 1787 strcpy(pcm->name, "ESS Maestro"); 1788 1789 chip->pcm = pcm; 1790 1791 return 0; 1792} 1793 1794/* 1795 * update pointer 1796 */ 1797static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es) 1798{ 1799 unsigned int hwptr; 1800 unsigned int diff; 1801 struct snd_pcm_substream *subs = es->substream; 1802 1803 if (subs == NULL || !es->running) 1804 return; 1805 1806 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1807 hwptr %= es->dma_size; 1808 1809 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; 1810 1811 es->hwptr = hwptr; 1812 es->count += diff; 1813 1814 if (es->count > es->frag_size) { 1815 spin_unlock(&chip->substream_lock); 1816 snd_pcm_period_elapsed(subs); 1817 spin_lock(&chip->substream_lock); 1818 es->count %= es->frag_size; 1819 } 1820} 1821 1822/* 1823 */ 1824static void es1968_update_hw_volume(unsigned long private_data) 1825{ 1826 struct es1968 *chip = (struct es1968 *) private_data; 1827 int x, val; 1828 unsigned long flags; 1829 1830 /* Figure out which volume control button was pushed, 1831 based on differences from the default register 1832 values. */ 1833 x = inb(chip->io_port + 0x1c) & 0xee; 1834 /* Reset the volume control registers. */ 1835 outb(0x88, chip->io_port + 0x1c); 1836 outb(0x88, chip->io_port + 0x1d); 1837 outb(0x88, chip->io_port + 0x1e); 1838 outb(0x88, chip->io_port + 0x1f); 1839 1840 if (chip->in_suspend) 1841 return; 1842 1843 if (! chip->master_switch || ! chip->master_volume) 1844 return; 1845 1846 spin_lock_irqsave(&chip->ac97_lock, flags); 1847 val = chip->ac97->regs[AC97_MASTER]; 1848 switch (x) { 1849 case 0x88: 1850 /* mute */ 1851 val ^= 0x8000; 1852 chip->ac97->regs[AC97_MASTER] = val; 1853 outw(val, chip->io_port + ESM_AC97_DATA); 1854 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1855 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1856 &chip->master_switch->id); 1857 break; 1858 case 0xaa: 1859 /* volume up */ 1860 if ((val & 0x7f) > 0) 1861 val--; 1862 if ((val & 0x7f00) > 0) 1863 val -= 0x0100; 1864 chip->ac97->regs[AC97_MASTER] = val; 1865 outw(val, chip->io_port + ESM_AC97_DATA); 1866 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1867 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1868 &chip->master_volume->id); 1869 break; 1870 case 0x66: 1871 /* volume down */ 1872 if ((val & 0x7f) < 0x1f) 1873 val++; 1874 if ((val & 0x7f00) < 0x1f00) 1875 val += 0x0100; 1876 chip->ac97->regs[AC97_MASTER] = val; 1877 outw(val, chip->io_port + ESM_AC97_DATA); 1878 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1879 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1880 &chip->master_volume->id); 1881 break; 1882 } 1883 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1884} 1885 1886/* 1887 * interrupt handler 1888 */ 1889static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id) 1890{ 1891 struct es1968 *chip = dev_id; 1892 u32 event; 1893 1894 if (!(event = inb(chip->io_port + 0x1A))) 1895 return IRQ_NONE; 1896 1897 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); 1898 1899 if (event & ESM_HWVOL_IRQ) 1900 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */ 1901 1902 /* else ack 'em all, i imagine */ 1903 outb(0xFF, chip->io_port + 0x1A); 1904 1905 if ((event & ESM_MPU401_IRQ) && chip->rmidi) { 1906 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1907 } 1908 1909 if (event & ESM_SOUND_IRQ) { 1910 struct list_head *p; 1911 spin_lock(&chip->substream_lock); 1912 list_for_each(p, &chip->substream_list) { 1913 struct esschan *es = list_entry(p, struct esschan, list); 1914 if (es->running) 1915 snd_es1968_update_pcm(chip, es); 1916 } 1917 spin_unlock(&chip->substream_lock); 1918 if (chip->in_measurement) { 1919 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); 1920 if (curp < chip->measure_lastpos) 1921 chip->measure_count++; 1922 chip->measure_lastpos = curp; 1923 } 1924 } 1925 1926 return IRQ_HANDLED; 1927} 1928 1929/* 1930 * Mixer stuff 1931 */ 1932 1933static int __devinit 1934snd_es1968_mixer(struct es1968 *chip) 1935{ 1936 struct snd_ac97_bus *pbus; 1937 struct snd_ac97_template ac97; 1938 struct snd_ctl_elem_id id; 1939 int err; 1940 static struct snd_ac97_bus_ops ops = { 1941 .write = snd_es1968_ac97_write, 1942 .read = snd_es1968_ac97_read, 1943 }; 1944 1945 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 1946 return err; 1947 pbus->no_vra = 1; /* ES1968 doesn't need VRA */ 1948 1949 memset(&ac97, 0, sizeof(ac97)); 1950 ac97.private_data = chip; 1951 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 1952 return err; 1953 1954 /* attach master switch / volumes for h/w volume control */ 1955 memset(&id, 0, sizeof(id)); 1956 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1957 strcpy(id.name, "Master Playback Switch"); 1958 chip->master_switch = snd_ctl_find_id(chip->card, &id); 1959 memset(&id, 0, sizeof(id)); 1960 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1961 strcpy(id.name, "Master Playback Volume"); 1962 chip->master_volume = snd_ctl_find_id(chip->card, &id); 1963 1964 return 0; 1965} 1966 1967/* 1968 * reset ac97 codec 1969 */ 1970 1971static void snd_es1968_ac97_reset(struct es1968 *chip) 1972{ 1973 unsigned long ioaddr = chip->io_port; 1974 1975 unsigned short save_ringbus_a; 1976 unsigned short save_68; 1977 unsigned short w; 1978 unsigned int vend; 1979 1980 /* save configuration */ 1981 save_ringbus_a = inw(ioaddr + 0x36); 1982 1983 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ 1984 /* set command/status address i/o to 1st codec */ 1985 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 1986 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 1987 1988 /* disable ac link */ 1989 outw(0x0000, ioaddr + 0x36); 1990 save_68 = inw(ioaddr + 0x68); 1991 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ 1992 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 1993 if (w & 1) 1994 save_68 |= 0x10; 1995 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ 1996 outw(0x0001, ioaddr + 0x68); /* gpio write */ 1997 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 1998 udelay(20); 1999 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2000 msleep(20); 2001 2002 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2003 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); 2004 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); 2005 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); 2006 2007 /* now the second codec */ 2008 /* disable ac link */ 2009 outw(0x0000, ioaddr + 0x36); 2010 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ 2011 save_68 = inw(ioaddr + 0x68); 2012 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ 2013 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2014 udelay(20); 2015 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2016 msleep(500); 2017 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2018 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2019 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2020 2021 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { 2022 /* turn on external amp? */ 2023 outw(0xf9ff, ioaddr + 0x64); 2024 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); 2025 outw(0x0209, ioaddr + 0x60); 2026 } 2027 2028 /* restore.. */ 2029 outw(save_ringbus_a, ioaddr + 0x36); 2030 2031 /* Turn on the 978 docking chip. 2032 First frob the "master output enable" bit, 2033 then set most of the playback volume control registers to max. */ 2034 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); 2035 outb(0xff, ioaddr+0xc3); 2036 outb(0xff, ioaddr+0xc4); 2037 outb(0xff, ioaddr+0xc6); 2038 outb(0xff, ioaddr+0xc8); 2039 outb(0x3f, ioaddr+0xcf); 2040 outb(0x3f, ioaddr+0xd0); 2041} 2042 2043static void snd_es1968_reset(struct es1968 *chip) 2044{ 2045 /* Reset */ 2046 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, 2047 chip->io_port + ESM_PORT_HOST_IRQ); 2048 udelay(10); 2049 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); 2050 udelay(10); 2051} 2052 2053/* 2054 * initialize maestro chip 2055 */ 2056static void snd_es1968_chip_init(struct es1968 *chip) 2057{ 2058 struct pci_dev *pci = chip->pci; 2059 int i; 2060 unsigned long iobase = chip->io_port; 2061 u16 w; 2062 u32 n; 2063 2064 /* We used to muck around with pci config space that 2065 * we had no business messing with. We don't know enough 2066 * about the machine to know which DMA mode is appropriate, 2067 * etc. We were guessing wrong on some machines and making 2068 * them unhappy. We now trust in the BIOS to do things right, 2069 * which almost certainly means a new host of problems will 2070 * arise with broken BIOS implementations. screw 'em. 2071 * We're already intolerant of machines that don't assign 2072 * IRQs. 2073 */ 2074 2075 /* Config Reg A */ 2076 pci_read_config_word(pci, ESM_CONFIG_A, &w); 2077 2078 w &= ~DMA_CLEAR; /* Clear DMA bits */ 2079 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ 2080 w &= ~SAFEGUARD; /* Safeguard off */ 2081 w |= POST_WRITE; /* Posted write */ 2082 w |= PCI_TIMING; /* PCI timing on */ 2083 w &= ~SWAP_LR; /* swap left/right 2084 seems to only have effect on SB 2085 Emulation */ 2086 w &= ~SUBTR_DECODE; /* Subtractive decode off */ 2087 2088 pci_write_config_word(pci, ESM_CONFIG_A, w); 2089 2090 /* Config Reg B */ 2091 2092 pci_read_config_word(pci, ESM_CONFIG_B, &w); 2093 2094 w &= ~(1 << 15); /* Turn off internal clock multiplier */ 2095 w &= ~(1 << 14); /* External clock */ 2096 2097 w &= ~SPDIF_CONFB; /* disable S/PDIF output */ 2098 w |= HWV_CONFB; /* HWV on */ 2099 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ 2100 w &= ~GPIO_CONFB; /* GPIO 4:5 */ 2101 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ 2102 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ 2103 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ 2104 w &= ~(1 << 1); /* reserved, always write 0 */ 2105 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ 2106 2107 pci_write_config_word(pci, ESM_CONFIG_B, w); 2108 2109 /* DDMA off */ 2110 2111 pci_read_config_word(pci, ESM_DDMA, &w); 2112 w &= ~(1 << 0); 2113 pci_write_config_word(pci, ESM_DDMA, w); 2114 2115 /* 2116 * Legacy mode 2117 */ 2118 2119 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); 2120 2121 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */ 2122 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ 2123 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ 2124 2125 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); 2126 2127 /* Set up 978 docking control chip. */ 2128 pci_read_config_word(pci, 0x58, &w); 2129 w|=1<<2; /* Enable 978. */ 2130 w|=1<<3; /* Turn on 978 hardware volume control. */ 2131 w&=~(1<<11); /* Turn on 978 mixer volume control. */ 2132 pci_write_config_word(pci, 0x58, w); 2133 2134 /* Sound Reset */ 2135 2136 snd_es1968_reset(chip); 2137 2138 /* 2139 * Ring Bus Setup 2140 */ 2141 2142 /* setup usual 0x34 stuff.. 0x36 may be chip specific */ 2143 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ 2144 udelay(20); 2145 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ 2146 udelay(20); 2147 2148 /* 2149 * Reset the CODEC 2150 */ 2151 2152 snd_es1968_ac97_reset(chip); 2153 2154 /* Ring Bus Control B */ 2155 2156 n = inl(iobase + ESM_RING_BUS_CONTR_B); 2157 n &= ~RINGB_EN_SPDIF; /* SPDIF off */ 2158 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ 2159 outl(n, iobase + ESM_RING_BUS_CONTR_B); 2160 2161 /* Set hardware volume control registers to midpoints. 2162 We can tell which button was pushed based on how they change. */ 2163 outb(0x88, iobase+0x1c); 2164 outb(0x88, iobase+0x1d); 2165 outb(0x88, iobase+0x1e); 2166 outb(0x88, iobase+0x1f); 2167 2168 /* it appears some maestros (dell 7500) only work if these are set, 2169 regardless of wether we use the assp or not. */ 2170 2171 outb(0, iobase + ASSP_CONTROL_B); 2172 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ 2173 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ 2174 2175 /* 2176 * set up wavecache 2177 */ 2178 for (i = 0; i < 16; i++) { 2179 /* Write 0 into the buffer area 0x1E0->1EF */ 2180 outw(0x01E0 + i, iobase + WC_INDEX); 2181 outw(0x0000, iobase + WC_DATA); 2182 2183 /* The 1.10 test program seem to write 0 into the buffer area 2184 * 0x1D0-0x1DF too.*/ 2185 outw(0x01D0 + i, iobase + WC_INDEX); 2186 outw(0x0000, iobase + WC_DATA); 2187 } 2188 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2189 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); 2190 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2191 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); 2192 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2193 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); 2194 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2195 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); 2196 2197 2198 maestro_write(chip, IDR2_CRAM_DATA, 0x0000); 2199 /* Now back to the DirectSound stuff */ 2200 /* audio serial configuration.. ? */ 2201 maestro_write(chip, 0x08, 0xB004); 2202 maestro_write(chip, 0x09, 0x001B); 2203 maestro_write(chip, 0x0A, 0x8000); 2204 maestro_write(chip, 0x0B, 0x3F37); 2205 maestro_write(chip, 0x0C, 0x0098); 2206 2207 /* parallel in, has something to do with recording :) */ 2208 maestro_write(chip, 0x0C, 2209 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); 2210 /* parallel out */ 2211 maestro_write(chip, 0x0C, 2212 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); 2213 2214 maestro_write(chip, 0x0D, 0x7632); 2215 2216 /* Wave cache control on - test off, sg off, 2217 enable, enable extra chans 1Mb */ 2218 2219 w = inw(iobase + WC_CONTROL); 2220 2221 w &= ~0xFA00; /* Seems to be reserved? I don't know */ 2222 w |= 0xA000; /* reserved... I don't know */ 2223 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable 2224 Seems to crash the Computer if enabled... */ 2225 w |= 0x0100; /* Wave Cache Operation Enabled */ 2226 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ 2227 w &= ~0x0060; /* Clear Wavtable Size */ 2228 w |= 0x0020; /* Wavetable Size : 1MB */ 2229 /* Bit 4 is reserved */ 2230 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ 2231 /* Bit 1 is reserved */ 2232 w &= ~0x0001; /* Test Mode off */ 2233 2234 outw(w, iobase + WC_CONTROL); 2235 2236 /* Now clear the APU control ram */ 2237 for (i = 0; i < NR_APUS; i++) { 2238 for (w = 0; w < NR_APU_REGS; w++) 2239 apu_set_register(chip, i, w, 0); 2240 2241 } 2242} 2243 2244/* Enable IRQ's */ 2245static void snd_es1968_start_irq(struct es1968 *chip) 2246{ 2247 unsigned short w; 2248 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; 2249 if (chip->rmidi) 2250 w |= ESM_HIRQ_MPU401; 2251 outw(w, chip->io_port + ESM_PORT_HOST_IRQ); 2252} 2253 2254#ifdef CONFIG_PM 2255/* 2256 * PM support 2257 */ 2258static int es1968_suspend(struct pci_dev *pci, pm_message_t state) 2259{ 2260 struct snd_card *card = pci_get_drvdata(pci); 2261 struct es1968 *chip = card->private_data; 2262 2263 if (! chip->do_pm) 2264 return 0; 2265 2266 chip->in_suspend = 1; 2267 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2268 snd_pcm_suspend_all(chip->pcm); 2269 snd_ac97_suspend(chip->ac97); 2270 snd_es1968_bob_stop(chip); 2271 2272 pci_disable_device(pci); 2273 pci_save_state(pci); 2274 pci_set_power_state(pci, pci_choose_state(pci, state)); 2275 return 0; 2276} 2277 2278static int es1968_resume(struct pci_dev *pci) 2279{ 2280 struct snd_card *card = pci_get_drvdata(pci); 2281 struct es1968 *chip = card->private_data; 2282 struct list_head *p; 2283 2284 if (! chip->do_pm) 2285 return 0; 2286 2287 /* restore all our config */ 2288 pci_set_power_state(pci, PCI_D0); 2289 pci_restore_state(pci); 2290 if (pci_enable_device(pci) < 0) { 2291 printk(KERN_ERR "es1968: pci_enable_device failed, " 2292 "disabling device\n"); 2293 snd_card_disconnect(card); 2294 return -EIO; 2295 } 2296 pci_set_master(pci); 2297 2298 snd_es1968_chip_init(chip); 2299 2300 /* need to restore the base pointers.. */ 2301 if (chip->dma.addr) { 2302 /* set PCMBAR */ 2303 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 2304 } 2305 2306 snd_es1968_start_irq(chip); 2307 2308 /* restore ac97 state */ 2309 snd_ac97_resume(chip->ac97); 2310 2311 list_for_each(p, &chip->substream_list) { 2312 struct esschan *es = list_entry(p, struct esschan, list); 2313 switch (es->mode) { 2314 case ESM_MODE_PLAY: 2315 snd_es1968_playback_setup(chip, es, es->substream->runtime); 2316 break; 2317 case ESM_MODE_CAPTURE: 2318 snd_es1968_capture_setup(chip, es, es->substream->runtime); 2319 break; 2320 } 2321 } 2322 2323 /* start timer again */ 2324 if (chip->bobclient) 2325 snd_es1968_bob_start(chip); 2326 2327 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2328 chip->in_suspend = 0; 2329 return 0; 2330} 2331#endif /* CONFIG_PM */ 2332 2333#ifdef SUPPORT_JOYSTICK 2334#define JOYSTICK_ADDR 0x200 2335static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev) 2336{ 2337 struct gameport *gp; 2338 struct resource *r; 2339 u16 val; 2340 2341 if (!joystick[dev]) 2342 return -ENODEV; 2343 2344 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport"); 2345 if (!r) 2346 return -EBUSY; 2347 2348 chip->gameport = gp = gameport_allocate_port(); 2349 if (!gp) { 2350 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n"); 2351 release_and_free_resource(r); 2352 return -ENOMEM; 2353 } 2354 2355 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); 2356 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); 2357 2358 gameport_set_name(gp, "ES1968 Gameport"); 2359 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2360 gameport_set_dev_parent(gp, &chip->pci->dev); 2361 gp->io = JOYSTICK_ADDR; 2362 gameport_set_port_data(gp, r); 2363 2364 gameport_register_port(gp); 2365 2366 return 0; 2367} 2368 2369static void snd_es1968_free_gameport(struct es1968 *chip) 2370{ 2371 if (chip->gameport) { 2372 struct resource *r = gameport_get_port_data(chip->gameport); 2373 2374 gameport_unregister_port(chip->gameport); 2375 chip->gameport = NULL; 2376 2377 release_and_free_resource(r); 2378 } 2379} 2380#else 2381static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; } 2382static inline void snd_es1968_free_gameport(struct es1968 *chip) { } 2383#endif 2384 2385static int snd_es1968_free(struct es1968 *chip) 2386{ 2387 if (chip->io_port) { 2388 synchronize_irq(chip->irq); 2389 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 2390 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ 2391 } 2392 2393 if (chip->irq >= 0) 2394 free_irq(chip->irq, chip); 2395 snd_es1968_free_gameport(chip); 2396 chip->master_switch = NULL; 2397 chip->master_volume = NULL; 2398 pci_release_regions(chip->pci); 2399 pci_disable_device(chip->pci); 2400 kfree(chip); 2401 return 0; 2402} 2403 2404static int snd_es1968_dev_free(struct snd_device *device) 2405{ 2406 struct es1968 *chip = device->device_data; 2407 return snd_es1968_free(chip); 2408} 2409 2410struct ess_device_list { 2411 unsigned short type; /* chip type */ 2412 unsigned short vendor; /* subsystem vendor id */ 2413}; 2414 2415static struct ess_device_list pm_whitelist[] __devinitdata = { 2416 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ 2417 { TYPE_MAESTRO2E, 0x1028 }, 2418 { TYPE_MAESTRO2E, 0x103c }, 2419 { TYPE_MAESTRO2E, 0x1179 }, 2420 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ 2421 { TYPE_MAESTRO2E, 0x1558 }, 2422}; 2423 2424static struct ess_device_list mpu_blacklist[] __devinitdata = { 2425 { TYPE_MAESTRO2, 0x125d }, 2426}; 2427 2428static int __devinit snd_es1968_create(struct snd_card *card, 2429 struct pci_dev *pci, 2430 int total_bufsize, 2431 int play_streams, 2432 int capt_streams, 2433 int chip_type, 2434 int do_pm, 2435 struct es1968 **chip_ret) 2436{ 2437 static struct snd_device_ops ops = { 2438 .dev_free = snd_es1968_dev_free, 2439 }; 2440 struct es1968 *chip; 2441 int i, err; 2442 2443 *chip_ret = NULL; 2444 2445 /* enable PCI device */ 2446 if ((err = pci_enable_device(pci)) < 0) 2447 return err; 2448 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2449 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 || 2450 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) { 2451 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); 2452 pci_disable_device(pci); 2453 return -ENXIO; 2454 } 2455 2456 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2457 if (! chip) { 2458 pci_disable_device(pci); 2459 return -ENOMEM; 2460 } 2461 2462 /* Set Vars */ 2463 chip->type = chip_type; 2464 spin_lock_init(&chip->reg_lock); 2465 spin_lock_init(&chip->substream_lock); 2466 INIT_LIST_HEAD(&chip->buf_list); 2467 INIT_LIST_HEAD(&chip->substream_list); 2468 spin_lock_init(&chip->ac97_lock); 2469 mutex_init(&chip->memory_mutex); 2470 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip); 2471 chip->card = card; 2472 chip->pci = pci; 2473 chip->irq = -1; 2474 chip->total_bufsize = total_bufsize; /* in bytes */ 2475 chip->playback_streams = play_streams; 2476 chip->capture_streams = capt_streams; 2477 2478 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) { 2479 kfree(chip); 2480 pci_disable_device(pci); 2481 return err; 2482 } 2483 chip->io_port = pci_resource_start(pci, 0); 2484 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED, 2485 "ESS Maestro", chip)) { 2486 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2487 snd_es1968_free(chip); 2488 return -EBUSY; 2489 } 2490 chip->irq = pci->irq; 2491 2492 /* Clear Maestro_map */ 2493 for (i = 0; i < 32; i++) 2494 chip->maestro_map[i] = 0; 2495 2496 /* Clear Apu Map */ 2497 for (i = 0; i < NR_APUS; i++) 2498 chip->apu[i] = ESM_APU_FREE; 2499 2500 /* just to be sure */ 2501 pci_set_master(pci); 2502 2503 if (do_pm > 1) { 2504 /* disable power-management if not on the whitelist */ 2505 unsigned short vend; 2506 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2507 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) { 2508 if (chip->type == pm_whitelist[i].type && 2509 vend == pm_whitelist[i].vendor) { 2510 do_pm = 1; 2511 break; 2512 } 2513 } 2514 if (do_pm > 1) { 2515 /* not matched; disabling pm */ 2516 printk(KERN_INFO "es1968: not attempting power management.\n"); 2517 do_pm = 0; 2518 } 2519 } 2520 chip->do_pm = do_pm; 2521 2522 snd_es1968_chip_init(chip); 2523 2524 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2525 snd_es1968_free(chip); 2526 return err; 2527 } 2528 2529 snd_card_set_dev(card, &pci->dev); 2530 2531 *chip_ret = chip; 2532 2533 return 0; 2534} 2535 2536 2537/* 2538 */ 2539static int __devinit snd_es1968_probe(struct pci_dev *pci, 2540 const struct pci_device_id *pci_id) 2541{ 2542 static int dev; 2543 struct snd_card *card; 2544 struct es1968 *chip; 2545 unsigned int i; 2546 int err; 2547 2548 if (dev >= SNDRV_CARDS) 2549 return -ENODEV; 2550 if (!enable[dev]) { 2551 dev++; 2552 return -ENOENT; 2553 } 2554 2555 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2556 if (!card) 2557 return -ENOMEM; 2558 2559 if (total_bufsize[dev] < 128) 2560 total_bufsize[dev] = 128; 2561 if (total_bufsize[dev] > 4096) 2562 total_bufsize[dev] = 4096; 2563 if ((err = snd_es1968_create(card, pci, 2564 total_bufsize[dev] * 1024, /* in bytes */ 2565 pcm_substreams_p[dev], 2566 pcm_substreams_c[dev], 2567 pci_id->driver_data, 2568 use_pm[dev], 2569 &chip)) < 0) { 2570 snd_card_free(card); 2571 return err; 2572 } 2573 card->private_data = chip; 2574 2575 switch (chip->type) { 2576 case TYPE_MAESTRO2E: 2577 strcpy(card->driver, "ES1978"); 2578 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); 2579 break; 2580 case TYPE_MAESTRO2: 2581 strcpy(card->driver, "ES1968"); 2582 strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); 2583 break; 2584 case TYPE_MAESTRO: 2585 strcpy(card->driver, "ESM1"); 2586 strcpy(card->shortname, "ESS Maestro 1"); 2587 break; 2588 } 2589 2590 if ((err = snd_es1968_pcm(chip, 0)) < 0) { 2591 snd_card_free(card); 2592 return err; 2593 } 2594 2595 if ((err = snd_es1968_mixer(chip)) < 0) { 2596 snd_card_free(card); 2597 return err; 2598 } 2599 2600 if (enable_mpu[dev] == 2) { 2601 /* check the black list */ 2602 unsigned short vend; 2603 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2604 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) { 2605 if (chip->type == mpu_blacklist[i].type && 2606 vend == mpu_blacklist[i].vendor) { 2607 enable_mpu[dev] = 0; 2608 break; 2609 } 2610 } 2611 } 2612 if (enable_mpu[dev]) { 2613 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, 2614 chip->io_port + ESM_MPU401_PORT, 2615 MPU401_INFO_INTEGRATED, 2616 chip->irq, 0, &chip->rmidi)) < 0) { 2617 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n"); 2618 } 2619 } 2620 2621 snd_es1968_create_gameport(chip, dev); 2622 2623 snd_es1968_start_irq(chip); 2624 2625 chip->clock = clock[dev]; 2626 if (! chip->clock) 2627 es1968_measure_clock(chip); 2628 2629 sprintf(card->longname, "%s at 0x%lx, irq %i", 2630 card->shortname, chip->io_port, chip->irq); 2631 2632 if ((err = snd_card_register(card)) < 0) { 2633 snd_card_free(card); 2634 return err; 2635 } 2636 pci_set_drvdata(pci, card); 2637 dev++; 2638 return 0; 2639} 2640 2641static void __devexit snd_es1968_remove(struct pci_dev *pci) 2642{ 2643 snd_card_free(pci_get_drvdata(pci)); 2644 pci_set_drvdata(pci, NULL); 2645} 2646 2647static struct pci_driver driver = { 2648 .name = "ES1968 (ESS Maestro)", 2649 .id_table = snd_es1968_ids, 2650 .probe = snd_es1968_probe, 2651 .remove = __devexit_p(snd_es1968_remove), 2652#ifdef CONFIG_PM 2653 .suspend = es1968_suspend, 2654 .resume = es1968_resume, 2655#endif 2656}; 2657 2658static int __init alsa_card_es1968_init(void) 2659{ 2660 return pci_register_driver(&driver); 2661} 2662 2663static void __exit alsa_card_es1968_exit(void) 2664{ 2665 pci_unregister_driver(&driver); 2666} 2667 2668module_init(alsa_card_es1968_init) 2669module_exit(alsa_card_es1968_exit) 2670