1/******************************************************************************* 2* 3* "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver. 4* 5* Copyright (C) 2001 Broadcom Corporation. 6* Copyright (C) 2000,2001 Cirrus Logic Corp. 7* -- adapted from drivers by Thomas Sailer, 8* -- but don't bug him; Problems should go to: 9* -- tom woller (twoller@crystal.cirrus.com) or 10* (audio@crystal.cirrus.com). 11* -- adapted from cs4281 PCI driver for cs4297a on 12* BCM1250 Synchronous Serial interface 13* (Kip Walker, Broadcom Corp.) 14* Copyright (C) 2004 Maciej W. Rozycki 15* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 16* 17* This program is free software; you can redistribute it and/or modify 18* it under the terms of the GNU General Public License as published by 19* the Free Software Foundation; either version 2 of the License, or 20* (at your option) any later version. 21* 22* This program is distributed in the hope that it will be useful, 23* but WITHOUT ANY WARRANTY; without even the implied warranty of 24* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25* GNU General Public License for more details. 26* 27* You should have received a copy of the GNU General Public License 28* along with this program; if not, write to the Free Software 29* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 30* 31* Module command line parameters: 32* none 33* 34* Supported devices: 35* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible 36* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible 37* /dev/midi simple MIDI UART interface, no ioctl 38* 39* Modification History 40* 08/20/00 trw - silence and no stopping DAC until release 41* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop. 42* 09/18/00 trw - added 16bit only record with conversion 43* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous 44* capture/playback rates) 45* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin 46* libOSSm.so) 47* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal) 48* 11/03/00 trw - fixed interrupt loss/stutter, added debug. 49* 11/10/00 bkz - added __devinit to cs4297a_hw_init() 50* 11/10/00 trw - fixed SMP and capture spinlock hang. 51* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm. 52* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix. 53* 12/08/00 trw - added PM support. 54* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 55* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident. 56* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup. 57* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use 58* defaultorder-100 as power of 2 for the buffer size. example: 59* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size. 60* 61*******************************************************************************/ 62 63#include <linux/list.h> 64#include <linux/module.h> 65#include <linux/string.h> 66#include <linux/ioport.h> 67#include <linux/sched.h> 68#include <linux/delay.h> 69#include <linux/sound.h> 70#include <linux/slab.h> 71#include <linux/soundcard.h> 72#include <linux/ac97_codec.h> 73#include <linux/pci.h> 74#include <linux/bitops.h> 75#include <linux/interrupt.h> 76#include <linux/init.h> 77#include <linux/poll.h> 78#include <linux/mutex.h> 79#include <linux/kernel.h> 80 81#include <asm/byteorder.h> 82#include <asm/dma.h> 83#include <asm/io.h> 84#include <asm/uaccess.h> 85 86#include <asm/sibyte/sb1250_regs.h> 87#include <asm/sibyte/sb1250_int.h> 88#include <asm/sibyte/sb1250_dma.h> 89#include <asm/sibyte/sb1250_scd.h> 90#include <asm/sibyte/sb1250_syncser.h> 91#include <asm/sibyte/sb1250_mac.h> 92#include <asm/sibyte/sb1250.h> 93 94struct cs4297a_state; 95 96static void stop_dac(struct cs4297a_state *s); 97static void stop_adc(struct cs4297a_state *s); 98static void start_dac(struct cs4297a_state *s); 99static void start_adc(struct cs4297a_state *s); 100#undef OSS_DOCUMENTED_MIXER_SEMANTICS 101 102// --------------------------------------------------------------------- 103 104#define CS4297a_MAGIC 0xf00beef1 105 106// buffer order determines the size of the dma buffer for the driver. 107// under Linux, a smaller buffer allows more responsiveness from many of the 108// applications (e.g. games). A larger buffer allows some of the apps (esound) 109// to not underrun the dma buffer as easily. As default, use 32k (order=3) 110// rather than 64k as some of the games work more responsively. 111// log base 2( buff sz = 32k). 112 113//static unsigned long defaultorder = 3; 114//MODULE_PARM(defaultorder, "i"); 115 116// 117// Turn on/off debugging compilation by commenting out "#define CSDEBUG" 118// 119#define CSDEBUG 0 120#if CSDEBUG 121#define CSDEBUG_INTERFACE 1 122#else 123#undef CSDEBUG_INTERFACE 124#endif 125// 126// cs_debugmask areas 127// 128#define CS_INIT 0x00000001 // initialization and probe functions 129#define CS_ERROR 0x00000002 // tmp debugging bit placeholder 130#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other) 131#define CS_FUNCTION 0x00000008 // enter/leave functions 132#define CS_WAVE_WRITE 0x00000010 // write information for wave 133#define CS_WAVE_READ 0x00000020 // read information for wave 134#define CS_AC97 0x00000040 // AC97 register access 135#define CS_DESCR 0x00000080 // descriptor management 136#define CS_OPEN 0x00000400 // all open functions in the driver 137#define CS_RELEASE 0x00000800 // all release functions in the driver 138#define CS_PARMS 0x00001000 // functional and operational parameters 139#define CS_IOCTL 0x00002000 // ioctl (non-mixer) 140#define CS_TMP 0x10000000 // tmp debug mask bit 141 142// 143// CSDEBUG is usual mode is set to 1, then use the 144// cs_debuglevel and cs_debugmask to turn on or off debugging. 145// Debug level of 1 has been defined to be kernel errors and info 146// that should be printed on any released driver. 147// 148#if CSDEBUG 149#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;} 150#else 151#define CS_DBGOUT(mask,level,x) 152#endif 153 154#if CSDEBUG 155static unsigned long cs_debuglevel = 4; // levels range from 1-9 156static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/; 157module_param(cs_debuglevel, int, 0); 158module_param(cs_debugmask, int, 0); 159#endif 160#define CS_TRUE 1 161#define CS_FALSE 0 162 163#define CS_TYPE_ADC 0 164#define CS_TYPE_DAC 1 165 166#define SER_BASE (A_SER_BASE_1 + KSEG1) 167#define SS_CSR(t) (SER_BASE+t) 168#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8)) 169#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8)) 170 171#define FRAME_BYTES 32 172#define FRAME_SAMPLE_BYTES 4 173 174/* Should this be variable? */ 175#define SAMPLE_BUF_SIZE (16*1024) 176#define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES) 177/* The driver can explode/shrink the frames to/from a smaller sample 178 buffer */ 179#define DMA_BLOAT_FACTOR 1 180#define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR) 181#define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES) 182 183/* Use the maxmium count (255 == 5.1 ms between interrupts) */ 184#define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1) 185 186/* Figure this out: how many TX DMAs ahead to schedule a reg access */ 187#define REG_LATENCY 150 188 189#define FRAME_TX_US 20 190 191#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz) 192 193static const char invalid_magic[] = 194 KERN_CRIT "cs4297a: invalid magic value\n"; 195 196#define VALIDATE_STATE(s) \ 197({ \ 198 if (!(s) || (s)->magic != CS4297a_MAGIC) { \ 199 printk(invalid_magic); \ 200 return -ENXIO; \ 201 } \ 202}) 203 204struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs }; 205 206typedef struct serdma_descr_s { 207 u64 descr_a; 208 u64 descr_b; 209} serdma_descr_t; 210 211typedef unsigned long paddr_t; 212 213typedef struct serdma_s { 214 unsigned ringsz; 215 serdma_descr_t *descrtab; 216 serdma_descr_t *descrtab_end; 217 paddr_t descrtab_phys; 218 219 serdma_descr_t *descr_add; 220 serdma_descr_t *descr_rem; 221 222 u64 *dma_buf; // buffer for DMA contents (frames) 223 paddr_t dma_buf_phys; 224 u16 *sample_buf; // tmp buffer for sample conversions 225 u16 *sb_swptr; 226 u16 *sb_hwptr; 227 u16 *sb_end; 228 229 dma_addr_t dmaaddr; 230// unsigned buforder; // Log base 2 of 'dma_buf' size in bytes.. 231 unsigned numfrag; // # of 'fragments' in the buffer. 232 unsigned fragshift; // Log base 2 of fragment size. 233 unsigned hwptr, swptr; 234 unsigned total_bytes; // # bytes process since open. 235 unsigned blocks; // last returned blocks value GETOPTR 236 unsigned wakeup; // interrupt occurred on block 237 int count; 238 unsigned underrun; // underrun flag 239 unsigned error; // over/underrun 240 wait_queue_head_t wait; 241 wait_queue_head_t reg_wait; 242 // redundant, but makes calculations easier 243 unsigned fragsize; // 2**fragshift.. 244 unsigned sbufsz; // 2**buforder. 245 unsigned fragsamples; 246 // OSS stuff 247 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()? 248 unsigned ready:1; // prog_dmabuf_dac()/adc() successful? 249 unsigned endcleared:1; 250 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX) 251 unsigned ossfragshift; 252 int ossmaxfrags; 253 unsigned subdivision; 254} serdma_t; 255 256struct cs4297a_state { 257 // magic 258 unsigned int magic; 259 260 struct list_head list; 261 262 // soundcore stuff 263 int dev_audio; 264 int dev_mixer; 265 266 // hardware resources 267 unsigned int irq; 268 269 struct { 270 unsigned int rx_ovrrn; /* FIFO */ 271 unsigned int rx_overflow; /* staging buffer */ 272 unsigned int tx_underrun; 273 unsigned int rx_bad; 274 unsigned int rx_good; 275 } stats; 276 277 // mixer registers 278 struct { 279 unsigned short vol[10]; 280 unsigned int recsrc; 281 unsigned int modcnt; 282 unsigned short micpreamp; 283 } mix; 284 285 // wave stuff 286 struct properties { 287 unsigned fmt; 288 unsigned fmt_original; // original requested format 289 unsigned channels; 290 unsigned rate; 291 } prop_dac, prop_adc; 292 unsigned conversion:1; // conversion from 16 to 8 bit in progress 293 unsigned ena; 294 spinlock_t lock; 295 struct mutex open_mutex; 296 struct mutex open_sem_adc; 297 struct mutex open_sem_dac; 298 mode_t open_mode; 299 wait_queue_head_t open_wait; 300 wait_queue_head_t open_wait_adc; 301 wait_queue_head_t open_wait_dac; 302 303 dma_addr_t dmaaddr_sample_buf; 304 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes.. 305 306 serdma_t dma_dac, dma_adc; 307 308 volatile u16 read_value; 309 volatile u16 read_reg; 310 volatile u64 reg_request; 311}; 312 313#define prog_codec(a,b) 314#define dealloc_dmabuf(a,b); 315 316static int prog_dmabuf_adc(struct cs4297a_state *s) 317{ 318 s->dma_adc.ready = 1; 319 return 0; 320} 321 322 323static int prog_dmabuf_dac(struct cs4297a_state *s) 324{ 325 s->dma_dac.ready = 1; 326 return 0; 327} 328 329static void clear_advance(void *buf, unsigned bsize, unsigned bptr, 330 unsigned len, unsigned char c) 331{ 332 if (bptr + len > bsize) { 333 unsigned x = bsize - bptr; 334 memset(((char *) buf) + bptr, c, x); 335 bptr = 0; 336 len -= x; 337 } 338 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 339 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n", 340 (unsigned)c, (unsigned)((char *) buf) + bptr, len)); 341 memset(((char *) buf) + bptr, c, len); 342} 343 344#if CSDEBUG 345 346// DEBUG ROUTINES 347 348#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int) 349#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int) 350#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int) 351#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int) 352 353static void cs_printioctl(unsigned int x) 354{ 355 unsigned int i; 356 unsigned char vidx; 357 // Index of mixtable1[] member is Device ID 358 // and must be <= SOUND_MIXER_NRDEVICES. 359 // Value of array member is index into s->mix.vol[] 360 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 361 [SOUND_MIXER_PCM] = 1, // voice 362 [SOUND_MIXER_LINE1] = 2, // AUX 363 [SOUND_MIXER_CD] = 3, // CD 364 [SOUND_MIXER_LINE] = 4, // Line 365 [SOUND_MIXER_SYNTH] = 5, // FM 366 [SOUND_MIXER_MIC] = 6, // Mic 367 [SOUND_MIXER_SPEAKER] = 7, // Speaker 368 [SOUND_MIXER_RECLEV] = 8, // Recording level 369 [SOUND_MIXER_VOLUME] = 9 // Master Volume 370 }; 371 372 switch (x) { 373 case SOUND_MIXER_CS_GETDBGMASK: 374 CS_DBGOUT(CS_IOCTL, 4, 375 printk("SOUND_MIXER_CS_GETDBGMASK:\n")); 376 break; 377 case SOUND_MIXER_CS_GETDBGLEVEL: 378 CS_DBGOUT(CS_IOCTL, 4, 379 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n")); 380 break; 381 case SOUND_MIXER_CS_SETDBGMASK: 382 CS_DBGOUT(CS_IOCTL, 4, 383 printk("SOUND_MIXER_CS_SETDBGMASK:\n")); 384 break; 385 case SOUND_MIXER_CS_SETDBGLEVEL: 386 CS_DBGOUT(CS_IOCTL, 4, 387 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n")); 388 break; 389 case OSS_GETVERSION: 390 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n")); 391 break; 392 case SNDCTL_DSP_SYNC: 393 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n")); 394 break; 395 case SNDCTL_DSP_SETDUPLEX: 396 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n")); 397 break; 398 case SNDCTL_DSP_GETCAPS: 399 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n")); 400 break; 401 case SNDCTL_DSP_RESET: 402 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n")); 403 break; 404 case SNDCTL_DSP_SPEED: 405 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n")); 406 break; 407 case SNDCTL_DSP_STEREO: 408 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n")); 409 break; 410 case SNDCTL_DSP_CHANNELS: 411 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n")); 412 break; 413 case SNDCTL_DSP_GETFMTS: 414 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n")); 415 break; 416 case SNDCTL_DSP_SETFMT: 417 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n")); 418 break; 419 case SNDCTL_DSP_POST: 420 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n")); 421 break; 422 case SNDCTL_DSP_GETTRIGGER: 423 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n")); 424 break; 425 case SNDCTL_DSP_SETTRIGGER: 426 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n")); 427 break; 428 case SNDCTL_DSP_GETOSPACE: 429 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n")); 430 break; 431 case SNDCTL_DSP_GETISPACE: 432 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n")); 433 break; 434 case SNDCTL_DSP_NONBLOCK: 435 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n")); 436 break; 437 case SNDCTL_DSP_GETODELAY: 438 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n")); 439 break; 440 case SNDCTL_DSP_GETIPTR: 441 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n")); 442 break; 443 case SNDCTL_DSP_GETOPTR: 444 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n")); 445 break; 446 case SNDCTL_DSP_GETBLKSIZE: 447 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n")); 448 break; 449 case SNDCTL_DSP_SETFRAGMENT: 450 CS_DBGOUT(CS_IOCTL, 4, 451 printk("SNDCTL_DSP_SETFRAGMENT:\n")); 452 break; 453 case SNDCTL_DSP_SUBDIVIDE: 454 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n")); 455 break; 456 case SOUND_PCM_READ_RATE: 457 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n")); 458 break; 459 case SOUND_PCM_READ_CHANNELS: 460 CS_DBGOUT(CS_IOCTL, 4, 461 printk("SOUND_PCM_READ_CHANNELS:\n")); 462 break; 463 case SOUND_PCM_READ_BITS: 464 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n")); 465 break; 466 case SOUND_PCM_WRITE_FILTER: 467 CS_DBGOUT(CS_IOCTL, 4, 468 printk("SOUND_PCM_WRITE_FILTER:\n")); 469 break; 470 case SNDCTL_DSP_SETSYNCRO: 471 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n")); 472 break; 473 case SOUND_PCM_READ_FILTER: 474 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n")); 475 break; 476 case SOUND_MIXER_PRIVATE1: 477 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n")); 478 break; 479 case SOUND_MIXER_PRIVATE2: 480 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n")); 481 break; 482 case SOUND_MIXER_PRIVATE3: 483 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n")); 484 break; 485 case SOUND_MIXER_PRIVATE4: 486 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n")); 487 break; 488 case SOUND_MIXER_PRIVATE5: 489 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n")); 490 break; 491 case SOUND_MIXER_INFO: 492 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n")); 493 break; 494 case SOUND_OLD_MIXER_INFO: 495 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n")); 496 break; 497 498 default: 499 switch (_IOC_NR(x)) { 500 case SOUND_MIXER_VOLUME: 501 CS_DBGOUT(CS_IOCTL, 4, 502 printk("SOUND_MIXER_VOLUME:\n")); 503 break; 504 case SOUND_MIXER_SPEAKER: 505 CS_DBGOUT(CS_IOCTL, 4, 506 printk("SOUND_MIXER_SPEAKER:\n")); 507 break; 508 case SOUND_MIXER_RECLEV: 509 CS_DBGOUT(CS_IOCTL, 4, 510 printk("SOUND_MIXER_RECLEV:\n")); 511 break; 512 case SOUND_MIXER_MIC: 513 CS_DBGOUT(CS_IOCTL, 4, 514 printk("SOUND_MIXER_MIC:\n")); 515 break; 516 case SOUND_MIXER_SYNTH: 517 CS_DBGOUT(CS_IOCTL, 4, 518 printk("SOUND_MIXER_SYNTH:\n")); 519 break; 520 case SOUND_MIXER_RECSRC: 521 CS_DBGOUT(CS_IOCTL, 4, 522 printk("SOUND_MIXER_RECSRC:\n")); 523 break; 524 case SOUND_MIXER_DEVMASK: 525 CS_DBGOUT(CS_IOCTL, 4, 526 printk("SOUND_MIXER_DEVMASK:\n")); 527 break; 528 case SOUND_MIXER_RECMASK: 529 CS_DBGOUT(CS_IOCTL, 4, 530 printk("SOUND_MIXER_RECMASK:\n")); 531 break; 532 case SOUND_MIXER_STEREODEVS: 533 CS_DBGOUT(CS_IOCTL, 4, 534 printk("SOUND_MIXER_STEREODEVS:\n")); 535 break; 536 case SOUND_MIXER_CAPS: 537 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n")); 538 break; 539 default: 540 i = _IOC_NR(x); 541 if (i >= SOUND_MIXER_NRDEVICES 542 || !(vidx = mixtable1[i])) { 543 CS_DBGOUT(CS_IOCTL, 4, printk 544 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n", 545 x, i)); 546 } else { 547 CS_DBGOUT(CS_IOCTL, 4, printk 548 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n", 549 x, i)); 550 } 551 break; 552 } 553 } 554} 555#endif 556 557 558static int ser_init(struct cs4297a_state *s) 559{ 560 int i; 561 562 CS_DBGOUT(CS_INIT, 2, 563 printk(KERN_INFO "cs4297a: Setting up serial parameters\n")); 564 565 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); 566 567 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); 568 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ)); 569 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ)); 570 571 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH)); 572 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH)); 573 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH)); 574 575 /* This looks good from experimentation */ 576 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT | 577 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE), 578 SS_CSR(R_SER_LINE_MODE)); 579 580 /* This looks good from experimentation */ 581 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 582 SS_TXTBL(0)); 583 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 584 SS_TXTBL(1)); 585 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 586 SS_TXTBL(2)); 587 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | 588 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3)); 589 590 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 591 SS_RXTBL(0)); 592 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 593 SS_RXTBL(1)); 594 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 595 SS_RXTBL(2)); 596 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | 597 M_SYNCSER_SEQ_LAST, SS_RXTBL(3)); 598 599 for (i=4; i<16; i++) { 600 /* Just in case... */ 601 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i)); 602 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i)); 603 } 604 605 return 0; 606} 607 608static int init_serdma(serdma_t *dma) 609{ 610 CS_DBGOUT(CS_INIT, 2, 611 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n", 612 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE)); 613 614 /* Descriptors */ 615 dma->ringsz = DMA_DESCR; 616 dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL); 617 if (!dma->descrtab) { 618 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n"); 619 return -1; 620 } 621 dma->descrtab_end = dma->descrtab + dma->ringsz; 622 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab); 623 dma->descr_add = dma->descr_rem = dma->descrtab; 624 625 /* Frame buffer area */ 626 dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL); 627 if (!dma->dma_buf) { 628 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n"); 629 kfree(dma->descrtab); 630 return -1; 631 } 632 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf); 633 634 /* Samples buffer area */ 635 dma->sbufsz = SAMPLE_BUF_SIZE; 636 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL); 637 if (!dma->sample_buf) { 638 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n"); 639 kfree(dma->descrtab); 640 kfree(dma->dma_buf); 641 return -1; 642 } 643 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf; 644 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz); 645 dma->fragsize = dma->sbufsz >> 1; 646 647 CS_DBGOUT(CS_INIT, 4, 648 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n", 649 (int)dma->descrtab, (int)dma->dma_buf, 650 (int)dma->sample_buf)); 651 652 return 0; 653} 654 655static int dma_init(struct cs4297a_state *s) 656{ 657 int i; 658 659 CS_DBGOUT(CS_INIT, 2, 660 printk(KERN_INFO "cs4297a: Setting up DMA\n")); 661 662 if (init_serdma(&s->dma_adc) || 663 init_serdma(&s->dma_dac)) 664 return -1; 665 666 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| 667 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { 668 panic("DMA state corrupted?!"); 669 } 670 671 /* Initialize now - the descr/buffer pairings will never 672 change... */ 673 for (i=0; i<DMA_DESCR; i++) { 674 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) | 675 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES); 676 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES); 677 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) | 678 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES); 679 s->dma_adc.descrtab[i].descr_b = 0; 680 } 681 682 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) | 683 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN), 684 SS_CSR(R_SER_DMA_CONFIG0_RX)); 685 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); 686 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); 687 688 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); 689 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); 690 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); 691 692 /* Prep the receive DMA descriptor ring */ 693 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 694 695 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); 696 697 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT), 698 SS_CSR(R_SER_INT_MASK)); 699 700 /* Enable the rx/tx; let the codec warm up to the sync and 701 start sending good frames before the receive FIFO is 702 enabled */ 703 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 704 udelay(1000); 705 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 706 707 /* XXXKW is this magic? (the "1" part) */ 708 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) 709 ; 710 711 CS_DBGOUT(CS_INIT, 4, 712 printk(KERN_INFO "cs4297a: status: %08x\n", 713 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff))); 714 715 return 0; 716} 717 718static int serdma_reg_access(struct cs4297a_state *s, u64 data) 719{ 720 serdma_t *d = &s->dma_dac; 721 u64 *data_p; 722 unsigned swptr; 723 unsigned long flags; 724 serdma_descr_t *descr; 725 726 if (s->reg_request) { 727 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n"); 728 return -1; 729 } 730 731 if (s->ena & FMODE_WRITE) { 732 /* Since a writer has the DSP open, we have to mux the 733 request in */ 734 s->reg_request = data; 735 interruptible_sleep_on(&s->dma_dac.reg_wait); 736 /* XXXKW how can I deal with the starvation case where 737 the opener isn't writing? */ 738 } else { 739 /* Be safe when changing ring pointers */ 740 spin_lock_irqsave(&s->lock, flags); 741 if (d->hwptr != d->swptr) { 742 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n", 743 d->hwptr, d->swptr); 744 spin_unlock_irqrestore(&s->lock, flags); 745 return -1; 746 } 747 swptr = d->swptr; 748 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz; 749 spin_unlock_irqrestore(&s->lock, flags); 750 751 descr = &d->descrtab[swptr]; 752 data_p = &d->dma_buf[swptr * 4]; 753 *data_p = cpu_to_be64(data); 754 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 755 CS_DBGOUT(CS_DESCR, 4, 756 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n", 757 data_p, swptr, d->hwptr)); 758 } 759 760 CS_DBGOUT(CS_FUNCTION, 6, 761 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n")); 762 763 return 0; 764} 765 766//**************************************************************************** 767// "cs4297a_read_ac97" -- Reads an AC97 register 768//**************************************************************************** 769static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset, 770 u32 * value) 771{ 772 CS_DBGOUT(CS_AC97, 1, 773 printk(KERN_INFO "cs4297a: read reg %2x\n", offset)); 774 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40))) 775 return -1; 776 777 interruptible_sleep_on(&s->dma_adc.reg_wait); 778 *value = s->read_value; 779 CS_DBGOUT(CS_AC97, 2, 780 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value)); 781 782 return 0; 783} 784 785 786//**************************************************************************** 787// "cs4297a_write_ac97()"-- writes an AC97 register 788//**************************************************************************** 789static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset, 790 u32 value) 791{ 792 CS_DBGOUT(CS_AC97, 1, 793 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value)); 794 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12))); 795} 796 797static void stop_dac(struct cs4297a_state *s) 798{ 799 unsigned long flags; 800 801 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n")); 802 spin_lock_irqsave(&s->lock, flags); 803 s->ena &= ~FMODE_WRITE; 804 805 spin_unlock_irqrestore(&s->lock, flags); 806} 807 808 809static void start_dac(struct cs4297a_state *s) 810{ 811 unsigned long flags; 812 813 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n")); 814 spin_lock_irqsave(&s->lock, flags); 815 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || 816 (s->dma_dac.count > 0 817 && s->dma_dac.ready))) { 818 s->ena |= FMODE_WRITE; 819 /* XXXKW what do I really want here? My theory for 820 now is that I just flip the "ena" bit, and the 821 interrupt handler will start processing the xmit 822 channel */ 823 824 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO 825 "cs4297a: start_dac(): start dma\n")); 826 827 } 828 spin_unlock_irqrestore(&s->lock, flags); 829 CS_DBGOUT(CS_FUNCTION, 3, 830 printk(KERN_INFO "cs4297a: start_dac()-\n")); 831} 832 833 834static void stop_adc(struct cs4297a_state *s) 835{ 836 unsigned long flags; 837 838 CS_DBGOUT(CS_FUNCTION, 3, 839 printk(KERN_INFO "cs4297a: stop_adc()+\n")); 840 841 spin_lock_irqsave(&s->lock, flags); 842 s->ena &= ~FMODE_READ; 843 844 if (s->conversion == 1) { 845 s->conversion = 0; 846 s->prop_adc.fmt = s->prop_adc.fmt_original; 847 } 848 /* Nothing to do really, I need to keep the DMA going 849 XXXKW when do I get here, and is there more I should do? */ 850 spin_unlock_irqrestore(&s->lock, flags); 851 CS_DBGOUT(CS_FUNCTION, 3, 852 printk(KERN_INFO "cs4297a: stop_adc()-\n")); 853} 854 855 856static void start_adc(struct cs4297a_state *s) 857{ 858 unsigned long flags; 859 860 CS_DBGOUT(CS_FUNCTION, 2, 861 printk(KERN_INFO "cs4297a: start_adc()+\n")); 862 863 if (!(s->ena & FMODE_READ) && 864 (s->dma_adc.mapped || s->dma_adc.count <= 865 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize)) 866 && s->dma_adc.ready) { 867 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) { 868 // 869 // now only use 16 bit capture, due to truncation issue 870 // in the chip, noticable distortion occurs. 871 // allocate buffer and then convert from 16 bit to 872 // 8 bit for the user buffer. 873 // 874 s->prop_adc.fmt_original = s->prop_adc.fmt; 875 if (s->prop_adc.fmt & AFMT_S8) { 876 s->prop_adc.fmt &= ~AFMT_S8; 877 s->prop_adc.fmt |= AFMT_S16_LE; 878 } 879 if (s->prop_adc.fmt & AFMT_U8) { 880 s->prop_adc.fmt &= ~AFMT_U8; 881 s->prop_adc.fmt |= AFMT_U16_LE; 882 } 883 // 884 // prog_dmabuf_adc performs a stop_adc() but that is 885 // ok since we really haven't started the DMA yet. 886 // 887 prog_codec(s, CS_TYPE_ADC); 888 889 prog_dmabuf_adc(s); 890 s->conversion = 1; 891 } 892 spin_lock_irqsave(&s->lock, flags); 893 s->ena |= FMODE_READ; 894 /* Nothing to do really, I am probably already 895 DMAing... XXXKW when do I get here, and is there 896 more I should do? */ 897 spin_unlock_irqrestore(&s->lock, flags); 898 899 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO 900 "cs4297a: start_adc(): start adc\n")); 901 } 902 CS_DBGOUT(CS_FUNCTION, 2, 903 printk(KERN_INFO "cs4297a: start_adc()-\n")); 904 905} 906 907 908// call with spinlock held! 909static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag) 910{ 911 int good_diff, diff, diff2; 912 u64 *data_p, data; 913 u32 *s_ptr; 914 unsigned hwptr; 915 u32 status; 916 serdma_t *d; 917 serdma_descr_t *descr; 918 919 // update ADC pointer 920 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0; 921 922 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) { 923 d = &s->dma_adc; 924 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 925 d->descrtab_phys) / sizeof(serdma_descr_t)); 926 927 if (s->ena & FMODE_READ) { 928 CS_DBGOUT(CS_FUNCTION, 2, 929 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n", 930 d->swptr, d->hwptr, hwptr, intflag)); 931 /* Number of DMA buffers available for software: */ 932 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 933 d->hwptr = hwptr; 934 good_diff = 0; 935 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]); 936 descr = &d->descrtab[d->swptr]; 937 while (diff2--) { 938 u64 data = be64_to_cpu(*(u64 *)s_ptr); 939 u64 descr_a; 940 u16 left, right; 941 descr_a = descr->descr_a; 942 descr->descr_a &= ~M_DMA_SERRX_SOP; 943 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) { 944 printk(KERN_ERR "cs4297a: RX Bad address (read)\n"); 945 } 946 if (((data & 0x9800000000000000) != 0x9800000000000000) || 947 (!(descr_a & M_DMA_SERRX_SOP)) || 948 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 949 s->stats.rx_bad++; 950 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n"); 951 continue; 952 } 953 s->stats.rx_good++; 954 if ((data >> 61) == 7) { 955 s->read_value = (data >> 12) & 0xffff; 956 s->read_reg = (data >> 40) & 0x7f; 957 wake_up(&d->reg_wait); 958 } 959 if (d->count && (d->sb_hwptr == d->sb_swptr)) { 960 s->stats.rx_overflow++; 961 printk(KERN_DEBUG "cs4297a: RX overflow\n"); 962 continue; 963 } 964 good_diff++; 965 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) | 966 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff); 967 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff; 968 *d->sb_hwptr++ = cpu_to_be16(left); 969 *d->sb_hwptr++ = cpu_to_be16(right); 970 if (d->sb_hwptr == d->sb_end) 971 d->sb_hwptr = d->sample_buf; 972 descr++; 973 if (descr == d->descrtab_end) { 974 descr = d->descrtab; 975 s_ptr = (u32 *)s->dma_adc.dma_buf; 976 } else { 977 s_ptr += 8; 978 } 979 } 980 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES; 981 d->count += good_diff * FRAME_SAMPLE_BYTES; 982 if (d->count > d->sbufsz) { 983 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n"); 984 } 985 d->swptr = (d->swptr + diff) % d->ringsz; 986 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 987 if (d->mapped) { 988 if (d->count >= (signed) d->fragsize) 989 wake_up(&d->wait); 990 } else { 991 if (d->count > 0) { 992 CS_DBGOUT(CS_WAVE_READ, 4, 993 printk(KERN_INFO 994 "cs4297a: update count -> %d\n", d->count)); 995 wake_up(&d->wait); 996 } 997 } 998 } else { 999 /* Receive is going even if no one is 1000 listening (for register accesses and to 1001 avoid FIFO overrun) */ 1002 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz; 1003 if (!diff) { 1004 printk(KERN_ERR "cs4297a: RX full or empty?\n"); 1005 } 1006 1007 descr = &d->descrtab[d->swptr]; 1008 data_p = &d->dma_buf[d->swptr*4]; 1009 1010 /* Force this to happen at least once; I got 1011 here because of an interrupt, so there must 1012 be a buffer to process. */ 1013 do { 1014 data = be64_to_cpu(*data_p); 1015 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) { 1016 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr, 1017 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR), 1018 (long)CPHYSADDR((long)data_p)); 1019 } 1020 if (!(data & (1LL << 63)) || 1021 !(descr->descr_a & M_DMA_SERRX_SOP) || 1022 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 1023 s->stats.rx_bad++; 1024 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n"); 1025 } else { 1026 s->stats.rx_good++; 1027 if ((data >> 61) == 7) { 1028 s->read_value = (data >> 12) & 0xffff; 1029 s->read_reg = (data >> 40) & 0x7f; 1030 wake_up(&d->reg_wait); 1031 } 1032 } 1033 descr->descr_a &= ~M_DMA_SERRX_SOP; 1034 descr++; 1035 d->swptr++; 1036 data_p += 4; 1037 if (descr == d->descrtab_end) { 1038 descr = d->descrtab; 1039 d->swptr = 0; 1040 data_p = d->dma_buf; 1041 } 1042 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 1043 } while (--diff); 1044 d->hwptr = hwptr; 1045 1046 CS_DBGOUT(CS_DESCR, 6, 1047 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr)); 1048 } 1049 1050 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1051 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1052 (unsigned)s, d->hwptr, 1053 d->total_bytes, d->count)); 1054 } 1055 1056 /* XXXKW worry about s->reg_request -- there is a starvation 1057 case if s->ena has FMODE_WRITE on, but the client isn't 1058 doing writes */ 1059 1060 // update DAC pointer 1061 // 1062 // check for end of buffer, means that we are going to wait for another interrupt 1063 // to allow silence to fill the fifos on the part, to keep pops down to a minimum. 1064 // 1065 if (s->ena & FMODE_WRITE) { 1066 serdma_t *d = &s->dma_dac; 1067 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1068 d->descrtab_phys) / sizeof(serdma_descr_t)); 1069 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 1070 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 1071 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n", 1072 d->hwptr, hwptr, d->swptr, diff, d->count)); 1073 d->hwptr = hwptr; 1074 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */ 1075 d->total_bytes += diff * FRAME_SAMPLE_BYTES; 1076 if (d->mapped) { 1077 d->count += diff * FRAME_SAMPLE_BYTES; 1078 if (d->count >= d->fragsize) { 1079 d->wakeup = 1; 1080 wake_up(&d->wait); 1081 if (d->count > d->sbufsz) 1082 d->count &= d->sbufsz - 1; 1083 } 1084 } else { 1085 d->count -= diff * FRAME_SAMPLE_BYTES; 1086 if (d->count <= 0) { 1087 // 1088 // fill with silence, and do not shut down the DAC. 1089 // Continue to play silence until the _release. 1090 // 1091 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO 1092 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n", 1093 (unsigned)(s->prop_dac.fmt & 1094 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 1095 (unsigned)d->dma_buf, 1096 d->ringsz)); 1097 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES); 1098 if (d->count < 0) { 1099 d->underrun = 1; 1100 s->stats.tx_underrun++; 1101 d->count = 0; 1102 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO 1103 "cs4297a: cs4297a_update_ptr(): underrun\n")); 1104 } 1105 } else if (d->count <= 1106 (signed) d->fragsize 1107 && !d->endcleared) { 1108 /* XXXKW what is this for? */ 1109 clear_advance(d->dma_buf, 1110 d->sbufsz, 1111 d->swptr, 1112 d->fragsize, 1113 0); 1114 d->endcleared = 1; 1115 } 1116 if ( (d->count <= (signed) d->sbufsz/2) || intflag) 1117 { 1118 CS_DBGOUT(CS_WAVE_WRITE, 4, 1119 printk(KERN_INFO 1120 "cs4297a: update count -> %d\n", d->count)); 1121 wake_up(&d->wait); 1122 } 1123 } 1124 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1125 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1126 (unsigned) s, d->hwptr, 1127 d->total_bytes, d->count)); 1128 } 1129} 1130 1131static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd, 1132 unsigned long arg) 1133{ 1134 // Index to mixer_src[] is value of AC97 Input Mux Select Reg. 1135 // Value of array member is recording source Device ID Mask. 1136 static const unsigned int mixer_src[8] = { 1137 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1, 1138 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0 1139 }; 1140 1141 // Index of mixtable1[] member is Device ID 1142 // and must be <= SOUND_MIXER_NRDEVICES. 1143 // Value of array member is index into s->mix.vol[] 1144 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 1145 [SOUND_MIXER_PCM] = 1, // voice 1146 [SOUND_MIXER_LINE1] = 2, // AUX 1147 [SOUND_MIXER_CD] = 3, // CD 1148 [SOUND_MIXER_LINE] = 4, // Line 1149 [SOUND_MIXER_SYNTH] = 5, // FM 1150 [SOUND_MIXER_MIC] = 6, // Mic 1151 [SOUND_MIXER_SPEAKER] = 7, // Speaker 1152 [SOUND_MIXER_RECLEV] = 8, // Recording level 1153 [SOUND_MIXER_VOLUME] = 9 // Master Volume 1154 }; 1155 1156 static const unsigned mixreg[] = { 1157 AC97_PCMOUT_VOL, 1158 AC97_AUX_VOL, 1159 AC97_CD_VOL, 1160 AC97_LINEIN_VOL 1161 }; 1162 unsigned char l, r, rl, rr, vidx; 1163 unsigned char attentbl[11] = 1164 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 }; 1165 unsigned temp1; 1166 int i, val; 1167 1168 VALIDATE_STATE(s); 1169 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO 1170 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n", 1171 (unsigned) s, cmd)); 1172#if CSDEBUG 1173 cs_printioctl(cmd); 1174#endif 1175#if CSDEBUG_INTERFACE 1176 1177 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) || 1178 (cmd == SOUND_MIXER_CS_SETDBGMASK) || 1179 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) || 1180 (cmd == SOUND_MIXER_CS_SETDBGLEVEL)) 1181 { 1182 switch (cmd) { 1183 1184 case SOUND_MIXER_CS_GETDBGMASK: 1185 return put_user(cs_debugmask, 1186 (unsigned long *) arg); 1187 1188 case SOUND_MIXER_CS_GETDBGLEVEL: 1189 return put_user(cs_debuglevel, 1190 (unsigned long *) arg); 1191 1192 case SOUND_MIXER_CS_SETDBGMASK: 1193 if (get_user(val, (unsigned long *) arg)) 1194 return -EFAULT; 1195 cs_debugmask = val; 1196 return 0; 1197 1198 case SOUND_MIXER_CS_SETDBGLEVEL: 1199 if (get_user(val, (unsigned long *) arg)) 1200 return -EFAULT; 1201 cs_debuglevel = val; 1202 return 0; 1203 default: 1204 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO 1205 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n")); 1206 return 0; 1207 } 1208 } 1209#endif 1210 1211 if (cmd == SOUND_MIXER_PRIVATE1) { 1212 return -EINVAL; 1213 } 1214 if (cmd == SOUND_MIXER_PRIVATE2) { 1215 // enable/disable/query spatializer 1216 if (get_user(val, (int *) arg)) 1217 return -EFAULT; 1218 if (val != -1) { 1219 temp1 = (val & 0x3f) >> 2; 1220 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1); 1221 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE, 1222 &temp1); 1223 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE, 1224 temp1 | 0x2000); 1225 } 1226 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1); 1227 return put_user((temp1 << 2) | 3, (int *) arg); 1228 } 1229 if (cmd == SOUND_MIXER_INFO) { 1230 mixer_info info; 1231 memset(&info, 0, sizeof(info)); 1232 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1233 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1234 info.modify_counter = s->mix.modcnt; 1235 if (copy_to_user((void *) arg, &info, sizeof(info))) 1236 return -EFAULT; 1237 return 0; 1238 } 1239 if (cmd == SOUND_OLD_MIXER_INFO) { 1240 _old_mixer_info info; 1241 memset(&info, 0, sizeof(info)); 1242 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1243 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1244 if (copy_to_user((void *) arg, &info, sizeof(info))) 1245 return -EFAULT; 1246 return 0; 1247 } 1248 if (cmd == OSS_GETVERSION) 1249 return put_user(SOUND_VERSION, (int *) arg); 1250 1251 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) 1252 return -EINVAL; 1253 1254 // If ioctl has only the SIOC_READ bit(bit 31) 1255 // on, process the only-read commands. 1256 if (_SIOC_DIR(cmd) == _SIOC_READ) { 1257 switch (_IOC_NR(cmd)) { 1258 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1259 cs4297a_read_ac97(s, AC97_RECORD_SELECT, 1260 &temp1); 1261 return put_user(mixer_src[temp1 & 7], (int *) arg); 1262 1263 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device 1264 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1265 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1266 (int *) arg); 1267 1268 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source 1269 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME, 1270 (int *) arg); 1271 1272 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo 1273 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1274 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1275 (int *) arg); 1276 1277 case SOUND_MIXER_CAPS: 1278 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg); 1279 1280 default: 1281 i = _IOC_NR(cmd); 1282 if (i >= SOUND_MIXER_NRDEVICES 1283 || !(vidx = mixtable1[i])) 1284 return -EINVAL; 1285 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1286 } 1287 } 1288 // If ioctl doesn't have both the SIOC_READ and 1289 // the SIOC_WRITE bit set, return invalid. 1290 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE)) 1291 return -EINVAL; 1292 1293 // Increment the count of volume writes. 1294 s->mix.modcnt++; 1295 1296 // Isolate the command; it must be a write. 1297 switch (_IOC_NR(cmd)) { 1298 1299 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1300 if (get_user(val, (int *) arg)) 1301 return -EFAULT; 1302 i = hweight32(val); // i = # bits on in val. 1303 if (i != 1) // One & only 1 bit must be on. 1304 return 0; 1305 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) { 1306 if (val == mixer_src[i]) { 1307 temp1 = (i << 8) | i; 1308 cs4297a_write_ac97(s, 1309 AC97_RECORD_SELECT, 1310 temp1); 1311 return 0; 1312 } 1313 } 1314 return 0; 1315 1316 case SOUND_MIXER_VOLUME: 1317 if (get_user(val, (int *) arg)) 1318 return -EFAULT; 1319 l = val & 0xff; 1320 if (l > 100) 1321 l = 100; // Max soundcard.h vol is 100. 1322 if (l < 6) { 1323 rl = 63; 1324 l = 0; 1325 } else 1326 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten. 1327 1328 r = (val >> 8) & 0xff; 1329 if (r > 100) 1330 r = 100; // Max right volume is 100, too 1331 if (r < 6) { 1332 rr = 63; 1333 r = 0; 1334 } else 1335 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation. 1336 1337 if ((rl > 60) && (rr > 60)) // If both l & r are 'low', 1338 temp1 = 0x8000; // turn on the mute bit. 1339 else 1340 temp1 = 0; 1341 1342 temp1 |= (rl << 8) | rr; 1343 1344 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1); 1345 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1); 1346 1347#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1348 s->mix.vol[8] = ((unsigned int) r << 8) | l; 1349#else 1350 s->mix.vol[8] = val; 1351#endif 1352 return put_user(s->mix.vol[8], (int *) arg); 1353 1354 case SOUND_MIXER_SPEAKER: 1355 if (get_user(val, (int *) arg)) 1356 return -EFAULT; 1357 l = val & 0xff; 1358 if (l > 100) 1359 l = 100; 1360 if (l < 3) { 1361 rl = 0; 1362 l = 0; 1363 } else { 1364 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15. 1365 l = (rl * 13 + 5) / 2; 1366 } 1367 1368 if (rl < 3) { 1369 temp1 = 0x8000; 1370 rl = 0; 1371 } else 1372 temp1 = 0; 1373 rl = 15 - rl; // Convert volume to attenuation. 1374 temp1 |= rl << 1; 1375 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1); 1376 1377#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1378 s->mix.vol[6] = l << 8; 1379#else 1380 s->mix.vol[6] = val; 1381#endif 1382 return put_user(s->mix.vol[6], (int *) arg); 1383 1384 case SOUND_MIXER_RECLEV: 1385 if (get_user(val, (int *) arg)) 1386 return -EFAULT; 1387 l = val & 0xff; 1388 if (l > 100) 1389 l = 100; 1390 r = (val >> 8) & 0xff; 1391 if (r > 100) 1392 r = 100; 1393 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15. 1394 rr = (r * 2 - 5) / 13; 1395 if (rl < 3 && rr < 3) 1396 temp1 = 0x8000; 1397 else 1398 temp1 = 0; 1399 1400 temp1 = temp1 | (rl << 8) | rr; 1401 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1); 1402 1403#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1404 s->mix.vol[7] = ((unsigned int) r << 8) | l; 1405#else 1406 s->mix.vol[7] = val; 1407#endif 1408 return put_user(s->mix.vol[7], (int *) arg); 1409 1410 case SOUND_MIXER_MIC: 1411 if (get_user(val, (int *) arg)) 1412 return -EFAULT; 1413 l = val & 0xff; 1414 if (l > 100) 1415 l = 100; 1416 if (l < 1) { 1417 l = 0; 1418 rl = 0; 1419 } else { 1420 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31. 1421 l = (rl * 16 + 4) / 5; 1422 } 1423 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1); 1424 temp1 &= 0x40; // Isolate 20db gain bit. 1425 if (rl < 3) { 1426 temp1 |= 0x8000; 1427 rl = 0; 1428 } 1429 rl = 31 - rl; // Convert volume to attenuation. 1430 temp1 |= rl; 1431 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1); 1432 1433#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1434 s->mix.vol[5] = val << 8; 1435#else 1436 s->mix.vol[5] = val; 1437#endif 1438 return put_user(s->mix.vol[5], (int *) arg); 1439 1440 1441 case SOUND_MIXER_SYNTH: 1442 if (get_user(val, (int *) arg)) 1443 return -EFAULT; 1444 l = val & 0xff; 1445 if (l > 100) 1446 l = 100; 1447 if (get_user(val, (int *) arg)) 1448 return -EFAULT; 1449 r = (val >> 8) & 0xff; 1450 if (r > 100) 1451 r = 100; 1452 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63. 1453 rr = (r * 2 - 11) / 3; 1454 if (rl < 3) // If l is low, turn on 1455 temp1 = 0x0080; // the mute bit. 1456 else 1457 temp1 = 0; 1458 1459 rl = 63 - rl; // Convert vol to attenuation. 1460// writel(temp1 | rl, s->pBA0 + FMLVC); 1461 if (rr < 3) // If rr is low, turn on 1462 temp1 = 0x0080; // the mute bit. 1463 else 1464 temp1 = 0; 1465 rr = 63 - rr; // Convert vol to attenuation. 1466// writel(temp1 | rr, s->pBA0 + FMRVC); 1467 1468#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1469 s->mix.vol[4] = (r << 8) | l; 1470#else 1471 s->mix.vol[4] = val; 1472#endif 1473 return put_user(s->mix.vol[4], (int *) arg); 1474 1475 1476 default: 1477 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1478 "cs4297a: mixer_ioctl(): default\n")); 1479 1480 i = _IOC_NR(cmd); 1481 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i])) 1482 return -EINVAL; 1483 if (get_user(val, (int *) arg)) 1484 return -EFAULT; 1485 l = val & 0xff; 1486 if (l > 100) 1487 l = 100; 1488 if (l < 1) { 1489 l = 0; 1490 rl = 31; 1491 } else 1492 rl = (attentbl[(l * 10) / 100]) >> 1; 1493 1494 r = (val >> 8) & 0xff; 1495 if (r > 100) 1496 r = 100; 1497 if (r < 1) { 1498 r = 0; 1499 rr = 31; 1500 } else 1501 rr = (attentbl[(r * 10) / 100]) >> 1; 1502 if ((rl > 30) && (rr > 30)) 1503 temp1 = 0x8000; 1504 else 1505 temp1 = 0; 1506 temp1 = temp1 | (rl << 8) | rr; 1507 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1); 1508 1509#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1510 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l; 1511#else 1512 s->mix.vol[vidx - 1] = val; 1513#endif 1514 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1515 } 1516} 1517 1518 1519// --------------------------------------------------------------------- 1520 1521static int cs4297a_open_mixdev(struct inode *inode, struct file *file) 1522{ 1523 int minor = iminor(inode); 1524 struct cs4297a_state *s=NULL; 1525 struct list_head *entry; 1526 1527 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1528 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n")); 1529 1530 list_for_each(entry, &cs4297a_devs) 1531 { 1532 s = list_entry(entry, struct cs4297a_state, list); 1533 if(s->dev_mixer == minor) 1534 break; 1535 } 1536 if (!s) 1537 { 1538 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, 1539 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n")); 1540 return -ENODEV; 1541 } 1542 VALIDATE_STATE(s); 1543 file->private_data = s; 1544 1545 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1546 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n")); 1547 1548 return nonseekable_open(inode, file); 1549} 1550 1551 1552static int cs4297a_release_mixdev(struct inode *inode, struct file *file) 1553{ 1554 struct cs4297a_state *s = 1555 (struct cs4297a_state *) file->private_data; 1556 1557 VALIDATE_STATE(s); 1558 return 0; 1559} 1560 1561 1562static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file, 1563 unsigned int cmd, unsigned long arg) 1564{ 1565 return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd, 1566 arg); 1567} 1568 1569 1570// ****************************************************************************************** 1571// Mixer file operations struct. 1572// ****************************************************************************************** 1573static /*const */ struct file_operations cs4297a_mixer_fops = { 1574 .owner = THIS_MODULE, 1575 .llseek = no_llseek, 1576 .ioctl = cs4297a_ioctl_mixdev, 1577 .open = cs4297a_open_mixdev, 1578 .release = cs4297a_release_mixdev, 1579}; 1580 1581// --------------------------------------------------------------------- 1582 1583 1584static int drain_adc(struct cs4297a_state *s, int nonblock) 1585{ 1586 /* This routine serves no purpose currently - any samples 1587 sitting in the receive queue will just be processed by the 1588 background consumer. This would be different if DMA 1589 actually stopped when there were no clients. */ 1590 return 0; 1591} 1592 1593static int drain_dac(struct cs4297a_state *s, int nonblock) 1594{ 1595 DECLARE_WAITQUEUE(wait, current); 1596 unsigned long flags; 1597 unsigned hwptr; 1598 unsigned tmo; 1599 int count; 1600 1601 if (s->dma_dac.mapped) 1602 return 0; 1603 if (nonblock) 1604 return -EBUSY; 1605 add_wait_queue(&s->dma_dac.wait, &wait); 1606 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || 1607 (s->dma_dac.count > 0)) { 1608 if (!signal_pending(current)) { 1609 set_current_state(TASK_INTERRUPTIBLE); 1610 /* XXXKW is this calculation working? */ 1611 tmo = ((count * FRAME_TX_US) * HZ) / 1000000; 1612 schedule_timeout(tmo + 1); 1613 } else { 1614 /* XXXKW do I care if there is a signal pending? */ 1615 } 1616 } 1617 spin_lock_irqsave(&s->lock, flags); 1618 /* Reset the bookkeeping */ 1619 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1620 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 1621 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr; 1622 spin_unlock_irqrestore(&s->lock, flags); 1623 remove_wait_queue(&s->dma_dac.wait, &wait); 1624 current->state = TASK_RUNNING; 1625 return 0; 1626} 1627 1628 1629// --------------------------------------------------------------------- 1630 1631static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count, 1632 loff_t * ppos) 1633{ 1634 struct cs4297a_state *s = 1635 (struct cs4297a_state *) file->private_data; 1636 ssize_t ret; 1637 unsigned long flags; 1638 int cnt, count_fr, cnt_by; 1639 unsigned copied = 0; 1640 1641 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1642 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count)); 1643 1644 VALIDATE_STATE(s); 1645 if (s->dma_adc.mapped) 1646 return -ENXIO; 1647 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) 1648 return ret; 1649 if (!access_ok(VERIFY_WRITE, buffer, count)) 1650 return -EFAULT; 1651 ret = 0; 1652// 1653// "count" is the amount of bytes to read (from app), is decremented each loop 1654// by the amount of bytes that have been returned to the user buffer. 1655// "cnt" is the running total of each read from the buffer (changes each loop) 1656// "buffer" points to the app's buffer 1657// "ret" keeps a running total of the amount of bytes that have been copied 1658// to the user buffer. 1659// "copied" is the total bytes copied into the user buffer for each loop. 1660// 1661 while (count > 0) { 1662 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1663 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n", 1664 count, s->dma_adc.count, 1665 s->dma_adc.swptr, s->dma_adc.hwptr)); 1666 spin_lock_irqsave(&s->lock, flags); 1667 1668 /* cnt will be the number of available samples (16-bit 1669 stereo); it starts out as the maxmimum consequetive 1670 samples */ 1671 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2; 1672 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES; 1673 1674 // dma_adc.count is the current total bytes that have not been read. 1675 // if the amount of unread bytes from the current sw pointer to the 1676 // end of the buffer is greater than the current total bytes that 1677 // have not been read, then set the "cnt" (unread bytes) to the 1678 // amount of unread bytes. 1679 1680 if (count_fr < cnt) 1681 cnt = count_fr; 1682 cnt_by = cnt * FRAME_SAMPLE_BYTES; 1683 spin_unlock_irqrestore(&s->lock, flags); 1684 // 1685 // if we are converting from 8/16 then we need to copy 1686 // twice the number of 16 bit bytes then 8 bit bytes. 1687 // 1688 if (s->conversion) { 1689 if (cnt_by > (count * 2)) { 1690 cnt = (count * 2) / FRAME_SAMPLE_BYTES; 1691 cnt_by = count * 2; 1692 } 1693 } else { 1694 if (cnt_by > count) { 1695 cnt = count / FRAME_SAMPLE_BYTES; 1696 cnt_by = count; 1697 } 1698 } 1699 // 1700 // "cnt" NOW is the smaller of the amount that will be read, 1701 // and the amount that is requested in this read (or partial). 1702 // if there are no bytes in the buffer to read, then start the 1703 // ADC and wait for the interrupt handler to wake us up. 1704 // 1705 if (cnt <= 0) { 1706 1707 // start up the dma engine and then continue back to the top of 1708 // the loop when wake up occurs. 1709 start_adc(s); 1710 if (file->f_flags & O_NONBLOCK) 1711 return ret ? ret : -EAGAIN; 1712 interruptible_sleep_on(&s->dma_adc.wait); 1713 if (signal_pending(current)) 1714 return ret ? ret : -ERESTARTSYS; 1715 continue; 1716 } 1717 // there are bytes in the buffer to read. 1718 // copy from the hw buffer over to the user buffer. 1719 // user buffer is designated by "buffer" 1720 // virtual address to copy from is dma_buf+swptr 1721 // the "cnt" is the number of bytes to read. 1722 1723 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO 1724 "_read() copy_to cnt=%d count=%d ", cnt_by, count)); 1725 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1726 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n", 1727 s->dma_adc.sbufsz, s->dma_adc.count, 1728 (unsigned) buffer, ret)); 1729 1730 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by)) 1731 return ret ? ret : -EFAULT; 1732 copied = cnt_by; 1733 1734 /* Return the descriptors */ 1735 spin_lock_irqsave(&s->lock, flags); 1736 CS_DBGOUT(CS_FUNCTION, 2, 1737 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr)); 1738 s->dma_adc.count -= cnt_by; 1739 s->dma_adc.sb_swptr += cnt * 2; 1740 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end) 1741 s->dma_adc.sb_swptr = s->dma_adc.sample_buf; 1742 spin_unlock_irqrestore(&s->lock, flags); 1743 count -= copied; 1744 buffer += copied; 1745 ret += copied; 1746 start_adc(s); 1747 } 1748 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1749 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret)); 1750 return ret; 1751} 1752 1753 1754static ssize_t cs4297a_write(struct file *file, const char *buffer, 1755 size_t count, loff_t * ppos) 1756{ 1757 struct cs4297a_state *s = 1758 (struct cs4297a_state *) file->private_data; 1759 ssize_t ret; 1760 unsigned long flags; 1761 unsigned swptr, hwptr; 1762 int cnt; 1763 1764 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1765 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n", 1766 count)); 1767 VALIDATE_STATE(s); 1768 1769 if (s->dma_dac.mapped) 1770 return -ENXIO; 1771 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) 1772 return ret; 1773 if (!access_ok(VERIFY_READ, buffer, count)) 1774 return -EFAULT; 1775 ret = 0; 1776 while (count > 0) { 1777 serdma_t *d = &s->dma_dac; 1778 int copy_cnt; 1779 u32 *s_tmpl; 1780 u32 *t_tmpl; 1781 u32 left, right; 1782 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE); 1783 1784 /* XXXXXX this is broken for BLOAT_FACTOR */ 1785 spin_lock_irqsave(&s->lock, flags); 1786 if (d->count < 0) { 1787 d->count = 0; 1788 d->swptr = d->hwptr; 1789 } 1790 if (d->underrun) { 1791 d->underrun = 0; 1792 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1793 d->descrtab_phys) / sizeof(serdma_descr_t)); 1794 d->swptr = d->hwptr = hwptr; 1795 } 1796 swptr = d->swptr; 1797 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES); 1798 /* Will this write fill up the buffer? */ 1799 if (d->count + cnt > d->sbufsz) 1800 cnt = d->sbufsz - d->count; 1801 spin_unlock_irqrestore(&s->lock, flags); 1802 if (cnt > count) 1803 cnt = count; 1804 if (cnt <= 0) { 1805 start_dac(s); 1806 if (file->f_flags & O_NONBLOCK) 1807 return ret ? ret : -EAGAIN; 1808 interruptible_sleep_on(&d->wait); 1809 if (signal_pending(current)) 1810 return ret ? ret : -ERESTARTSYS; 1811 continue; 1812 } 1813 if (copy_from_user(d->sample_buf, buffer, cnt)) 1814 return ret ? ret : -EFAULT; 1815 1816 copy_cnt = cnt; 1817 s_tmpl = (u32 *)d->sample_buf; 1818 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4)); 1819 1820 /* XXXKW assuming 16-bit stereo! */ 1821 do { 1822 u32 tmp; 1823 1824 t_tmpl[0] = cpu_to_be32(0x98000000); 1825 1826 tmp = be32_to_cpu(s_tmpl[0]); 1827 left = tmp & 0xffff; 1828 right = tmp >> 16; 1829 if (swap) { 1830 left = swab16(left); 1831 right = swab16(right); 1832 } 1833 t_tmpl[1] = cpu_to_be32(left >> 8); 1834 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) | 1835 (right << 4)); 1836 1837 s_tmpl++; 1838 t_tmpl += 8; 1839 copy_cnt -= 4; 1840 } while (copy_cnt); 1841 1842 /* Mux in any pending read/write accesses */ 1843 if (s->reg_request) { 1844 *(u64 *)(d->dma_buf + (swptr * 4)) |= 1845 cpu_to_be64(s->reg_request); 1846 s->reg_request = 0; 1847 wake_up(&s->dma_dac.reg_wait); 1848 } 1849 1850 CS_DBGOUT(CS_WAVE_WRITE, 4, 1851 printk(KERN_INFO 1852 "cs4297a: copy in %d to swptr %x\n", cnt, swptr)); 1853 1854 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz; 1855 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 1856 spin_lock_irqsave(&s->lock, flags); 1857 d->swptr = swptr; 1858 d->count += cnt; 1859 d->endcleared = 0; 1860 spin_unlock_irqrestore(&s->lock, flags); 1861 count -= cnt; 1862 buffer += cnt; 1863 ret += cnt; 1864 start_dac(s); 1865 } 1866 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1867 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret)); 1868 return ret; 1869} 1870 1871 1872static unsigned int cs4297a_poll(struct file *file, 1873 struct poll_table_struct *wait) 1874{ 1875 struct cs4297a_state *s = 1876 (struct cs4297a_state *) file->private_data; 1877 unsigned long flags; 1878 unsigned int mask = 0; 1879 1880 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1881 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n")); 1882 VALIDATE_STATE(s); 1883 if (file->f_mode & FMODE_WRITE) { 1884 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1885 printk(KERN_INFO 1886 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n")); 1887 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 1888 return 0; 1889 poll_wait(file, &s->dma_dac.wait, wait); 1890 } 1891 if (file->f_mode & FMODE_READ) { 1892 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1893 printk(KERN_INFO 1894 "cs4297a: cs4297a_poll() wait on FMODE_READ\n")); 1895 if(!s->dma_dac.ready && prog_dmabuf_adc(s)) 1896 return 0; 1897 poll_wait(file, &s->dma_adc.wait, wait); 1898 } 1899 spin_lock_irqsave(&s->lock, flags); 1900 cs4297a_update_ptr(s,CS_FALSE); 1901 if (file->f_mode & FMODE_WRITE) { 1902 if (s->dma_dac.mapped) { 1903 if (s->dma_dac.count >= 1904 (signed) s->dma_dac.fragsize) { 1905 if (s->dma_dac.wakeup) 1906 mask |= POLLOUT | POLLWRNORM; 1907 else 1908 mask = 0; 1909 s->dma_dac.wakeup = 0; 1910 } 1911 } else { 1912 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count) 1913 mask |= POLLOUT | POLLWRNORM; 1914 } 1915 } else if (file->f_mode & FMODE_READ) { 1916 if (s->dma_adc.mapped) { 1917 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 1918 mask |= POLLIN | POLLRDNORM; 1919 } else { 1920 if (s->dma_adc.count > 0) 1921 mask |= POLLIN | POLLRDNORM; 1922 } 1923 } 1924 spin_unlock_irqrestore(&s->lock, flags); 1925 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1926 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n", 1927 mask)); 1928 return mask; 1929} 1930 1931 1932static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma) 1933{ 1934 /* XXXKW currently no mmap support */ 1935 return -EINVAL; 1936 return 0; 1937} 1938 1939 1940static int cs4297a_ioctl(struct inode *inode, struct file *file, 1941 unsigned int cmd, unsigned long arg) 1942{ 1943 struct cs4297a_state *s = 1944 (struct cs4297a_state *) file->private_data; 1945 unsigned long flags; 1946 audio_buf_info abinfo; 1947 count_info cinfo; 1948 int val, mapped, ret; 1949 1950 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO 1951 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n", 1952 (unsigned) file, cmd)); 1953#if CSDEBUG 1954 cs_printioctl(cmd); 1955#endif 1956 VALIDATE_STATE(s); 1957 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || 1958 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); 1959 switch (cmd) { 1960 case OSS_GETVERSION: 1961 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 1962 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n", 1963 SOUND_VERSION)); 1964 return put_user(SOUND_VERSION, (int *) arg); 1965 1966 case SNDCTL_DSP_SYNC: 1967 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1968 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n")); 1969 if (file->f_mode & FMODE_WRITE) 1970 return drain_dac(s, 1971 0 /*file->f_flags & O_NONBLOCK */ 1972 ); 1973 return 0; 1974 1975 case SNDCTL_DSP_SETDUPLEX: 1976 return 0; 1977 1978 case SNDCTL_DSP_GETCAPS: 1979 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | 1980 DSP_CAP_TRIGGER | DSP_CAP_MMAP, 1981 (int *) arg); 1982 1983 case SNDCTL_DSP_RESET: 1984 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1985 "cs4297a: cs4297a_ioctl(): DSP_RESET\n")); 1986 if (file->f_mode & FMODE_WRITE) { 1987 stop_dac(s); 1988 synchronize_irq(s->irq); 1989 s->dma_dac.count = s->dma_dac.total_bytes = 1990 s->dma_dac.blocks = s->dma_dac.wakeup = 0; 1991 s->dma_dac.swptr = s->dma_dac.hwptr = 1992 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1993 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 1994 } 1995 if (file->f_mode & FMODE_READ) { 1996 stop_adc(s); 1997 synchronize_irq(s->irq); 1998 s->dma_adc.count = s->dma_adc.total_bytes = 1999 s->dma_adc.blocks = s->dma_dac.wakeup = 0; 2000 s->dma_adc.swptr = s->dma_adc.hwptr = 2001 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2002 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2003 } 2004 return 0; 2005 2006 case SNDCTL_DSP_SPEED: 2007 if (get_user(val, (int *) arg)) 2008 return -EFAULT; 2009 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2010 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val)); 2011 val = 48000; 2012 return put_user(val, (int *) arg); 2013 2014 case SNDCTL_DSP_STEREO: 2015 if (get_user(val, (int *) arg)) 2016 return -EFAULT; 2017 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2018 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val)); 2019 if (file->f_mode & FMODE_READ) { 2020 stop_adc(s); 2021 s->dma_adc.ready = 0; 2022 s->prop_adc.channels = val ? 2 : 1; 2023 } 2024 if (file->f_mode & FMODE_WRITE) { 2025 stop_dac(s); 2026 s->dma_dac.ready = 0; 2027 s->prop_dac.channels = val ? 2 : 1; 2028 } 2029 return 0; 2030 2031 case SNDCTL_DSP_CHANNELS: 2032 if (get_user(val, (int *) arg)) 2033 return -EFAULT; 2034 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2035 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n", 2036 val)); 2037 if (val != 0) { 2038 if (file->f_mode & FMODE_READ) { 2039 stop_adc(s); 2040 s->dma_adc.ready = 0; 2041 if (val >= 2) 2042 s->prop_adc.channels = 2; 2043 else 2044 s->prop_adc.channels = 1; 2045 } 2046 if (file->f_mode & FMODE_WRITE) { 2047 stop_dac(s); 2048 s->dma_dac.ready = 0; 2049 if (val >= 2) 2050 s->prop_dac.channels = 2; 2051 else 2052 s->prop_dac.channels = 1; 2053 } 2054 } 2055 2056 if (file->f_mode & FMODE_WRITE) 2057 val = s->prop_dac.channels; 2058 else if (file->f_mode & FMODE_READ) 2059 val = s->prop_adc.channels; 2060 2061 return put_user(val, (int *) arg); 2062 2063 case SNDCTL_DSP_GETFMTS: // Returns a mask 2064 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2065 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n", 2066 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2067 AFMT_U8)); 2068 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2069 AFMT_U8, (int *) arg); 2070 2071 case SNDCTL_DSP_SETFMT: 2072 if (get_user(val, (int *) arg)) 2073 return -EFAULT; 2074 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2075 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n", 2076 val)); 2077 if (val != AFMT_QUERY) { 2078 if (file->f_mode & FMODE_READ) { 2079 stop_adc(s); 2080 s->dma_adc.ready = 0; 2081 if (val != AFMT_S16_LE 2082 && val != AFMT_U16_LE && val != AFMT_S8 2083 && val != AFMT_U8) 2084 val = AFMT_U8; 2085 s->prop_adc.fmt = val; 2086 s->prop_adc.fmt_original = s->prop_adc.fmt; 2087 } 2088 if (file->f_mode & FMODE_WRITE) { 2089 stop_dac(s); 2090 s->dma_dac.ready = 0; 2091 if (val != AFMT_S16_LE 2092 && val != AFMT_U16_LE && val != AFMT_S8 2093 && val != AFMT_U8) 2094 val = AFMT_U8; 2095 s->prop_dac.fmt = val; 2096 s->prop_dac.fmt_original = s->prop_dac.fmt; 2097 } 2098 } else { 2099 if (file->f_mode & FMODE_WRITE) 2100 val = s->prop_dac.fmt_original; 2101 else if (file->f_mode & FMODE_READ) 2102 val = s->prop_adc.fmt_original; 2103 } 2104 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2105 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n", 2106 val)); 2107 return put_user(val, (int *) arg); 2108 2109 case SNDCTL_DSP_POST: 2110 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 2111 "cs4297a: cs4297a_ioctl(): DSP_POST\n")); 2112 return 0; 2113 2114 case SNDCTL_DSP_GETTRIGGER: 2115 val = 0; 2116 if (file->f_mode & s->ena & FMODE_READ) 2117 val |= PCM_ENABLE_INPUT; 2118 if (file->f_mode & s->ena & FMODE_WRITE) 2119 val |= PCM_ENABLE_OUTPUT; 2120 return put_user(val, (int *) arg); 2121 2122 case SNDCTL_DSP_SETTRIGGER: 2123 if (get_user(val, (int *) arg)) 2124 return -EFAULT; 2125 if (file->f_mode & FMODE_READ) { 2126 if (val & PCM_ENABLE_INPUT) { 2127 if (!s->dma_adc.ready 2128 && (ret = prog_dmabuf_adc(s))) 2129 return ret; 2130 start_adc(s); 2131 } else 2132 stop_adc(s); 2133 } 2134 if (file->f_mode & FMODE_WRITE) { 2135 if (val & PCM_ENABLE_OUTPUT) { 2136 if (!s->dma_dac.ready 2137 && (ret = prog_dmabuf_dac(s))) 2138 return ret; 2139 start_dac(s); 2140 } else 2141 stop_dac(s); 2142 } 2143 return 0; 2144 2145 case SNDCTL_DSP_GETOSPACE: 2146 if (!(file->f_mode & FMODE_WRITE)) 2147 return -EINVAL; 2148 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s))) 2149 return val; 2150 spin_lock_irqsave(&s->lock, flags); 2151 cs4297a_update_ptr(s,CS_FALSE); 2152 abinfo.fragsize = s->dma_dac.fragsize; 2153 if (s->dma_dac.mapped) 2154 abinfo.bytes = s->dma_dac.sbufsz; 2155 else 2156 abinfo.bytes = 2157 s->dma_dac.sbufsz - s->dma_dac.count; 2158 abinfo.fragstotal = s->dma_dac.numfrag; 2159 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; 2160 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO 2161 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n", 2162 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal, 2163 abinfo.fragments)); 2164 spin_unlock_irqrestore(&s->lock, flags); 2165 return copy_to_user((void *) arg, &abinfo, 2166 sizeof(abinfo)) ? -EFAULT : 0; 2167 2168 case SNDCTL_DSP_GETISPACE: 2169 if (!(file->f_mode & FMODE_READ)) 2170 return -EINVAL; 2171 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s))) 2172 return val; 2173 spin_lock_irqsave(&s->lock, flags); 2174 cs4297a_update_ptr(s,CS_FALSE); 2175 if (s->conversion) { 2176 abinfo.fragsize = s->dma_adc.fragsize / 2; 2177 abinfo.bytes = s->dma_adc.count / 2; 2178 abinfo.fragstotal = s->dma_adc.numfrag; 2179 abinfo.fragments = 2180 abinfo.bytes >> (s->dma_adc.fragshift - 1); 2181 } else { 2182 abinfo.fragsize = s->dma_adc.fragsize; 2183 abinfo.bytes = s->dma_adc.count; 2184 abinfo.fragstotal = s->dma_adc.numfrag; 2185 abinfo.fragments = 2186 abinfo.bytes >> s->dma_adc.fragshift; 2187 } 2188 spin_unlock_irqrestore(&s->lock, flags); 2189 return copy_to_user((void *) arg, &abinfo, 2190 sizeof(abinfo)) ? -EFAULT : 0; 2191 2192 case SNDCTL_DSP_NONBLOCK: 2193 file->f_flags |= O_NONBLOCK; 2194 return 0; 2195 2196 case SNDCTL_DSP_GETODELAY: 2197 if (!(file->f_mode & FMODE_WRITE)) 2198 return -EINVAL; 2199 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2200 return 0; 2201 spin_lock_irqsave(&s->lock, flags); 2202 cs4297a_update_ptr(s,CS_FALSE); 2203 val = s->dma_dac.count; 2204 spin_unlock_irqrestore(&s->lock, flags); 2205 return put_user(val, (int *) arg); 2206 2207 case SNDCTL_DSP_GETIPTR: 2208 if (!(file->f_mode & FMODE_READ)) 2209 return -EINVAL; 2210 if(!s->dma_adc.ready && prog_dmabuf_adc(s)) 2211 return 0; 2212 spin_lock_irqsave(&s->lock, flags); 2213 cs4297a_update_ptr(s,CS_FALSE); 2214 cinfo.bytes = s->dma_adc.total_bytes; 2215 if (s->dma_adc.mapped) { 2216 cinfo.blocks = 2217 (cinfo.bytes >> s->dma_adc.fragshift) - 2218 s->dma_adc.blocks; 2219 s->dma_adc.blocks = 2220 cinfo.bytes >> s->dma_adc.fragshift; 2221 } else { 2222 if (s->conversion) { 2223 cinfo.blocks = 2224 s->dma_adc.count / 2225 2 >> (s->dma_adc.fragshift - 1); 2226 } else 2227 cinfo.blocks = 2228 s->dma_adc.count >> s->dma_adc. 2229 fragshift; 2230 } 2231 if (s->conversion) 2232 cinfo.ptr = s->dma_adc.hwptr / 2; 2233 else 2234 cinfo.ptr = s->dma_adc.hwptr; 2235 if (s->dma_adc.mapped) 2236 s->dma_adc.count &= s->dma_adc.fragsize - 1; 2237 spin_unlock_irqrestore(&s->lock, flags); 2238 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2239 2240 case SNDCTL_DSP_GETOPTR: 2241 if (!(file->f_mode & FMODE_WRITE)) 2242 return -EINVAL; 2243 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2244 return 0; 2245 spin_lock_irqsave(&s->lock, flags); 2246 cs4297a_update_ptr(s,CS_FALSE); 2247 cinfo.bytes = s->dma_dac.total_bytes; 2248 if (s->dma_dac.mapped) { 2249 cinfo.blocks = 2250 (cinfo.bytes >> s->dma_dac.fragshift) - 2251 s->dma_dac.blocks; 2252 s->dma_dac.blocks = 2253 cinfo.bytes >> s->dma_dac.fragshift; 2254 } else { 2255 cinfo.blocks = 2256 s->dma_dac.count >> s->dma_dac.fragshift; 2257 } 2258 cinfo.ptr = s->dma_dac.hwptr; 2259 if (s->dma_dac.mapped) 2260 s->dma_dac.count &= s->dma_dac.fragsize - 1; 2261 spin_unlock_irqrestore(&s->lock, flags); 2262 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2263 2264 case SNDCTL_DSP_GETBLKSIZE: 2265 if (file->f_mode & FMODE_WRITE) { 2266 if ((val = prog_dmabuf_dac(s))) 2267 return val; 2268 return put_user(s->dma_dac.fragsize, (int *) arg); 2269 } 2270 if ((val = prog_dmabuf_adc(s))) 2271 return val; 2272 if (s->conversion) 2273 return put_user(s->dma_adc.fragsize / 2, 2274 (int *) arg); 2275 else 2276 return put_user(s->dma_adc.fragsize, (int *) arg); 2277 2278 case SNDCTL_DSP_SETFRAGMENT: 2279 if (get_user(val, (int *) arg)) 2280 return -EFAULT; 2281 return 0; // Say OK, but do nothing. 2282 2283 case SNDCTL_DSP_SUBDIVIDE: 2284 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) 2285 || (file->f_mode & FMODE_WRITE 2286 && s->dma_dac.subdivision)) return -EINVAL; 2287 if (get_user(val, (int *) arg)) 2288 return -EFAULT; 2289 if (val != 1 && val != 2 && val != 4) 2290 return -EINVAL; 2291 if (file->f_mode & FMODE_READ) 2292 s->dma_adc.subdivision = val; 2293 else if (file->f_mode & FMODE_WRITE) 2294 s->dma_dac.subdivision = val; 2295 return 0; 2296 2297 case SOUND_PCM_READ_RATE: 2298 if (file->f_mode & FMODE_READ) 2299 return put_user(s->prop_adc.rate, (int *) arg); 2300 else if (file->f_mode & FMODE_WRITE) 2301 return put_user(s->prop_dac.rate, (int *) arg); 2302 2303 case SOUND_PCM_READ_CHANNELS: 2304 if (file->f_mode & FMODE_READ) 2305 return put_user(s->prop_adc.channels, (int *) arg); 2306 else if (file->f_mode & FMODE_WRITE) 2307 return put_user(s->prop_dac.channels, (int *) arg); 2308 2309 case SOUND_PCM_READ_BITS: 2310 if (file->f_mode & FMODE_READ) 2311 return 2312 put_user( 2313 (s->prop_adc. 2314 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2315 (int *) arg); 2316 else if (file->f_mode & FMODE_WRITE) 2317 return 2318 put_user( 2319 (s->prop_dac. 2320 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2321 (int *) arg); 2322 2323 case SOUND_PCM_WRITE_FILTER: 2324 case SNDCTL_DSP_SETSYNCRO: 2325 case SOUND_PCM_READ_FILTER: 2326 return -EINVAL; 2327 } 2328 return mixer_ioctl(s, cmd, arg); 2329} 2330 2331 2332static int cs4297a_release(struct inode *inode, struct file *file) 2333{ 2334 struct cs4297a_state *s = 2335 (struct cs4297a_state *) file->private_data; 2336 2337 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO 2338 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2339 (unsigned) inode, (unsigned) file, file->f_mode)); 2340 VALIDATE_STATE(s); 2341 2342 if (file->f_mode & FMODE_WRITE) { 2343 drain_dac(s, file->f_flags & O_NONBLOCK); 2344 mutex_lock(&s->open_sem_dac); 2345 stop_dac(s); 2346 dealloc_dmabuf(s, &s->dma_dac); 2347 s->open_mode &= ~FMODE_WRITE; 2348 mutex_unlock(&s->open_sem_dac); 2349 wake_up(&s->open_wait_dac); 2350 } 2351 if (file->f_mode & FMODE_READ) { 2352 drain_adc(s, file->f_flags & O_NONBLOCK); 2353 mutex_lock(&s->open_sem_adc); 2354 stop_adc(s); 2355 dealloc_dmabuf(s, &s->dma_adc); 2356 s->open_mode &= ~FMODE_READ; 2357 mutex_unlock(&s->open_sem_adc); 2358 wake_up(&s->open_wait_adc); 2359 } 2360 return 0; 2361} 2362 2363static int cs4297a_open(struct inode *inode, struct file *file) 2364{ 2365 int minor = iminor(inode); 2366 struct cs4297a_state *s=NULL; 2367 struct list_head *entry; 2368 2369 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2370 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2371 (unsigned) inode, (unsigned) file, file->f_mode)); 2372 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2373 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG)))); 2374 2375 list_for_each(entry, &cs4297a_devs) 2376 { 2377 s = list_entry(entry, struct cs4297a_state, list); 2378 2379 if (!((s->dev_audio ^ minor) & ~0xf)) 2380 break; 2381 } 2382 if (entry == &cs4297a_devs) 2383 return -ENODEV; 2384 if (!s) { 2385 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2386 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n")); 2387 return -ENODEV; 2388 } 2389 VALIDATE_STATE(s); 2390 file->private_data = s; 2391 2392 // wait for device to become free 2393 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) { 2394 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO 2395 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n")); 2396 return -ENODEV; 2397 } 2398 if (file->f_mode & FMODE_WRITE) { 2399 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { 2400 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n"); 2401 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) 2402 ; 2403 } 2404 2405 mutex_lock(&s->open_sem_dac); 2406 while (s->open_mode & FMODE_WRITE) { 2407 if (file->f_flags & O_NONBLOCK) { 2408 mutex_unlock(&s->open_sem_dac); 2409 return -EBUSY; 2410 } 2411 mutex_unlock(&s->open_sem_dac); 2412 interruptible_sleep_on(&s->open_wait_dac); 2413 2414 if (signal_pending(current)) { 2415 printk("open - sig pending\n"); 2416 return -ERESTARTSYS; 2417 } 2418 mutex_lock(&s->open_sem_dac); 2419 } 2420 } 2421 if (file->f_mode & FMODE_READ) { 2422 mutex_lock(&s->open_sem_adc); 2423 while (s->open_mode & FMODE_READ) { 2424 if (file->f_flags & O_NONBLOCK) { 2425 mutex_unlock(&s->open_sem_adc); 2426 return -EBUSY; 2427 } 2428 mutex_unlock(&s->open_sem_adc); 2429 interruptible_sleep_on(&s->open_wait_adc); 2430 2431 if (signal_pending(current)) { 2432 printk("open - sig pending\n"); 2433 return -ERESTARTSYS; 2434 } 2435 mutex_lock(&s->open_sem_adc); 2436 } 2437 } 2438 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 2439 if (file->f_mode & FMODE_READ) { 2440 s->prop_adc.fmt = AFMT_S16_BE; 2441 s->prop_adc.fmt_original = s->prop_adc.fmt; 2442 s->prop_adc.channels = 2; 2443 s->prop_adc.rate = 48000; 2444 s->conversion = 0; 2445 s->ena &= ~FMODE_READ; 2446 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = 2447 s->dma_adc.subdivision = 0; 2448 mutex_unlock(&s->open_sem_adc); 2449 2450 if (prog_dmabuf_adc(s)) { 2451 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2452 "cs4297a: adc Program dmabufs failed.\n")); 2453 cs4297a_release(inode, file); 2454 return -ENOMEM; 2455 } 2456 } 2457 if (file->f_mode & FMODE_WRITE) { 2458 s->prop_dac.fmt = AFMT_S16_BE; 2459 s->prop_dac.fmt_original = s->prop_dac.fmt; 2460 s->prop_dac.channels = 2; 2461 s->prop_dac.rate = 48000; 2462 s->conversion = 0; 2463 s->ena &= ~FMODE_WRITE; 2464 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = 2465 s->dma_dac.subdivision = 0; 2466 mutex_unlock(&s->open_sem_dac); 2467 2468 if (prog_dmabuf_dac(s)) { 2469 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2470 "cs4297a: dac Program dmabufs failed.\n")); 2471 cs4297a_release(inode, file); 2472 return -ENOMEM; 2473 } 2474 } 2475 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, 2476 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n")); 2477 return nonseekable_open(inode, file); 2478} 2479 2480 2481// ****************************************************************************************** 2482// Wave (audio) file operations struct. 2483// ****************************************************************************************** 2484static /*const */ struct file_operations cs4297a_audio_fops = { 2485 .owner = THIS_MODULE, 2486 .llseek = no_llseek, 2487 .read = cs4297a_read, 2488 .write = cs4297a_write, 2489 .poll = cs4297a_poll, 2490 .ioctl = cs4297a_ioctl, 2491 .mmap = cs4297a_mmap, 2492 .open = cs4297a_open, 2493 .release = cs4297a_release, 2494}; 2495 2496static void cs4297a_interrupt(int irq, void *dev_id) 2497{ 2498 struct cs4297a_state *s = (struct cs4297a_state *) dev_id; 2499 u32 status; 2500 2501 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG)); 2502 2503 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2504 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status)); 2505 2506 2507 if (status & M_SYNCSER_RX_SYNC_ERR) { 2508 status = __raw_readq(SS_CSR(R_SER_STATUS)); 2509 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status); 2510 return; 2511 } 2512 2513 if (status & M_SYNCSER_RX_OVERRUN) { 2514 int newptr, i; 2515 s->stats.rx_ovrrn++; 2516 printk(KERN_ERR "cs4297a: receive FIFO overrun\n"); 2517 2518 /* Fix things up: get the receive descriptor pool 2519 clean and give them back to the hardware */ 2520 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) 2521 ; 2522 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2523 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2524 for (i=0; i<DMA_DESCR; i++) { 2525 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP; 2526 } 2527 s->dma_adc.swptr = s->dma_adc.hwptr = newptr; 2528 s->dma_adc.count = 0; 2529 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf; 2530 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 2531 } 2532 2533 spin_lock(&s->lock); 2534 cs4297a_update_ptr(s,CS_TRUE); 2535 spin_unlock(&s->lock); 2536 2537 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2538 "cs4297a: cs4297a_interrupt()-\n")); 2539} 2540 2541 2542static int __init cs4297a_init(void) 2543{ 2544 struct cs4297a_state *s; 2545 u32 pwr, id; 2546 mm_segment_t fs; 2547 int rval; 2548#ifndef CONFIG_BCM_CS4297A_CSWARM 2549 u64 cfg; 2550 int mdio_val; 2551#endif 2552 2553 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO 2554 "cs4297a: cs4297a_init_module()+ \n")); 2555 2556#ifndef CONFIG_BCM_CS4297A_CSWARM 2557 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) & 2558 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT); 2559 2560 /* Check syscfg for synchronous serial on port 1 */ 2561 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2562 if (!(cfg & M_SYS_SER1_ENABLE)) { 2563 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG); 2564 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2565 if (!(cfg & M_SYS_SER1_ENABLE)) { 2566 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n"); 2567 return -1; 2568 } 2569 2570 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n"); 2571 2572 /* Force the codec (on SWARM) to reset by clearing 2573 GENO, preserving MDIO (no effect on CSWARM) */ 2574 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2575 udelay(10); 2576 } 2577 2578 /* Now set GENO */ 2579 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2580 /* Give the codec some time to finish resetting (start the bit clock) */ 2581 udelay(100); 2582#endif 2583 2584 if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) { 2585 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR 2586 "cs4297a: probe() no memory for state struct.\n")); 2587 return -1; 2588 } 2589 s->magic = CS4297a_MAGIC; 2590 init_waitqueue_head(&s->dma_adc.wait); 2591 init_waitqueue_head(&s->dma_dac.wait); 2592 init_waitqueue_head(&s->dma_adc.reg_wait); 2593 init_waitqueue_head(&s->dma_dac.reg_wait); 2594 init_waitqueue_head(&s->open_wait); 2595 init_waitqueue_head(&s->open_wait_adc); 2596 init_waitqueue_head(&s->open_wait_dac); 2597 mutex_init(&s->open_sem_adc); 2598 mutex_init(&s->open_sem_dac); 2599 spin_lock_init(&s->lock); 2600 2601 s->irq = K_INT_SER_1; 2602 2603 if (request_irq 2604 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) { 2605 CS_DBGOUT(CS_INIT | CS_ERROR, 1, 2606 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq)); 2607 goto err_irq; 2608 } 2609 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) < 2610 0) { 2611 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2612 "cs4297a: probe() register_sound_dsp() failed.\n")); 2613 goto err_dev1; 2614 } 2615 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) < 2616 0) { 2617 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2618 "cs4297a: probe() register_sound_mixer() failed.\n")); 2619 goto err_dev2; 2620 } 2621 2622 if (ser_init(s) || dma_init(s)) { 2623 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2624 "cs4297a: ser_init failed.\n")); 2625 goto err_dev3; 2626 } 2627 2628 do { 2629 udelay(4000); 2630 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr); 2631 } while (!rval && (pwr != 0xf)); 2632 2633 if (!rval) { 2634 char *sb1250_duart_present; 2635 2636 fs = get_fs(); 2637 set_fs(KERNEL_DS); 2638 // cs4297a_write_ac97(s, 0x5e, 0x180); 2639 cs4297a_write_ac97(s, 0x02, 0x0808); 2640 cs4297a_write_ac97(s, 0x18, 0x0808); 2641 set_fs(fs); 2642 2643 list_add(&s->list, &cs4297a_devs); 2644 2645 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id); 2646 2647 sb1250_duart_present = symbol_get(sb1250_duart_present); 2648 if (sb1250_duart_present) 2649 sb1250_duart_present[1] = 0; 2650 2651 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id); 2652 2653 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2654 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n")); 2655 2656 return 0; 2657 } 2658 2659 err_dev3: 2660 unregister_sound_mixer(s->dev_mixer); 2661 err_dev2: 2662 unregister_sound_dsp(s->dev_audio); 2663 err_dev1: 2664 free_irq(s->irq, s); 2665 err_irq: 2666 kfree(s); 2667 2668 printk(KERN_INFO "cs4297a: initialization failed\n"); 2669 2670 return -1; 2671} 2672 2673static void __exit cs4297a_cleanup(void) 2674{ 2675 /* 2676 XXXKW 2677 disable_irq, free_irq 2678 drain DMA queue 2679 disable DMA 2680 disable TX/RX 2681 free memory 2682 */ 2683 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2684 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n")); 2685} 2686 2687// --------------------------------------------------------------------- 2688 2689MODULE_AUTHOR("Kip Walker, Broadcom Corp."); 2690MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board"); 2691 2692// --------------------------------------------------------------------- 2693 2694module_init(cs4297a_init); 2695module_exit(cs4297a_cleanup); 2696