1/* 2 * Routines for GF1 DMA control 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22#include <sound/driver.h> 23#include <asm/dma.h> 24#include <linux/slab.h> 25#include <sound/core.h> 26#include <sound/gus.h> 27 28static void snd_gf1_dma_ack(struct snd_gus_card * gus) 29{ 30 unsigned long flags; 31 32 spin_lock_irqsave(&gus->reg_lock, flags); 33 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00); 34 snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL); 35 spin_unlock_irqrestore(&gus->reg_lock, flags); 36} 37 38static void snd_gf1_dma_program(struct snd_gus_card * gus, 39 unsigned int addr, 40 unsigned long buf_addr, 41 unsigned int count, 42 unsigned int cmd) 43{ 44 unsigned long flags; 45 unsigned int address; 46 unsigned char dma_cmd; 47 unsigned int address_high; 48 49 // snd_printk("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n", addr, (long) buf, count); 50 51 if (gus->gf1.dma1 > 3) { 52 if (gus->gf1.enh_mode) { 53 address = addr >> 1; 54 } else { 55 if (addr & 0x1f) { 56 snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr); 57 return; 58 } 59 address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1); 60 } 61 } else { 62 address = addr; 63 } 64 65 dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd; 66 if (dma_cmd & SNDRV_GF1_DMA_16BIT) { 67 count++; 68 count &= ~1; /* align */ 69 } 70 if (gus->gf1.dma1 > 3) { 71 dma_cmd |= SNDRV_GF1_DMA_WIDTH16; 72 count++; 73 count &= ~1; /* align */ 74 } 75 snd_gf1_dma_ack(gus); 76 snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE); 77 spin_lock_irqsave(&gus->reg_lock, flags); 78 if (gus->gf1.enh_mode) { 79 address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f); 80 snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4)); 81 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high); 82 } else 83 snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4)); 84 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd); 85 spin_unlock_irqrestore(&gus->reg_lock, flags); 86} 87 88static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus) 89{ 90 struct snd_gf1_dma_block *block; 91 92 /* PCM block have bigger priority than synthesizer one */ 93 if (gus->gf1.dma_data_pcm) { 94 block = gus->gf1.dma_data_pcm; 95 if (gus->gf1.dma_data_pcm_last == block) { 96 gus->gf1.dma_data_pcm = 97 gus->gf1.dma_data_pcm_last = NULL; 98 } else { 99 gus->gf1.dma_data_pcm = block->next; 100 } 101 } else if (gus->gf1.dma_data_synth) { 102 block = gus->gf1.dma_data_synth; 103 if (gus->gf1.dma_data_synth_last == block) { 104 gus->gf1.dma_data_synth = 105 gus->gf1.dma_data_synth_last = NULL; 106 } else { 107 gus->gf1.dma_data_synth = block->next; 108 } 109 } else { 110 block = NULL; 111 } 112 if (block) { 113 gus->gf1.dma_ack = block->ack; 114 gus->gf1.dma_private_data = block->private_data; 115 } 116 return block; 117} 118 119 120static void snd_gf1_dma_interrupt(struct snd_gus_card * gus) 121{ 122 struct snd_gf1_dma_block *block; 123 124 snd_gf1_dma_ack(gus); 125 if (gus->gf1.dma_ack) 126 gus->gf1.dma_ack(gus, gus->gf1.dma_private_data); 127 spin_lock(&gus->dma_lock); 128 if (gus->gf1.dma_data_pcm == NULL && 129 gus->gf1.dma_data_synth == NULL) { 130 gus->gf1.dma_ack = NULL; 131 gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER; 132 spin_unlock(&gus->dma_lock); 133 return; 134 } 135 block = snd_gf1_dma_next_block(gus); 136 spin_unlock(&gus->dma_lock); 137 snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd); 138 kfree(block); 139} 140 141int snd_gf1_dma_init(struct snd_gus_card * gus) 142{ 143 mutex_lock(&gus->dma_mutex); 144 gus->gf1.dma_shared++; 145 if (gus->gf1.dma_shared > 1) { 146 mutex_unlock(&gus->dma_mutex); 147 return 0; 148 } 149 gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt; 150 gus->gf1.dma_data_pcm = 151 gus->gf1.dma_data_pcm_last = 152 gus->gf1.dma_data_synth = 153 gus->gf1.dma_data_synth_last = NULL; 154 mutex_unlock(&gus->dma_mutex); 155 return 0; 156} 157 158int snd_gf1_dma_done(struct snd_gus_card * gus) 159{ 160 struct snd_gf1_dma_block *block; 161 162 mutex_lock(&gus->dma_mutex); 163 gus->gf1.dma_shared--; 164 if (!gus->gf1.dma_shared) { 165 snd_dma_disable(gus->gf1.dma1); 166 snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE); 167 snd_gf1_dma_ack(gus); 168 while ((block = gus->gf1.dma_data_pcm)) { 169 gus->gf1.dma_data_pcm = block->next; 170 kfree(block); 171 } 172 while ((block = gus->gf1.dma_data_synth)) { 173 gus->gf1.dma_data_synth = block->next; 174 kfree(block); 175 } 176 gus->gf1.dma_data_pcm_last = 177 gus->gf1.dma_data_synth_last = NULL; 178 } 179 mutex_unlock(&gus->dma_mutex); 180 return 0; 181} 182 183int snd_gf1_dma_transfer_block(struct snd_gus_card * gus, 184 struct snd_gf1_dma_block * __block, 185 int atomic, 186 int synth) 187{ 188 unsigned long flags; 189 struct snd_gf1_dma_block *block; 190 191 block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL); 192 if (block == NULL) { 193 snd_printk(KERN_ERR "gf1: DMA transfer failure; not enough memory\n"); 194 return -ENOMEM; 195 } 196 *block = *__block; 197 block->next = NULL; 198 spin_lock_irqsave(&gus->dma_lock, flags); 199 if (synth) { 200 if (gus->gf1.dma_data_synth_last) { 201 gus->gf1.dma_data_synth_last->next = block; 202 gus->gf1.dma_data_synth_last = block; 203 } else { 204 gus->gf1.dma_data_synth = 205 gus->gf1.dma_data_synth_last = block; 206 } 207 } else { 208 if (gus->gf1.dma_data_pcm_last) { 209 gus->gf1.dma_data_pcm_last->next = block; 210 gus->gf1.dma_data_pcm_last = block; 211 } else { 212 gus->gf1.dma_data_pcm = 213 gus->gf1.dma_data_pcm_last = block; 214 } 215 } 216 if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) { 217 gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER; 218 block = snd_gf1_dma_next_block(gus); 219 spin_unlock_irqrestore(&gus->dma_lock, flags); 220 if (block == NULL) 221 return 0; 222 snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd); 223 kfree(block); 224 return 0; 225 } 226 spin_unlock_irqrestore(&gus->dma_lock, flags); 227 return 0; 228} 229