1/* $Revision: 1.1.1.1 $$Date: 2007/08/03 18:53:40 $ 2 * linux/include/linux/cyclades.h 3 * 4 * This file was initially written by 5 * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by 6 * Ivan Passos <ivan@cyclades.com>. 7 * 8 * This file contains the general definitions for the cyclades.c driver 9 *$Log: cyclades.h,v $ 10 *Revision 1.1.1.1 2007/08/03 18:53:40 rnuti 11 *Importing Linux MIPS Kernel 2.6.22 12 * 13 *Revision 3.1 2002/01/29 11:36:16 henrique 14 *added throttle field on struct cyclades_port to indicate whether the 15 *port is throttled or not 16 * 17 *Revision 3.1 2000/04/19 18:52:52 ivan 18 *converted address fields to unsigned long and added fields for physical 19 *addresses on cyclades_card structure; 20 * 21 *Revision 3.0 1998/11/02 14:20:59 ivan 22 *added nports field on cyclades_card structure; 23 * 24 *Revision 2.5 1998/08/03 16:57:01 ivan 25 *added cyclades_idle_stats structure; 26 * 27 *Revision 2.4 1998/06/01 12:09:53 ivan 28 *removed closing_wait2 from cyclades_port structure; 29 * 30 *Revision 2.3 1998/03/16 18:01:12 ivan 31 *changes in the cyclades_port structure to get it closer to the 32 *standard serial port structure; 33 *added constants for new ioctls; 34 * 35 *Revision 2.2 1998/02/17 16:50:00 ivan 36 *changes in the cyclades_port structure (addition of shutdown_wait and 37 *chip_rev variables); 38 *added constants for new ioctls and for CD1400 rev. numbers. 39 * 40 *Revision 2.1 1997/10/24 16:03:00 ivan 41 *added rflow (which allows enabling the CD1400 special flow control 42 *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to 43 *cyclades_port structure; 44 *added Alpha support 45 * 46 *Revision 2.0 1997/06/30 10:30:00 ivan 47 *added some new doorbell command constants related to IOCTLW and 48 *UART error signaling 49 * 50 *Revision 1.8 1997/06/03 15:30:00 ivan 51 *added constant ZFIRM_HLT 52 *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) 53 * 54 *Revision 1.7 1997/03/26 10:30:00 daniel 55 *new entries at the end of cyclades_port struct to reallocate 56 *variables illegally allocated within card memory. 57 * 58 *Revision 1.6 1996/09/09 18:35:30 bentson 59 *fold in changes for Cyclom-Z -- including structures for 60 *communicating with board as well modest changes to original 61 *structures to support new features. 62 * 63 *Revision 1.5 1995/11/13 21:13:31 bentson 64 *changes suggested by Michael Chastain <mec@duracef.shout.net> 65 *to support use of this file in non-kernel applications 66 * 67 * 68 */ 69 70#ifndef _LINUX_CYCLADES_H 71#define _LINUX_CYCLADES_H 72 73#include <linux/types.h> 74 75struct cyclades_monitor { 76 unsigned long int_count; 77 unsigned long char_count; 78 unsigned long char_max; 79 unsigned long char_last; 80}; 81 82/* 83 * These stats all reflect activity since the device was last initialized. 84 * (i.e., since the port was opened with no other processes already having it 85 * open) 86 */ 87struct cyclades_idle_stats { 88 time_t in_use; /* Time device has been in use (secs) */ 89 time_t recv_idle; /* Time since last char received (secs) */ 90 time_t xmit_idle; /* Time since last char transmitted (secs) */ 91 unsigned long recv_bytes; /* Bytes received */ 92 unsigned long xmit_bytes; /* Bytes transmitted */ 93 unsigned long overruns; /* Input overruns */ 94 unsigned long frame_errs; /* Input framing errors */ 95 unsigned long parity_errs; /* Input parity errors */ 96}; 97 98#define CYCLADES_MAGIC 0x4359 99 100#define CYGETMON 0x435901 101#define CYGETTHRESH 0x435902 102#define CYSETTHRESH 0x435903 103#define CYGETDEFTHRESH 0x435904 104#define CYSETDEFTHRESH 0x435905 105#define CYGETTIMEOUT 0x435906 106#define CYSETTIMEOUT 0x435907 107#define CYGETDEFTIMEOUT 0x435908 108#define CYSETDEFTIMEOUT 0x435909 109#define CYSETRFLOW 0x43590a 110#define CYGETRFLOW 0x43590b 111#define CYSETRTSDTR_INV 0x43590c 112#define CYGETRTSDTR_INV 0x43590d 113#define CYZSETPOLLCYCLE 0x43590e 114#define CYZGETPOLLCYCLE 0x43590f 115#define CYGETCD1400VER 0x435910 116#define CYSETWAIT 0x435912 117#define CYGETWAIT 0x435913 118 119/*************** CYCLOM-Z ADDITIONS ***************/ 120 121#define CZIOC ('M' << 8) 122#define CZ_NBOARDS (CZIOC|0xfa) 123#define CZ_BOOT_START (CZIOC|0xfb) 124#define CZ_BOOT_DATA (CZIOC|0xfc) 125#define CZ_BOOT_END (CZIOC|0xfd) 126#define CZ_TEST (CZIOC|0xfe) 127 128#define CZ_DEF_POLL (HZ/25) 129 130#define MAX_BOARD 4 /* Max number of boards */ 131#define MAX_DEV 256 /* Max number of ports total */ 132#define CYZ_MAX_SPEED 921600 133 134#define CYZ_FIFO_SIZE 16 135 136#define CYZ_BOOT_NWORDS 0x100 137struct CYZ_BOOT_CTRL { 138 unsigned short nboard; 139 int status[MAX_BOARD]; 140 int nchannel[MAX_BOARD]; 141 int fw_rev[MAX_BOARD]; 142 unsigned long offset; 143 unsigned long data[CYZ_BOOT_NWORDS]; 144}; 145 146 147#ifndef DP_WINDOW_SIZE 148/* #include "cyclomz.h" */ 149/****************** ****************** *******************/ 150/* 151 * The data types defined below are used in all ZFIRM interface 152 * data structures. They accomodate differences between HW 153 * architectures and compilers. 154 */ 155 156#include <asm/types.h> 157 158typedef __u64 ucdouble; /* 64 bits, unsigned */ 159typedef __u32 uclong; /* 32 bits, unsigned */ 160typedef __u16 ucshort; /* 16 bits, unsigned */ 161typedef __u8 ucchar; /* 8 bits, unsigned */ 162 163/* 164 * Memory Window Sizes 165 */ 166 167#define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ 168#define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and 169 8Zo V.2 */ 170#define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ 171 172/* 173 * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver 174 * normally will access only interested on the fpga_id, fpga_version, 175 * start_cpu and stop_cpu. 176 */ 177 178struct CUSTOM_REG { 179 __u32 fpga_id; /* FPGA Identification Register */ 180 __u32 fpga_version; /* FPGA Version Number Register */ 181 __u32 cpu_start; /* CPU start Register (write) */ 182 __u32 cpu_stop; /* CPU stop Register (write) */ 183 __u32 misc_reg; /* Miscelaneous Register */ 184 __u32 idt_mode; /* IDT mode Register */ 185 __u32 uart_irq_status; /* UART IRQ status Register */ 186 __u32 clear_timer0_irq; /* Clear timer interrupt Register */ 187 __u32 clear_timer1_irq; /* Clear timer interrupt Register */ 188 __u32 clear_timer2_irq; /* Clear timer interrupt Register */ 189 __u32 test_register; /* Test Register */ 190 __u32 test_count; /* Test Count Register */ 191 __u32 timer_select; /* Timer select register */ 192 __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ 193 __u32 ram_wait_state; /* RAM wait-state Register */ 194 __u32 uart_wait_state; /* UART wait-state Register */ 195 __u32 timer_wait_state; /* timer wait-state Register */ 196 __u32 ack_wait_state; /* ACK wait State Register */ 197}; 198 199/* 200 * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime 201 * registers. This structure can be used to access the 9060 registers 202 * (memory mapped). 203 */ 204 205struct RUNTIME_9060 { 206 __u32 loc_addr_range; /* 00h - Local Address Range */ 207 __u32 loc_addr_base; /* 04h - Local Address Base */ 208 __u32 loc_arbitr; /* 08h - Local Arbitration */ 209 __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */ 210 __u32 loc_rom_range; /* 10h - Local ROM Range */ 211 __u32 loc_rom_base; /* 14h - Local ROM Base */ 212 __u32 loc_bus_descr; /* 18h - Local Bus descriptor */ 213 __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */ 214 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */ 215 __u32 loc_range_io; /* 24h - Local Range for Master IO */ 216 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */ 217 __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */ 218 __u32 filler1; /* 30h */ 219 __u32 filler2; /* 34h */ 220 __u32 filler3; /* 38h */ 221 __u32 filler4; /* 3Ch */ 222 __u32 mail_box_0; /* 40h - Mail Box 0 */ 223 __u32 mail_box_1; /* 44h - Mail Box 1 */ 224 __u32 mail_box_2; /* 48h - Mail Box 2 */ 225 __u32 mail_box_3; /* 4Ch - Mail Box 3 */ 226 __u32 filler5; /* 50h */ 227 __u32 filler6; /* 54h */ 228 __u32 filler7; /* 58h */ 229 __u32 filler8; /* 5Ch */ 230 __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */ 231 __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */ 232 __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */ 233 __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ 234}; 235 236/* Values for the Local Base Address re-map register */ 237 238#define WIN_RAM 0x00000001L /* set the sliding window to RAM */ 239#define WIN_CREG 0x14000001L /* set the window to custom Registers */ 240 241/* Values timer select registers */ 242 243#define TIMER_BY_1M 0x00 /* clock divided by 1M */ 244#define TIMER_BY_256K 0x01 /* clock divided by 256k */ 245#define TIMER_BY_128K 0x02 /* clock divided by 128k */ 246#define TIMER_BY_32K 0x03 /* clock divided by 32k */ 247 248/****************** ****************** *******************/ 249#endif 250 251#ifndef ZFIRM_ID 252/* #include "zfwint.h" */ 253/****************** ****************** *******************/ 254/* 255 * This file contains the definitions for interfacing with the 256 * Cyclom-Z ZFIRM Firmware. 257 */ 258 259/* General Constant definitions */ 260 261#define MAX_CHAN 64 /* max number of channels per board */ 262 263/* firmware id structure (set after boot) */ 264 265#define ID_ADDRESS 0x00000180L /* signature/pointer address */ 266#define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ 267#define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ 268#define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ 269 270#define ZF_TINACT_DEF 1000 /* default inactivity timeout 271 (1000 ms) */ 272#define ZF_TINACT ZF_TINACT_DEF 273 274struct FIRM_ID { 275 __u32 signature; /* ZFIRM/U signature */ 276 __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */ 277}; 278 279/* Op. System id */ 280 281#define C_OS_LINUX 0x00000030 /* generic Linux system */ 282 283/* channel op_mode */ 284 285#define C_CH_DISABLE 0x00000000 /* channel is disabled */ 286#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ 287#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ 288#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ 289#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ 290 291/* comm_parity - parity */ 292 293#define C_PR_NONE 0x00000000 /* None */ 294#define C_PR_ODD 0x00000001 /* Odd */ 295#define C_PR_EVEN 0x00000002 /* Even */ 296#define C_PR_MARK 0x00000004 /* Mark */ 297#define C_PR_SPACE 0x00000008 /* Space */ 298#define C_PR_PARITY 0x000000ff 299 300#define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ 301#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ 302 303/* comm_data_l - data length and stop bits */ 304 305#define C_DL_CS5 0x00000001 306#define C_DL_CS6 0x00000002 307#define C_DL_CS7 0x00000004 308#define C_DL_CS8 0x00000008 309#define C_DL_CS 0x0000000f 310#define C_DL_1STOP 0x00000010 311#define C_DL_15STOP 0x00000020 312#define C_DL_2STOP 0x00000040 313#define C_DL_STOP 0x000000f0 314 315/* interrupt enabling/status */ 316 317#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ 318#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ 319#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ 320#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ 321#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ 322#define C_IN_MDCD 0x00000100 /* modem DCD change */ 323#define C_IN_MDSR 0x00000200 /* modem DSR change */ 324#define C_IN_MRI 0x00000400 /* modem RI change */ 325#define C_IN_MCTS 0x00000800 /* modem CTS change */ 326#define C_IN_RXBRK 0x00001000 /* Break received */ 327#define C_IN_PR_ERROR 0x00002000 /* parity error */ 328#define C_IN_FR_ERROR 0x00004000 /* frame error */ 329#define C_IN_OVR_ERROR 0x00008000 /* overrun error */ 330#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ 331#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ 332#define C_IN_MRTS 0x00040000 /* modem RTS drop */ 333#define C_IN_ICHAR 0x00080000 334 335/* flow control */ 336 337#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ 338#define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ 339#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ 340#define C_FL_SWFLOW 0x0000000f 341 342/* flow status */ 343 344#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ 345#define C_FS_SENDING 0x00000001 /* UART is sending data */ 346#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ 347 348/* rs_control/rs_status RS-232 signals */ 349 350#define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in 351 IOCTLM command */ 352#define C_RS_RTS 0x00000001 /* RTS */ 353#define C_RS_DTR 0x00000004 /* DTR */ 354#define C_RS_DCD 0x00000100 /* CD */ 355#define C_RS_DSR 0x00000200 /* DSR */ 356#define C_RS_RI 0x00000400 /* RI */ 357#define C_RS_CTS 0x00000800 /* CTS */ 358 359/* commands Host <-> Board */ 360 361#define C_CM_RESET 0x01 /* reset/flush buffers */ 362#define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ 363#define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ 364#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ 365#define C_CM_SENDXOFF 0x10 /* send Xoff */ 366#define C_CM_SENDXON 0x11 /* send Xon */ 367#define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ 368#define C_CM_SENDBRK 0x41 /* send break */ 369#define C_CM_INTBACK 0x42 /* Interrupt back */ 370#define C_CM_SET_BREAK 0x43 /* Tx break on */ 371#define C_CM_CLR_BREAK 0x44 /* Tx break off */ 372#define C_CM_CMD_DONE 0x45 /* Previous command done */ 373#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ 374#define C_CM_TINACT 0x51 /* set inactivity detection */ 375#define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ 376#define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ 377#define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ 378#define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ 379#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ 380#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ 381#define C_CM_Q_ENABLE 0x58 /* enables queue access from the 382 driver */ 383#define C_CM_Q_DISABLE 0x59 /* disables queue access from the 384 driver */ 385 386#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ 387#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ 388#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ 389#define C_CM_RXNNDT 0x63 /* rx no new data timeout */ 390#define C_CM_TXFEMPTY 0x64 391#define C_CM_ICHAR 0x65 392#define C_CM_MDCD 0x70 /* modem DCD change */ 393#define C_CM_MDSR 0x71 /* modem DSR change */ 394#define C_CM_MRI 0x72 /* modem RI change */ 395#define C_CM_MCTS 0x73 /* modem CTS change */ 396#define C_CM_MRTS 0x74 /* modem RTS drop */ 397#define C_CM_RXBRK 0x84 /* Break received */ 398#define C_CM_PR_ERROR 0x85 /* Parity error */ 399#define C_CM_FR_ERROR 0x86 /* Frame error */ 400#define C_CM_OVR_ERROR 0x87 /* Overrun error */ 401#define C_CM_RXOFL 0x88 /* RX buffer overflow */ 402#define C_CM_CMDERROR 0x90 /* command error */ 403#define C_CM_FATAL 0x91 /* fatal error */ 404#define C_CM_HW_RESET 0x92 /* reset board */ 405 406/* 407 * CH_CTRL - This per port structure contains all parameters 408 * that control an specific port. It can be seen as the 409 * configuration registers of a "super-serial-controller". 410 */ 411 412struct CH_CTRL { 413 __u32 op_mode; /* operation mode */ 414 __u32 intr_enable; /* interrupt masking */ 415 __u32 sw_flow; /* SW flow control */ 416 __u32 flow_status; /* output flow status */ 417 __u32 comm_baud; /* baud rate - numerically specified */ 418 __u32 comm_parity; /* parity */ 419 __u32 comm_data_l; /* data length/stop */ 420 __u32 comm_flags; /* other flags */ 421 __u32 hw_flow; /* HW flow control */ 422 __u32 rs_control; /* RS-232 outputs */ 423 __u32 rs_status; /* RS-232 inputs */ 424 __u32 flow_xon; /* xon char */ 425 __u32 flow_xoff; /* xoff char */ 426 __u32 hw_overflow; /* hw overflow counter */ 427 __u32 sw_overflow; /* sw overflow counter */ 428 __u32 comm_error; /* frame/parity error counter */ 429 __u32 ichar; 430 __u32 filler[7]; 431}; 432 433 434/* 435 * BUF_CTRL - This per channel structure contains 436 * all Tx and Rx buffer control for a given channel. 437 */ 438 439struct BUF_CTRL { 440 __u32 flag_dma; /* buffers are in Host memory */ 441 __u32 tx_bufaddr; /* address of the tx buffer */ 442 __u32 tx_bufsize; /* tx buffer size */ 443 __u32 tx_threshold; /* tx low water mark */ 444 __u32 tx_get; /* tail index tx buf */ 445 __u32 tx_put; /* head index tx buf */ 446 __u32 rx_bufaddr; /* address of the rx buffer */ 447 __u32 rx_bufsize; /* rx buffer size */ 448 __u32 rx_threshold; /* rx high water mark */ 449 __u32 rx_get; /* tail index rx buf */ 450 __u32 rx_put; /* head index rx buf */ 451 __u32 filler[5]; /* filler to align structures */ 452}; 453 454/* 455 * BOARD_CTRL - This per board structure contains all global 456 * control fields related to the board. 457 */ 458 459struct BOARD_CTRL { 460 461 /* static info provided by the on-board CPU */ 462 __u32 n_channel; /* number of channels */ 463 __u32 fw_version; /* firmware version */ 464 465 /* static info provided by the driver */ 466 __u32 op_system; /* op_system id */ 467 __u32 dr_version; /* driver version */ 468 469 /* board control area */ 470 __u32 inactivity; /* inactivity control */ 471 472 /* host to FW commands */ 473 __u32 hcmd_channel; /* channel number */ 474 __u32 hcmd_param; /* pointer to parameters */ 475 476 /* FW to Host commands */ 477 __u32 fwcmd_channel; /* channel number */ 478 __u32 fwcmd_param; /* pointer to parameters */ 479 __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */ 480 481 /* filler so the structures are aligned */ 482 __u32 filler[6]; 483}; 484 485/* Host Interrupt Queue */ 486 487#define QUEUE_SIZE (10*MAX_CHAN) 488 489struct INT_QUEUE { 490 unsigned char intr_code[QUEUE_SIZE]; 491 unsigned long channel[QUEUE_SIZE]; 492 unsigned long param[QUEUE_SIZE]; 493 unsigned long put; 494 unsigned long get; 495}; 496 497/* 498 * ZFW_CTRL - This is the data structure that includes all other 499 * data structures used by the Firmware. 500 */ 501 502struct ZFW_CTRL { 503 struct BOARD_CTRL board_ctrl; 504 struct CH_CTRL ch_ctrl[MAX_CHAN]; 505 struct BUF_CTRL buf_ctrl[MAX_CHAN]; 506}; 507 508/****************** ****************** *******************/ 509#endif 510 511#ifdef __KERNEL__ 512 513/* Per card data structure */ 514struct cyclades_card { 515 void __iomem *base_addr; 516 void __iomem *ctl_addr; 517 int irq; 518 int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ 519 int first_line; /* minor number of first channel on card */ 520 int nports; /* Number of ports in the card */ 521 int bus_index; /* address shift - 0 for ISA, 1 for PCI */ 522 int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ 523 spinlock_t card_lock; 524 struct cyclades_port *ports; 525}; 526 527/*************************************** 528 * Memory access functions/macros * 529 * (required to support Alpha systems) * 530 ***************************************/ 531 532#define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0) 533#define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0) 534#define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0) 535 536/* 537 * Statistics counters 538 */ 539struct cyclades_icount { 540 __u32 cts, dsr, rng, dcd, tx, rx; 541 __u32 frame, parity, overrun, brk; 542 __u32 buf_overrun; 543}; 544 545/* 546 * This is our internal structure for each serial port's state. 547 * 548 * Many fields are paralleled by the structure used by the serial_struct 549 * structure. 550 * 551 * For definitions of the flags field, see tty.h 552 */ 553 554struct cyclades_port { 555 int magic; 556 struct cyclades_card *card; 557 int line; 558 int flags; /* defined in tty.h */ 559 int type; /* UART type */ 560 struct tty_struct *tty; 561 int read_status_mask; 562 int ignore_status_mask; 563 int timeout; 564 int xmit_fifo_size; 565 int cor1,cor2,cor3,cor4,cor5; 566 int tbpr,tco,rbpr,rco; 567 int baud; 568 int rflow; 569 int rtsdtr_inv; 570 int chip_rev; 571 int custom_divisor; 572 int x_char; /* to be pushed out ASAP */ 573 int close_delay; 574 unsigned short closing_wait; 575 unsigned long event; 576 int count; /* # of fd on device */ 577 int breakon; 578 int breakoff; 579 int blocked_open; /* # of blocked opens */ 580 unsigned char *xmit_buf; 581 int xmit_head; 582 int xmit_tail; 583 int xmit_cnt; 584 int default_threshold; 585 int default_timeout; 586 unsigned long rflush_count; 587 struct cyclades_monitor mon; 588 struct cyclades_idle_stats idle_stats; 589 struct cyclades_icount icount; 590 struct work_struct tqueue; 591 wait_queue_head_t open_wait; 592 wait_queue_head_t close_wait; 593 struct completion shutdown_wait; 594 wait_queue_head_t delta_msr_wait; 595 int throttle; 596}; 597 598/* 599 * Events are used to schedule things to happen at timer-interrupt 600 * time, instead of at cy interrupt time. 601 */ 602#define Cy_EVENT_READ_PROCESS 0 603#define Cy_EVENT_WRITE_WAKEUP 1 604#define Cy_EVENT_HANGUP 2 605#define Cy_EVENT_BREAK 3 606#define Cy_EVENT_OPEN_WAKEUP 4 607#define Cy_EVENT_SHUTDOWN_WAKEUP 5 608#define Cy_EVENT_DELTA_WAKEUP 6 609#define Cy_EVENT_Z_RX_FULL 7 610 611#define CLOSING_WAIT_DELAY 30*HZ 612#define CY_CLOSING_WAIT_NONE 65535 613#define CY_CLOSING_WAIT_INF 0 614 615 616#define CyMAX_CHIPS_PER_CARD 8 617#define CyMAX_CHAR_FIFO 12 618#define CyPORTS_PER_CHIP 4 619#define CD1400_MAX_SPEED 115200 620 621#define CyISA_Ywin 0x2000 622 623#define CyPCI_Ywin 0x4000 624#define CyPCI_Yctl 0x80 625#define CyPCI_Zctl CTRL_WINDOW_SIZE 626#define CyPCI_Zwin 0x80000 627#define CyPCI_Ze_win (2 * CyPCI_Zwin) 628 629#define PCI_DEVICE_ID_MASK 0x06 630 631/**** CD1400 registers ****/ 632 633#define CD1400_REV_G 0x46 634#define CD1400_REV_J 0x48 635 636#define CyRegSize 0x0400 637#define Cy_HwReset 0x1400 638#define Cy_ClrIntr 0x1800 639#define Cy_EpldRev 0x1e00 640 641/* Global Registers */ 642 643#define CyGFRCR (0x40*2) 644#define CyRevE (44) 645#define CyCAR (0x68*2) 646#define CyCHAN_0 (0x00) 647#define CyCHAN_1 (0x01) 648#define CyCHAN_2 (0x02) 649#define CyCHAN_3 (0x03) 650#define CyGCR (0x4B*2) 651#define CyCH0_SERIAL (0x00) 652#define CyCH0_PARALLEL (0x80) 653#define CySVRR (0x67*2) 654#define CySRModem (0x04) 655#define CySRTransmit (0x02) 656#define CySRReceive (0x01) 657#define CyRICR (0x44*2) 658#define CyTICR (0x45*2) 659#define CyMICR (0x46*2) 660#define CyICR0 (0x00) 661#define CyICR1 (0x01) 662#define CyICR2 (0x02) 663#define CyICR3 (0x03) 664#define CyRIR (0x6B*2) 665#define CyTIR (0x6A*2) 666#define CyMIR (0x69*2) 667#define CyIRDirEq (0x80) 668#define CyIRBusy (0x40) 669#define CyIRUnfair (0x20) 670#define CyIRContext (0x1C) 671#define CyIRChannel (0x03) 672#define CyPPR (0x7E*2) 673#define CyCLOCK_20_1MS (0x27) 674#define CyCLOCK_25_1MS (0x31) 675#define CyCLOCK_25_5MS (0xf4) 676#define CyCLOCK_60_1MS (0x75) 677#define CyCLOCK_60_2MS (0xea) 678 679/* Virtual Registers */ 680 681#define CyRIVR (0x43*2) 682#define CyTIVR (0x42*2) 683#define CyMIVR (0x41*2) 684#define CyIVRMask (0x07) 685#define CyIVRRxEx (0x07) 686#define CyIVRRxOK (0x03) 687#define CyIVRTxOK (0x02) 688#define CyIVRMdmOK (0x01) 689#define CyTDR (0x63*2) 690#define CyRDSR (0x62*2) 691#define CyTIMEOUT (0x80) 692#define CySPECHAR (0x70) 693#define CyBREAK (0x08) 694#define CyPARITY (0x04) 695#define CyFRAME (0x02) 696#define CyOVERRUN (0x01) 697#define CyMISR (0x4C*2) 698/* see CyMCOR_ and CyMSVR_ for bits*/ 699#define CyEOSRR (0x60*2) 700 701/* Channel Registers */ 702 703#define CyLIVR (0x18*2) 704#define CyMscsr (0x01) 705#define CyTdsr (0x02) 706#define CyRgdsr (0x03) 707#define CyRedsr (0x07) 708#define CyCCR (0x05*2) 709/* Format 1 */ 710#define CyCHAN_RESET (0x80) 711#define CyCHIP_RESET (0x81) 712#define CyFlushTransFIFO (0x82) 713/* Format 2 */ 714#define CyCOR_CHANGE (0x40) 715#define CyCOR1ch (0x02) 716#define CyCOR2ch (0x04) 717#define CyCOR3ch (0x08) 718/* Format 3 */ 719#define CySEND_SPEC_1 (0x21) 720#define CySEND_SPEC_2 (0x22) 721#define CySEND_SPEC_3 (0x23) 722#define CySEND_SPEC_4 (0x24) 723/* Format 4 */ 724#define CyCHAN_CTL (0x10) 725#define CyDIS_RCVR (0x01) 726#define CyENB_RCVR (0x02) 727#define CyDIS_XMTR (0x04) 728#define CyENB_XMTR (0x08) 729#define CySRER (0x06*2) 730#define CyMdmCh (0x80) 731#define CyRxData (0x10) 732#define CyTxRdy (0x04) 733#define CyTxMpty (0x02) 734#define CyNNDT (0x01) 735#define CyCOR1 (0x08*2) 736#define CyPARITY_NONE (0x00) 737#define CyPARITY_0 (0x20) 738#define CyPARITY_1 (0xA0) 739#define CyPARITY_E (0x40) 740#define CyPARITY_O (0xC0) 741#define Cy_1_STOP (0x00) 742#define Cy_1_5_STOP (0x04) 743#define Cy_2_STOP (0x08) 744#define Cy_5_BITS (0x00) 745#define Cy_6_BITS (0x01) 746#define Cy_7_BITS (0x02) 747#define Cy_8_BITS (0x03) 748#define CyCOR2 (0x09*2) 749#define CyIXM (0x80) 750#define CyTxIBE (0x40) 751#define CyETC (0x20) 752#define CyAUTO_TXFL (0x60) 753#define CyLLM (0x10) 754#define CyRLM (0x08) 755#define CyRtsAO (0x04) 756#define CyCtsAE (0x02) 757#define CyDsrAE (0x01) 758#define CyCOR3 (0x0A*2) 759#define CySPL_CH_DRANGE (0x80) /* special character detect range */ 760#define CySPL_CH_DET1 (0x40) /* enable special character detection 761 on SCHR4-SCHR3 */ 762#define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */ 763#define CySPL_CH_DET2 (0x10) /* Enable special character detection 764 on SCHR2-SCHR1 */ 765#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ 766#define CyCOR4 (0x1E*2) 767#define CyCOR5 (0x1F*2) 768#define CyCCSR (0x0B*2) 769#define CyRxEN (0x80) 770#define CyRxFloff (0x40) 771#define CyRxFlon (0x20) 772#define CyTxEN (0x08) 773#define CyTxFloff (0x04) 774#define CyTxFlon (0x02) 775#define CyRDCR (0x0E*2) 776#define CySCHR1 (0x1A*2) 777#define CySCHR2 (0x1B*2) 778#define CySCHR3 (0x1C*2) 779#define CySCHR4 (0x1D*2) 780#define CySCRL (0x22*2) 781#define CySCRH (0x23*2) 782#define CyLNC (0x24*2) 783#define CyMCOR1 (0x15*2) 784#define CyMCOR2 (0x16*2) 785#define CyRTPR (0x21*2) 786#define CyMSVR1 (0x6C*2) 787#define CyMSVR2 (0x6D*2) 788#define CyANY_DELTA (0xF0) 789#define CyDSR (0x80) 790#define CyCTS (0x40) 791#define CyRI (0x20) 792#define CyDCD (0x10) 793#define CyDTR (0x02) 794#define CyRTS (0x01) 795#define CyPVSR (0x6F*2) 796#define CyRBPR (0x78*2) 797#define CyRCOR (0x7C*2) 798#define CyTBPR (0x72*2) 799#define CyTCOR (0x76*2) 800 801/* Custom Registers */ 802 803#define CyPLX_VER (0x3400) 804#define PLX_9050 0x0b 805#define PLX_9060 0x0c 806#define PLX_9080 0x0d 807 808/***************************************************************************/ 809 810#endif /* __KERNEL__ */ 811#endif /* _LINUX_CYCLADES_H */ 812