1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28. 7 * 8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 by Ralf Baechle 10 */ 11#ifndef _ASM_SN_SN0_HUBPI_H 12#define _ASM_SN_SN0_HUBPI_H 13 14#include <linux/types.h> 15 16/* 17 * Hub I/O interface registers 18 * 19 * All registers in this file are subject to change until Hub chip tapeout. 20 * All register "addresses" are actually offsets. Use the LOCAL_HUB 21 * or REMOTE_HUB macros to synthesize an actual address 22 */ 23 24#define PI_BASE 0x000000 25 26/* General protection and control registers */ 27 28#define PI_CPU_PROTECT 0x000000 /* CPU Protection */ 29#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */ 30#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */ 31#define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */ 32#define PI_CPU_NUM 0x000020 /* CPU Number ID */ 33#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */ 34#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */ 35#define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */ 36 37/* CALIAS values */ 38#define PI_CALIAS_SIZE_0 0 39#define PI_CALIAS_SIZE_4K 1 40#define PI_CALIAS_SIZE_8K 2 41#define PI_CALIAS_SIZE_16K 3 42#define PI_CALIAS_SIZE_32K 4 43#define PI_CALIAS_SIZE_64K 5 44#define PI_CALIAS_SIZE_128K 6 45#define PI_CALIAS_SIZE_256K 7 46#define PI_CALIAS_SIZE_512K 8 47#define PI_CALIAS_SIZE_1M 9 48#define PI_CALIAS_SIZE_2M 10 49#define PI_CALIAS_SIZE_4M 11 50#define PI_CALIAS_SIZE_8M 12 51#define PI_CALIAS_SIZE_16M 13 52#define PI_CALIAS_SIZE_32M 14 53#define PI_CALIAS_SIZE_64M 15 54 55/* Processor control and status checking */ 56 57#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */ 58#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */ 59#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */ 60#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */ 61#define PI_REPLY_LEVEL 0x000060 /* Reply Level */ 62#define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */ 63#define PI_NMI_A 0x000070 /* NMI to CPU A */ 64#define PI_NMI_B 0x000078 /* NMI to CPU B */ 65#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) 66#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */ 67 68/* Regular Interrupt register checking. */ 69 70#define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */ 71#define PI_INT_PEND0 0x000098 /* Read to get pending ints */ 72#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */ 73#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */ 74#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */ 75#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */ 76#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */ 77 78#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */ 79 80/* Crosscall interrupts */ 81 82#define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */ 83#define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */ 84#define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */ 85#define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */ 86#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */ 87 88#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */ 89 90/* Realtime Counter and Profiler control registers */ 91 92#define PI_RT_COUNT 0x030100 /* Real Time Counter */ 93#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */ 94#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */ 95#define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */ 96#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */ 97#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */ 98#define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */ 99#define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */ 100#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */ 101#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */ 102#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */ 103#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */ 104#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */ 105#define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */ 106 107#define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */ 108 109/* Built-In Self Test support */ 110 111#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */ 112#define PI_BIST_READ_DATA 0x000208 /* BIST read data */ 113#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */ 114#define PI_BIST_READY 0x000218 /* BIST Ready indicator */ 115#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */ 116#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */ 117#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */ 118 119/* Graphics control registers */ 120 121#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */ 122#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */ 123#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */ 124#define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */ 125#define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */ 126#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */ 127#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */ 128#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */ 129#define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */ 130#define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */ 131 132#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A) 133#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL 134 135/* Error and timeout registers */ 136#define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */ 137#define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */ 138#define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */ 139#define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */ 140#define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */ 141#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */ 142#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */ 143#define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */ 144#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */ 145#define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */ 146#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */ 147#define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */ 148#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */ 149#define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */ 150#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */ 151#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */ 152#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */ 153#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */ 154#define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */ 155#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */ 156#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */ 157#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */ 158#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */ 159#define PI_NACK_CMP 0x0004b8 /* NACK count compare */ 160#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) 161#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) 162#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A) 163 164/* Bits in PI_ERR_INT_PEND */ 165#define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */ 166#define PI_ERR_SPOOL_CMP_A 0x00000002 167#define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */ 168#define PI_ERR_SPUR_MSG_A 0x00000008 169#define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */ 170#define PI_ERR_WRB_TERR_A 0x00000020 171#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */ 172#define PI_ERR_WRB_WERR_A 0x00000080 173#define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */ 174#define PI_ERR_SYSSTATE_A 0x00000200 175#define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */ 176#define PI_ERR_SYSAD_DATA_A 0x00000800 177#define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */ 178#define PI_ERR_SYSAD_ADDR_A 0x00002000 179#define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */ 180#define PI_ERR_SYSCMD_DATA_A 0x00008000 181#define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */ 182#define PI_ERR_SYSCMD_ADDR_A 0x00020000 183#define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */ 184#define PI_ERR_BAD_SPOOL_A 0x00080000 185#define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */ 186#define PI_ERR_UNCAC_UNCORR_A 0x00200000 187#define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */ 188#define PI_ERR_SYSSTATE_TAG_A 0x00800000 189#define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */ 190 191#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa 192#define PI_ERR_CLEAR_ALL_B 0x00555555 193 194 195/* 196 * The following three macros define all possible error int pends. 197 */ 198 199#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \ 200 PI_ERR_BAD_SPOOL_A | \ 201 PI_ERR_SYSCMD_ADDR_A | \ 202 PI_ERR_SYSCMD_DATA_A | \ 203 PI_ERR_SYSAD_ADDR_A | \ 204 PI_ERR_SYSAD_DATA_A | \ 205 PI_ERR_SYSSTATE_A) 206 207#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \ 208 PI_ERR_WRB_WERR_A | \ 209 PI_ERR_WRB_TERR_A | \ 210 PI_ERR_SPUR_MSG_A | \ 211 PI_ERR_SPOOL_CMP_A) 212 213#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \ 214 PI_ERR_BAD_SPOOL_B | \ 215 PI_ERR_SYSCMD_ADDR_B | \ 216 PI_ERR_SYSCMD_DATA_B | \ 217 PI_ERR_SYSAD_ADDR_B | \ 218 PI_ERR_SYSAD_DATA_B | \ 219 PI_ERR_SYSSTATE_B) 220 221#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ 222 PI_ERR_WRB_WERR_B | \ 223 PI_ERR_WRB_TERR_B | \ 224 PI_ERR_SPUR_MSG_B | \ 225 PI_ERR_SPOOL_CMP_B) 226 227#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) 228 229/* 230 * Error types for PI_ERR_STATUS0_[AB] and error stack: 231 * Use the write types if WRBRRB is 1 else use the read types 232 */ 233 234/* Fields in PI_ERR_STATUS0_[AB] */ 235#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007 236#define PI_ERR_ST0_TYPE_SHFT 0 237#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038 238#define PI_ERR_ST0_REQNUM_SHFT 3 239#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0 240#define PI_ERR_ST0_SUPPL_SHFT 6 241#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000 242#define PI_ERR_ST0_CMD_SHFT 17 243#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000 244#define PI_ERR_ST0_ADDR_SHFT 25 245#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000 246#define PI_ERR_ST0_OVERRUN_SHFT 62 247#define PI_ERR_ST0_VALID_MASK 0x8000000000000000 248#define PI_ERR_ST0_VALID_SHFT 63 249 250/* Fields in PI_ERR_STATUS1_[AB] */ 251#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff 252#define PI_ERR_ST1_SPOOL_SHFT 0 253#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000 254#define PI_ERR_ST1_TOUTCNT_SHFT 21 255#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000 256#define PI_ERR_ST1_INVCNT_SHFT 29 257#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000 258#define PI_ERR_ST1_CRBNUM_SHFT 39 259#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000 260#define PI_ERR_ST1_WRBRRB_SHFT 42 261#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000 262#define PI_ERR_ST1_CRBSTAT_SHFT 43 263#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000 264#define PI_ERR_ST1_MSGSRC_SHFT 53 265 266/* Fields in the error stack */ 267#define PI_ERR_STK_TYPE_MASK 0x0000000000000003 268#define PI_ERR_STK_TYPE_SHFT 0 269#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038 270#define PI_ERR_STK_SUPPL_SHFT 3 271#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0 272#define PI_ERR_STK_REQNUM_SHFT 6 273#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00 274#define PI_ERR_STK_CRBNUM_SHFT 9 275#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000 276#define PI_ERR_STK_WRBRRB_SHFT 12 277#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000 278#define PI_ERR_STK_CRBSTAT_SHFT 13 279#define PI_ERR_STK_CMD_MASK 0x000000007f800000 280#define PI_ERR_STK_CMD_SHFT 23 281#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000 282#define PI_ERR_STK_ADDR_SHFT 31 283 284/* Error type in the error status or stack on Read CRBs */ 285#define PI_ERR_RD_PRERR 1 286#define PI_ERR_RD_DERR 2 287#define PI_ERR_RD_TERR 3 288 289/* Error type in the error status or stack on Write CRBs */ 290#define PI_ERR_WR_WERR 0 291#define PI_ERR_WR_PWERR 1 292#define PI_ERR_WR_TERR 3 293 294/* Read or Write CRB in error status or stack */ 295#define PI_ERR_RRB 0 296#define PI_ERR_WRB 1 297#define PI_ERR_ANY_CRB 2 298 299/* Address masks in the error status and error stack are not the same */ 300#define ERR_STK_ADDR_SHFT 7 301#define ERR_STAT0_ADDR_SHFT 3 302 303#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */ 304#define PI_STACK_SIZE_SHFT 12 /* 4k */ 305 306#define ERR_STACK_SIZE_BYTES(_sz) \ 307 ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0) 308 309#ifndef __ASSEMBLY__ 310/* 311 * format of error stack and error status registers. 312 */ 313 314struct err_stack_format { 315 u64 sk_addr : 33, /* address */ 316 sk_cmd : 8, /* message command */ 317 sk_crb_sts : 10, /* status from RRB or WRB */ 318 sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ 319 sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ 320 sk_t5_req : 3, /* RRB T5 request number */ 321 sk_suppl : 3, /* lowest 3 bit of supplemental */ 322 sk_err_type: 3; /* error type */ 323}; 324 325typedef union pi_err_stack { 326 u64 pi_stk_word; 327 struct err_stack_format pi_stk_fmt; 328} pi_err_stack_t; 329 330struct err_status0_format { 331 u64 s0_valid : 1, /* Valid */ 332 s0_ovr_run : 1, /* Overrun, spooled to memory */ 333 s0_addr : 37, /* address */ 334 s0_cmd : 8, /* message command */ 335 s0_supl : 11, /* message supplemental field */ 336 s0_t5_req : 3, /* RRB T5 request number */ 337 s0_err_type: 3; /* error type */ 338}; 339 340typedef union pi_err_stat0 { 341 u64 pi_stat0_word; 342 struct err_status0_format pi_stat0_fmt; 343} pi_err_stat0_t; 344 345struct err_status1_format { 346 u64 s1_src : 11, /* message source */ 347 s1_crb_sts : 10, /* status from RRB or WRB */ 348 s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ 349 s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ 350 s1_inval_cnt:10, /* signed invalidate counter RRB */ 351 s1_to_cnt : 8, /* crb timeout counter */ 352 s1_spl_cnt : 21; /* number spooled to memory */ 353}; 354 355typedef union pi_err_stat1 { 356 u64 pi_stat1_word; 357 struct err_status1_format pi_stat1_fmt; 358} pi_err_stat1_t; 359 360typedef u64 rtc_time_t; 361 362#endif /* !__ASSEMBLY__ */ 363 364 365/* Bits in PI_SYSAD_ERRCHK_EN */ 366#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ 367#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ 368#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ 369#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ 370#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ 371#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ 372#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ 373 374/* Interrupt pending bits on R10000 */ 375 376#define HUB_IP_PEND0 0x0400 377#define HUB_IP_PEND1_CC 0x0800 378#define HUB_IP_RT 0x1000 379#define HUB_IP_PROF 0x2000 380#define HUB_IP_ERROR 0x4000 381#define HUB_IP_MASK 0x7c00 382 383/* PI_RT_LOCAL_CTRL mask and shift definitions */ 384 385#define PRLC_USE_INT_SHFT 16 386#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16) 387#define PRLC_USE_INT (UINT64_CAST 1 << 16) 388#define PRLC_GCLK_SHFT 15 389#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15) 390#define PRLC_GCLK (UINT64_CAST 1 << 15) 391#define PRLC_GCLK_COUNT_SHFT 8 392#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8) 393#define PRLC_MAX_COUNT_SHFT 1 394#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1) 395#define PRLC_GCLK_EN_SHFT 0 396#define PRLC_GCLK_EN_MASK (UINT64_CAST 1) 397#define PRLC_GCLK_EN (UINT64_CAST 1) 398 399/* PI_RT_FILTER_CTRL mask and shift definitions */ 400 401/* 402 * Bits for NACK_CNT_A/B and NACK_CMP 403 */ 404#define PI_NACK_CNT_EN_SHFT 20 405#define PI_NACK_CNT_EN_MASK 0x100000 406#define PI_NACK_CNT_MASK 0x0fffff 407#define PI_NACK_CNT_MAX 0x0fffff 408 409#endif /* _ASM_SN_SN0_HUBPI_H */ 410