1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * DMA definitions File: sb1250_dma.h 5 * 6 * This module contains constants and macros useful for 7 * programming the SB1250's DMA controllers, both the data mover 8 * and the Ethernet DMA. 9 * 10 * SB1250 specification level: User's manual 10/21/02 11 * BCM1280 specification level: User's manual 11/24/03 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 ********************************************************************* */ 33 34 35#ifndef _SB1250_DMA_H 36#define _SB1250_DMA_H 37 38 39#include "sb1250_defs.h" 40 41/* ********************************************************************* 42 * DMA Registers 43 ********************************************************************* */ 44 45/* 46 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) 47 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 48 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 49 * Registers: DMA_CONFIG0_SER_x_RX 50 * Registers: DMA_CONFIG0_SER_x_TX 51 */ 52 53 54#define M_DMA_DROP _SB_MAKEMASK1(0) 55 56#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) 57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 58 59#define S_DMA_DESC_TYPE _SB_MAKE64(1) 60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) 61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 63 64#define K_DMA_DESC_TYPE_RING_AL 0 65#define K_DMA_DESC_TYPE_CHAIN_AL 1 66 67#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 68 SIBYTE_HDR_FEATURE_CHIP(1480) 69#define K_DMA_DESC_TYPE_RING_UAL_WI 2 70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 71#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 72 73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) 74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) 75#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) 76#define M_DMA_TBX_EN _SB_MAKEMASK1(6) 77#define M_DMA_TDX_EN _SB_MAKEMASK1(7) 78 79#define S_DMA_INT_PKTCNT _SB_MAKE64(8) 80#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) 81#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) 82#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) 83 84#define S_DMA_RINGSZ _SB_MAKE64(16) 85#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) 86#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) 87#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) 88 89#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) 90#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) 91#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) 92#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) 93 94#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) 95#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) 96#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) 97#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) 98 99/* 100 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) 101 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 102 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 103 * Registers: DMA_CONFIG1_SER_x_RX 104 * Registers: DMA_CONFIG1_SER_x_TX 105 */ 106 107#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) 108#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) 109#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) 110#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) 111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) 112#define M_DMA_L2CA _SB_MAKEMASK1(5) 113 114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 115 SIBYTE_HDR_FEATURE_CHIP(1480) 116#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) 117#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) 118#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 119#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 120 121#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 122 123#define S_DMA_HDR_SIZE _SB_MAKE64(21) 124#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) 125#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) 126#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) 127 128#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) 129 130#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) 131#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) 132#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) 133#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) 134 135#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) 136#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) 137#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) 138#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) 139 140/* 141 * Ethernet and Serial DMA Descriptor base address (Table 7-6) 142 */ 143 144#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) 145 146 147/* 148 * ASIC Mode Base Address (Table 7-7) 149 */ 150 151#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) 152 153/* 154 * DMA Descriptor Count Registers (Table 7-8) 155 */ 156 157/* No bitfields */ 158 159 160/* 161 * Current Descriptor Address Register (Table 7-11) 162 */ 163 164#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) 165#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) 166#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 167#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 168 169#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 170 SIBYTE_HDR_FEATURE_CHIP(1480) 171#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 172#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 173 174/* 175 * Receive Packet Drop Registers 176 */ 177#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 178 SIBYTE_HDR_FEATURE_CHIP(1480) 179#define S_DMA_OODLOST_RX _SB_MAKE64(0) 180#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 181#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 182 183#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 184#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 185#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 186#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 187 188/* ********************************************************************* 189 * DMA Descriptors 190 ********************************************************************* */ 191 192/* 193 * Descriptor doubleword "A" (Table 7-12) 194 */ 195 196#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) 197#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) 198#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) 199#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) 200 201/* Note: Don't shift the address over, just mask it with the mask below */ 202#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) 203#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) 204 205#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 206 207#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 208 SIBYTE_HDR_FEATURE_CHIP(1480) 209#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 210#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 211#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 212 213#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 214#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 215#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 216#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 217 218#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 219 SIBYTE_HDR_FEATURE_CHIP(1480) 220#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 221#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 222#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 223#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 224 225#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 226#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 227 228#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) 229#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) 230#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) 231#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) 232 233/* 234 * Descriptor doubleword "B" (Table 7-13) 235 */ 236 237 238#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) 239#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) 240#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 241#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 242 243#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 244 SIBYTE_HDR_FEATURE_CHIP(1480) 245#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 246#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 247#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 248#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 249#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 250 251#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 252 253/* Note: Don't shift the address over, just mask it with the mask below */ 254#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) 255#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) 256 257#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) 258#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) 259#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) 260#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) 261 262#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 263 264#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 265 SIBYTE_HDR_FEATURE_CHIP(1480) 266#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 267#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 268#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 269#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 270#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 271 272#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 273#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 274#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) 275#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) 276 277/* 278 * from pass2 some bits in dscr_b are also used for rx status 279 */ 280#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) 281#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) 282#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) 283#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) 284 285/* 286 * Ethernet Descriptor Status Bits (Table 7-15) 287 */ 288 289#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 290#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 291 292#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 293 SIBYTE_HDR_FEATURE_CHIP(1480) 294/* Note: This bit is in the DSCR_B options field */ 295#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 296#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 297 298#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 299 SIBYTE_HDR_FEATURE_CHIP(1480) 300/* Note: These bits are in the DSCR_B options field */ 301#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) 302#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) 303#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 304 305#define S_DMA_ETHRX_RXCH 53 306#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 307#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) 308#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) 309 310#define S_DMA_ETHRX_PKTTYPE 55 311#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) 312#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) 313#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) 314 315#define K_DMA_ETHRX_PKTTYPE_IPV4 0 316#define K_DMA_ETHRX_PKTTYPE_ARPV4 1 317#define K_DMA_ETHRX_PKTTYPE_802 2 318#define K_DMA_ETHRX_PKTTYPE_OTHER 3 319#define K_DMA_ETHRX_PKTTYPE_USER0 4 320#define K_DMA_ETHRX_PKTTYPE_USER1 5 321#define K_DMA_ETHRX_PKTTYPE_USER2 6 322#define K_DMA_ETHRX_PKTTYPE_USER3 7 323 324#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) 325#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) 326#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) 327#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) 328#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) 329#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) 330 331/* 332 * Ethernet Transmit Status Bits (Table 7-16) 333 */ 334 335#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) 336 337/* 338 * Ethernet Transmit Options (Table 7-17) 339 */ 340 341#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) 342#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) 343#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) 344#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) 345#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) 346#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) 347#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) 348#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) 349#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) 350#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) 351#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) 352#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) 353#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) 354#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) 355#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) 356#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) 357 358/* 359 * Serial Receive Options (Table 7-18) 360 */ 361#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) 362#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) 363#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) 364#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) 365#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) 366#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) 367#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) 368#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) 369 370/* 371 * Serial Transmit Status Bits (Table 7-20) 372 */ 373 374#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63) 375 376/* 377 * Serial Transmit Options (Table 7-21) 378 */ 379 380#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) 381#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) 382#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) 383#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) 384 385 386/* ********************************************************************* 387 * Data Mover Registers 388 ********************************************************************* */ 389 390/* 391 * Data Mover Descriptor Base Address Register (Table 7-22) 392 * Register: DM_DSCR_BASE_0 393 * Register: DM_DSCR_BASE_1 394 * Register: DM_DSCR_BASE_2 395 * Register: DM_DSCR_BASE_3 396 */ 397 398#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) 399 400/* Note: Just mask the base address and then OR it in. */ 401#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) 402#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) 403 404#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) 405#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) 406#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) 407#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) 408 409#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) 410#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) 411#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) 412#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) 413 414#define K_DM_DSCR_BASE_PRIORITY_1 0 415#define K_DM_DSCR_BASE_PRIORITY_2 1 416#define K_DM_DSCR_BASE_PRIORITY_4 2 417#define K_DM_DSCR_BASE_PRIORITY_8 3 418#define K_DM_DSCR_BASE_PRIORITY_16 4 419 420#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) 421#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) 422#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ 423#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ 424#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) 425#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) 426 427/* 428 * Data Mover Descriptor Count Register (Table 7-25) 429 */ 430 431/* no bitfields */ 432 433/* 434 * Data Mover Current Descriptor Address (Table 7-24) 435 * Register: DM_CUR_DSCR_ADDR_0 436 * Register: DM_CUR_DSCR_ADDR_1 437 * Register: DM_CUR_DSCR_ADDR_2 438 * Register: DM_CUR_DSCR_ADDR_3 439 */ 440 441#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) 442#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) 443 444#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) 445#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) 446#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) 447#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ 448 M_DM_CUR_DSCR_DSCR_COUNT) 449 450 451#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 452 SIBYTE_HDR_FEATURE_CHIP(1480) 453/* 454 * Data Mover Channel Partial Result Registers 455 * Register: DM_PARTIAL_0 456 * Register: DM_PARTIAL_1 457 * Register: DM_PARTIAL_2 458 * Register: DM_PARTIAL_3 459 */ 460#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) 461#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) 462#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) 463#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ 464 M_DM_PARTIAL_CRC_PARTIAL) 465 466#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) 467#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) 468#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) 469#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ 470 M_DM_PARTIAL_TCPCS_PARTIAL) 471 472#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 473#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 474 475 476#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 477 SIBYTE_HDR_FEATURE_CHIP(1480) 478/* 479 * Data Mover CRC Definition Registers 480 * Register: CRC_DEF_0 481 * Register: CRC_DEF_1 482 */ 483#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) 484#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) 485#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) 486#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ 487 M_CRC_DEF_CRC_INIT) 488 489#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) 490#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) 491#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 492#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 493 M_CRC_DEF_CRC_POLY) 494#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 495 496 497#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 498 SIBYTE_HDR_FEATURE_CHIP(1480) 499/* 500 * Data Mover CRC/Checksum Definition Registers 501 * Register: CTCP_DEF_0 502 * Register: CTCP_DEF_1 503 */ 504#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) 505#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) 506#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) 507#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ 508 M_CTCP_DEF_CRC_TXOR) 509 510#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) 511#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) 512#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) 513#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ 514 M_CTCP_DEF_TCPCS_INIT) 515 516#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) 517#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) 518#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) 519#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ 520 M_CTCP_DEF_CRC_WIDTH) 521 522#define K_CTCP_DEF_CRC_WIDTH_4 0 523#define K_CTCP_DEF_CRC_WIDTH_2 1 524#define K_CTCP_DEF_CRC_WIDTH_1 2 525 526#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) 527#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 528 529 530/* 531 * Data Mover Descriptor Doubleword "A" (Table 7-26) 532 */ 533 534#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) 535#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) 536 537#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) 538#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) 539#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) 540#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 541#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) 542#endif /* up to 1250 PASS1 */ 543 544#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) 545#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) 546#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) 547#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) 548 549#define K_DM_DSCRA_DIR_DEST_INCR 0 550#define K_DM_DSCRA_DIR_DEST_DECR 1 551#define K_DM_DSCRA_DIR_DEST_CONST 2 552 553#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) 554#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) 555#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) 556 557#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) 558#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) 559#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) 560#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) 561 562#define K_DM_DSCRA_DIR_SRC_INCR 0 563#define K_DM_DSCRA_DIR_SRC_DECR 1 564#define K_DM_DSCRA_DIR_SRC_CONST 2 565 566#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) 567#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) 568#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) 569 570 571#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) 572#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) 573#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) 574#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) 575 576#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 577 SIBYTE_HDR_FEATURE_CHIP(1480) 578#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) 579#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) 580#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 581 582#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 583 SIBYTE_HDR_FEATURE_CHIP(1480) 584#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) 585#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) 586#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) 587#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) 588#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) 589#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) 590#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) 591#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 592#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 593 594#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 595 596/* 597 * Data Mover Descriptor Doubleword "B" (Table 7-25) 598 */ 599 600#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) 601#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) 602 603#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) 604#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) 605#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) 606#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) 607 608 609#endif 610