1/*
2 * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2004 Ladislav Michl
10 */
11
12#ifndef __ASM_MACE_H__
13#define __ASM_MACE_H__
14
15/*
16 * Address map
17 */
18#define MACE_BASE	0x1f000000	/* physical */
19
20#undef BIT
21#define BIT(x) (1UL << (x))
22
23/*
24 * PCI interface
25 */
26struct mace_pci {
27	volatile unsigned int error_addr;
28	volatile unsigned int error;
29#define MACEPCI_ERROR_MASTER_ABORT		BIT(31)
30#define MACEPCI_ERROR_TARGET_ABORT		BIT(30)
31#define MACEPCI_ERROR_DATA_PARITY_ERR		BIT(29)
32#define MACEPCI_ERROR_RETRY_ERR			BIT(28)
33#define MACEPCI_ERROR_ILLEGAL_CMD		BIT(27)
34#define MACEPCI_ERROR_SYSTEM_ERR		BIT(26)
35#define MACEPCI_ERROR_INTERRUPT_TEST		BIT(25)
36#define MACEPCI_ERROR_PARITY_ERR		BIT(24)
37#define MACEPCI_ERROR_OVERRUN			BIT(23)
38#define MACEPCI_ERROR_RSVD			BIT(22)
39#define MACEPCI_ERROR_MEMORY_ADDR		BIT(21)
40#define MACEPCI_ERROR_CONFIG_ADDR		BIT(20)
41#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID	BIT(19)
42#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID	BIT(18)
43#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID	BIT(17)
44#define MACEPCI_ERROR_RETRY_ADDR_VALID		BIT(16)
45#define MACEPCI_ERROR_SIG_TABORT		BIT(4)
46#define MACEPCI_ERROR_DEVSEL_MASK		0xc0
47#define MACEPCI_ERROR_DEVSEL_FAST		0
48#define MACEPCI_ERROR_DEVSEL_MED		0x40
49#define MACEPCI_ERROR_DEVSEL_SLOW		0x80
50#define MACEPCI_ERROR_FBB			BIT(1)
51#define MACEPCI_ERROR_66MHZ			BIT(0)
52	volatile unsigned int control;
53#define MACEPCI_CONTROL_INT(x)			BIT(x)
54#define MACEPCI_CONTROL_INT_MASK		0xff
55#define MACEPCI_CONTROL_SERR_ENA		BIT(8)
56#define MACEPCI_CONTROL_ARB_N6			BIT(9)
57#define MACEPCI_CONTROL_PARITY_ERR		BIT(10)
58#define MACEPCI_CONTROL_MRMRA_ENA		BIT(11)
59#define MACEPCI_CONTROL_ARB_N3			BIT(12)
60#define MACEPCI_CONTROL_ARB_N4			BIT(13)
61#define MACEPCI_CONTROL_ARB_N5			BIT(14)
62#define MACEPCI_CONTROL_PARK_LIU		BIT(15)
63#define MACEPCI_CONTROL_INV_INT(x)		BIT(16+x)
64#define MACEPCI_CONTROL_INV_INT_MASK		0x00ff0000
65#define MACEPCI_CONTROL_OVERRUN_INT		BIT(24)
66#define MACEPCI_CONTROL_PARITY_INT		BIT(25)
67#define MACEPCI_CONTROL_SERR_INT		BIT(26)
68#define MACEPCI_CONTROL_IT_INT			BIT(27)
69#define MACEPCI_CONTROL_RE_INT			BIT(28)
70#define MACEPCI_CONTROL_DPED_INT		BIT(29)
71#define MACEPCI_CONTROL_TAR_INT			BIT(30)
72#define MACEPCI_CONTROL_MAR_INT			BIT(31)
73	volatile unsigned int rev;
74	unsigned int _pad[0xcf8/4 - 4];
75	volatile unsigned int config_addr;
76	union {
77		volatile unsigned char b[4];
78		volatile unsigned short w[2];
79		volatile unsigned int l;
80	} config_data;
81};
82#define MACEPCI_LOW_MEMORY		0x1a000000
83#define MACEPCI_LOW_IO			0x18000000
84#define MACEPCI_SWAPPED_VIEW		0
85#define MACEPCI_NATIVE_VIEW		0x40000000
86#define MACEPCI_IO			0x80000000
87#define MACEPCI_HI_MEMORY		0x280000000
88#define MACEPCI_HI_IO			0x100000000
89
90/*
91 * Video interface
92 */
93struct mace_video {
94	unsigned long xxx;	/* later... */
95};
96
97/*
98 * Ethernet interface
99 */
100struct mace_ethernet {
101	volatile unsigned long mac_ctrl;
102	volatile unsigned long int_stat;
103	volatile unsigned long dma_ctrl;
104	volatile unsigned long timer;
105	volatile unsigned long tx_int_al;
106	volatile unsigned long rx_int_al;
107	volatile unsigned long tx_info;
108	volatile unsigned long tx_info_al;
109	volatile unsigned long rx_buff;
110	volatile unsigned long rx_buff_al1;
111	volatile unsigned long rx_buff_al2;
112	volatile unsigned long diag;
113	volatile unsigned long phy_data;
114	volatile unsigned long phy_regs;
115	volatile unsigned long phy_trans_go;
116	volatile unsigned long backoff_seed;
117	/*===================================*/
118	volatile unsigned long imq_reserved[4];
119	volatile unsigned long mac_addr;
120	volatile unsigned long mac_addr2;
121	volatile unsigned long mcast_filter;
122	volatile unsigned long tx_ring_base;
123	/* Following are read-only registers for debugging */
124	volatile unsigned long tx_pkt1_hdr;
125	volatile unsigned long tx_pkt1_ptr[3];
126	volatile unsigned long tx_pkt2_hdr;
127	volatile unsigned long tx_pkt2_ptr[3];
128	/*===================================*/
129	volatile unsigned long rx_fifo;
130};
131
132/*
133 * Peripherals
134 */
135
136/* Audio registers */
137struct mace_audio {
138	volatile unsigned long control;
139	volatile unsigned long codec_control;		/* codec status control */
140	volatile unsigned long codec_mask;		/* codec status input mask */
141	volatile unsigned long codec_read;		/* codec status read data */
142	struct {
143		volatile unsigned long control;		/* channel control */
144		volatile unsigned long read_ptr;	/* channel read pointer */
145		volatile unsigned long write_ptr;	/* channel write pointer */
146		volatile unsigned long depth;		/* channel depth */
147	} chan[3];
148};
149
150
151/* register definitions for parallel port DMA */
152struct mace_parport {
153	/* 0 - do nothing,
154	 * 1 - pulse terminal count to the device after buffer is drained */
155#define MACEPAR_CONTEXT_LASTFLAG	BIT(63)
156	/* Should not cross 4K page boundary */
157#define MACEPAR_CONTEXT_DATA_BOUND	0x0000000000001000UL
158#define MACEPAR_CONTEXT_DATALEN_MASK	0x00000fff00000000UL
159#define MACEPAR_CONTEXT_DATALEN_SHIFT	32
160	/* Can be arbitrarily aligned on any byte boundary on output,
161	 * 64 byte aligned on input */
162#define MACEPAR_CONTEXT_BASEADDR_MASK	0x00000000ffffffffUL
163	volatile u64 context_a;
164	volatile u64 context_b;
165	/* 0 - mem->device, 1 - device->mem */
166#define MACEPAR_CTLSTAT_DIRECTION	BIT(0)
167	/* 0 - channel frozen, 1 - channel enabled */
168#define MACEPAR_CTLSTAT_ENABLE		BIT(1)
169	/* 0 - channel active, 1 - complete channel reset */
170#define MACEPAR_CTLSTAT_RESET		BIT(2)
171#define MACEPAR_CTLSTAT_CTXB_VALID	BIT(3)
172#define MACEPAR_CTLSTAT_CTXA_VALID	BIT(4)
173	volatile u64 cntlstat;		/* Control/Status register */
174#define MACEPAR_DIAG_CTXINUSE		BIT(0)
175	/* 1 - Dma engine is enabled and processing something */
176#define MACEPAR_DIAG_DMACTIVE		BIT(1)
177	/* Counter of bytes left */
178#define MACEPAR_DIAG_CTRMASK		0x0000000000003ffcUL
179#define MACEPAR_DIAG_CTRSHIFT		2
180	volatile u64 diagnostic;	/* RO: diagnostic register */
181};
182
183/* ISA Control and DMA registers */
184struct mace_isactrl {
185	volatile unsigned long ringbase;
186#define MACEISA_RINGBUFFERS_SIZE	(8 * 4096)
187
188	volatile unsigned long misc;
189#define MACEISA_FLASH_WE		BIT(0)	/* 1=> Enable FLASH writes */
190#define MACEISA_PWD_CLEAR		BIT(1)	/* 1=> PWD CLEAR jumper detected */
191#define MACEISA_NIC_DEASSERT		BIT(2)
192#define MACEISA_NIC_DATA		BIT(3)
193#define MACEISA_LED_RED			BIT(4)	/* 0=> Illuminate red LED */
194#define MACEISA_LED_GREEN		BIT(5)	/* 0=> Illuminate green LED */
195#define MACEISA_DP_RAM_ENABLE		BIT(6)
196
197	volatile unsigned long istat;
198	volatile unsigned long imask;
199#define MACEISA_AUDIO_SW_INT		BIT(0)
200#define MACEISA_AUDIO_SC_INT		BIT(1)
201#define MACEISA_AUDIO1_DMAT_INT		BIT(2)
202#define MACEISA_AUDIO1_OF_INT		BIT(3)
203#define MACEISA_AUDIO2_DMAT_INT		BIT(4)
204#define MACEISA_AUDIO2_MERR_INT		BIT(5)
205#define MACEISA_AUDIO3_DMAT_INT		BIT(6)
206#define MACEISA_AUDIO3_MERR_INT		BIT(7)
207#define MACEISA_RTC_INT			BIT(8)
208#define MACEISA_KEYB_INT		BIT(9)
209#define MACEISA_KEYB_POLL_INT		BIT(10)
210#define MACEISA_MOUSE_INT		BIT(11)
211#define MACEISA_MOUSE_POLL_INT		BIT(12)
212#define MACEISA_TIMER0_INT		BIT(13)
213#define MACEISA_TIMER1_INT		BIT(14)
214#define MACEISA_TIMER2_INT		BIT(15)
215#define MACEISA_PARALLEL_INT		BIT(16)
216#define MACEISA_PAR_CTXA_INT		BIT(17)
217#define MACEISA_PAR_CTXB_INT		BIT(18)
218#define MACEISA_PAR_MERR_INT		BIT(19)
219#define MACEISA_SERIAL1_INT		BIT(20)
220#define MACEISA_SERIAL1_TDMAT_INT	BIT(21)
221#define MACEISA_SERIAL1_TDMAPR_INT	BIT(22)
222#define MACEISA_SERIAL1_TDMAME_INT	BIT(23)
223#define MACEISA_SERIAL1_RDMAT_INT	BIT(24)
224#define MACEISA_SERIAL1_RDMAOR_INT	BIT(25)
225#define MACEISA_SERIAL2_INT		BIT(26)
226#define MACEISA_SERIAL2_TDMAT_INT	BIT(27)
227#define MACEISA_SERIAL2_TDMAPR_INT	BIT(28)
228#define MACEISA_SERIAL2_TDMAME_INT	BIT(29)
229#define MACEISA_SERIAL2_RDMAT_INT	BIT(30)
230#define MACEISA_SERIAL2_RDMAOR_INT	BIT(31)
231
232	volatile unsigned long _pad[0x2000/8 - 4];
233
234	volatile unsigned long dp_ram[0x400];
235	struct mace_parport parport;
236};
237
238/* Keyboard & Mouse registers
239 * -> drivers/input/serio/maceps2.c */
240struct mace_ps2port {
241	volatile unsigned long tx;
242	volatile unsigned long rx;
243	volatile unsigned long control;
244	volatile unsigned long status;
245};
246
247struct mace_ps2 {
248	struct mace_ps2port keyb;
249	struct mace_ps2port mouse;
250};
251
252/* I2C registers
253 * -> drivers/i2c/algos/i2c-algo-sgi.c */
254struct mace_i2c {
255	volatile unsigned long config;
256#define MACEI2C_RESET           BIT(0)
257#define MACEI2C_FAST            BIT(1)
258#define MACEI2C_DATA_OVERRIDE   BIT(2)
259#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
260#define MACEI2C_DATA_STATUS     BIT(4)
261#define MACEI2C_CLOCK_STATUS    BIT(5)
262	volatile unsigned long control;
263	volatile unsigned long data;
264};
265
266/* Timer registers */
267typedef union {
268	volatile unsigned long ust_msc;
269	struct reg {
270		volatile unsigned int ust;
271		volatile unsigned int msc;
272	} reg;
273} timer_reg;
274
275struct mace_timers {
276	volatile unsigned long ust;
277#define MACE_UST_PERIOD_NS	960
278
279	volatile unsigned long compare1;
280	volatile unsigned long compare2;
281	volatile unsigned long compare3;
282
283	timer_reg audio_in;
284	timer_reg audio_out1;
285	timer_reg audio_out2;
286	timer_reg video_in1;
287	timer_reg video_in2;
288	timer_reg video_out;
289};
290
291struct mace_perif {
292	struct mace_audio audio;
293	char _pad0[0x10000 - sizeof(struct mace_audio)];
294
295	struct mace_isactrl ctrl;
296	char _pad1[0x10000 - sizeof(struct mace_isactrl)];
297
298	struct mace_ps2 ps2;
299	char _pad2[0x10000 - sizeof(struct mace_ps2)];
300
301	struct mace_i2c i2c;
302	char _pad3[0x10000 - sizeof(struct mace_i2c)];
303
304	struct mace_timers timers;
305	char _pad4[0x10000 - sizeof(struct mace_timers)];
306};
307
308
309/*
310 * ISA peripherals
311 */
312
313/* Parallel port */
314struct mace_parallel {
315};
316
317struct mace_ecp1284 {	/* later... */
318};
319
320/* Serial port */
321struct mace_serial {
322	volatile unsigned long xxx;	/* later... */
323};
324
325struct mace_isa {
326	struct mace_parallel parallel;
327	char _pad1[0x8000 - sizeof(struct mace_parallel)];
328
329	struct mace_ecp1284 ecp1284;
330	char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
331
332	struct mace_serial serial1;
333	char _pad3[0x8000 - sizeof(struct mace_serial)];
334
335	struct mace_serial serial2;
336	char _pad4[0x8000 - sizeof(struct mace_serial)];
337
338	volatile unsigned char rtc[0x10000];
339};
340
341struct sgi_mace {
342	char _reserved[0x80000];
343
344	struct mace_pci pci;
345	char _pad0[0x80000 - sizeof(struct mace_pci)];
346
347	struct mace_video video_in1;
348	char _pad1[0x80000 - sizeof(struct mace_video)];
349
350	struct mace_video video_in2;
351	char _pad2[0x80000 - sizeof(struct mace_video)];
352
353	struct mace_video video_out;
354	char _pad3[0x80000 - sizeof(struct mace_video)];
355
356	struct mace_ethernet eth;
357	char _pad4[0x80000 - sizeof(struct mace_ethernet)];
358
359	struct mace_perif perif;
360	char _pad5[0x80000 - sizeof(struct mace_perif)];
361
362	struct mace_isa isa;
363	char _pad6[0x80000 - sizeof(struct mace_isa)];
364};
365
366extern struct sgi_mace __iomem *mace;
367
368#endif /* __ASM_MACE_H__ */
369