1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright - Galileo technology. 7 * Copyright (C) 2004 by Ralf Baechle 8 */ 9#ifndef __ASM_MIPS_MV64240_H 10#define __ASM_MIPS_MV64240_H 11 12#include <asm/addrspace.h> 13#include <asm/marvell.h> 14 15/* 16 * CPU Control Registers 17 */ 18 19#define CPU_CONFIGURATION 0x000 20#define CPU_MODE 0x120 21#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170 22#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178 23 24/* 25 * Processor Address Space 26 */ 27 28/* Sdram's BAR'S */ 29#define SCS_0_LOW_DECODE_ADDRESS 0x008 30#define SCS_0_HIGH_DECODE_ADDRESS 0x010 31#define SCS_1_LOW_DECODE_ADDRESS 0x208 32#define SCS_1_HIGH_DECODE_ADDRESS 0x210 33#define SCS_2_LOW_DECODE_ADDRESS 0x018 34#define SCS_2_HIGH_DECODE_ADDRESS 0x020 35#define SCS_3_LOW_DECODE_ADDRESS 0x218 36#define SCS_3_HIGH_DECODE_ADDRESS 0x220 37/* Devices BAR'S */ 38#define CS_0_LOW_DECODE_ADDRESS 0x028 39#define CS_0_HIGH_DECODE_ADDRESS 0x030 40#define CS_1_LOW_DECODE_ADDRESS 0x228 41#define CS_1_HIGH_DECODE_ADDRESS 0x230 42#define CS_2_LOW_DECODE_ADDRESS 0x248 43#define CS_2_HIGH_DECODE_ADDRESS 0x250 44#define CS_3_LOW_DECODE_ADDRESS 0x038 45#define CS_3_HIGH_DECODE_ADDRESS 0x040 46#define BOOTCS_LOW_DECODE_ADDRESS 0x238 47#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 48 49#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 50#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 51#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 52#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 53#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 54#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 55#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 56#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 57#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 58#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 59 60#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 61#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 62#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 63#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 64#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 65#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 66#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 67#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 68#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 69#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 70 71#define INTERNAL_SPACE_DECODE 0x068 72 73#define CPU_0_LOW_DECODE_ADDRESS 0x290 74#define CPU_0_HIGH_DECODE_ADDRESS 0x298 75#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 76#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 77 78#define PCI_0I_O_ADDRESS_REMAP 0x0f0 79#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 80#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 81#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 82#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 83#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 84#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 85#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 86#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 87 88#define PCI_1I_O_ADDRESS_REMAP 0x108 89#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 90#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 91#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 92#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 93#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 94#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 95#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 96#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 97 98/* 99 * CPU Sync Barrier 100 */ 101 102#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 103#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 104 105 106/* 107 * CPU Access Protect 108 */ 109 110#define CPU_LOW_PROTECT_ADDRESS_0 0X180 111#define CPU_HIGH_PROTECT_ADDRESS_0 0X188 112#define CPU_LOW_PROTECT_ADDRESS_1 0X190 113#define CPU_HIGH_PROTECT_ADDRESS_1 0X198 114#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 115#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 116#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 117#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 118#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 119#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 120#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 121#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 122#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 123#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 124#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 125#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 126 127 128/* 129 * Snoop Control 130 */ 131 132#define SNOOP_BASE_ADDRESS_0 0x380 133#define SNOOP_TOP_ADDRESS_0 0x388 134#define SNOOP_BASE_ADDRESS_1 0x390 135#define SNOOP_TOP_ADDRESS_1 0x398 136#define SNOOP_BASE_ADDRESS_2 0x3a0 137#define SNOOP_TOP_ADDRESS_2 0x3a8 138#define SNOOP_BASE_ADDRESS_3 0x3b0 139#define SNOOP_TOP_ADDRESS_3 0x3b8 140 141/* 142 * CPU Error Report 143 */ 144 145#define CPU_ERROR_ADDRESS_LOW 0x070 146#define CPU_ERROR_ADDRESS_HIGH 0x078 147#define CPU_ERROR_DATA_LOW 0x128 148#define CPU_ERROR_DATA_HIGH 0x130 149#define CPU_ERROR_PARITY 0x138 150#define CPU_ERROR_CAUSE 0x140 151#define CPU_ERROR_MASK 0x148 152 153/* 154 * Pslave Debug 155 */ 156 157#define X_0_ADDRESS 0x360 158#define X_0_COMMAND_ID 0x368 159#define X_1_ADDRESS 0x370 160#define X_1_COMMAND_ID 0x378 161#define WRITE_DATA_LOW 0x3c0 162#define WRITE_DATA_HIGH 0x3c8 163#define WRITE_BYTE_ENABLE 0X3e0 164#define READ_DATA_LOW 0x3d0 165#define READ_DATA_HIGH 0x3d8 166#define READ_ID 0x3e8 167 168 169/* 170 * SDRAM and Device Address Space 171 */ 172 173 174/* 175 * SDRAM Configuration 176 */ 177 178#define SDRAM_CONFIGURATION 0x448 179#define SDRAM_OPERATION_MODE 0x474 180#define SDRAM_ADDRESS_DECODE 0x47C 181#define SDRAM_TIMING_PARAMETERS 0x4b4 182#define SDRAM_UMA_CONTROL 0x4a4 183#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 184#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac 185#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 186 187 188/* 189 * SDRAM Parameters 190 */ 191 192#define SDRAM_BANK0PARAMETERS 0x44C 193#define SDRAM_BANK1PARAMETERS 0x450 194#define SDRAM_BANK2PARAMETERS 0x454 195#define SDRAM_BANK3PARAMETERS 0x458 196 197 198/* 199 * SDRAM Error Report 200 */ 201 202#define SDRAM_ERROR_DATA_LOW 0x484 203#define SDRAM_ERROR_DATA_HIGH 0x480 204#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 205#define SDRAM_RECEIVED_ECC 0x488 206#define SDRAM_CALCULATED_ECC 0x48c 207#define SDRAM_ECC_CONTROL 0x494 208#define SDRAM_ECC_ERROR_COUNTER 0x498 209 210 211/* 212 * SDunit Debug (for internal use) 213 */ 214 215#define X0_ADDRESS 0x500 216#define X0_COMMAND_AND_ID 0x504 217#define X0_WRITE_DATA_LOW 0x508 218#define X0_WRITE_DATA_HIGH 0x50c 219#define X0_WRITE_BYTE_ENABLE 0x518 220#define X0_READ_DATA_LOW 0x510 221#define X0_READ_DATA_HIGH 0x514 222#define X0_READ_ID 0x51c 223#define X1_ADDRESS 0x520 224#define X1_COMMAND_AND_ID 0x524 225#define X1_WRITE_DATA_LOW 0x528 226#define X1_WRITE_DATA_HIGH 0x52c 227#define X1_WRITE_BYTE_ENABLE 0x538 228#define X1_READ_DATA_LOW 0x530 229#define X1_READ_DATA_HIGH 0x534 230#define X1_READ_ID 0x53c 231#define X0_SNOOP_ADDRESS 0x540 232#define X0_SNOOP_COMMAND 0x544 233#define X1_SNOOP_ADDRESS 0x548 234#define X1_SNOOP_COMMAND 0x54c 235 236 237/* 238 * Device Parameters 239 */ 240 241#define DEVICE_BANK0PARAMETERS 0x45c 242#define DEVICE_BANK1PARAMETERS 0x460 243#define DEVICE_BANK2PARAMETERS 0x464 244#define DEVICE_BANK3PARAMETERS 0x468 245#define DEVICE_BOOT_BANK_PARAMETERS 0x46c 246#define DEVICE_CONTROL 0x4c0 247#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 248#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc 249#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 250 251 252/* 253 * Device Interrupt 254 */ 255 256#define DEVICE_INTERRUPT_CAUSE 0x4d0 257#define DEVICE_INTERRUPT_MASK 0x4d4 258#define DEVICE_ERROR_ADDRESS 0x4d8 259 260/* 261 * DMA Record 262 */ 263 264#define CHANNEL0_DMA_BYTE_COUNT 0x800 265#define CHANNEL1_DMA_BYTE_COUNT 0x804 266#define CHANNEL2_DMA_BYTE_COUNT 0x808 267#define CHANNEL3_DMA_BYTE_COUNT 0x80C 268#define CHANNEL4_DMA_BYTE_COUNT 0x900 269#define CHANNEL5_DMA_BYTE_COUNT 0x904 270#define CHANNEL6_DMA_BYTE_COUNT 0x908 271#define CHANNEL7_DMA_BYTE_COUNT 0x90C 272#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 273#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 274#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 275#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C 276#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 277#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 278#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 279#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C 280#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 281#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 282#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 283#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C 284#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 285#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 286#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 287#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C 288#define CHANNEL0NEXT_RECORD_POINTER 0x830 289#define CHANNEL1NEXT_RECORD_POINTER 0x834 290#define CHANNEL2NEXT_RECORD_POINTER 0x838 291#define CHANNEL3NEXT_RECORD_POINTER 0x83C 292#define CHANNEL4NEXT_RECORD_POINTER 0x930 293#define CHANNEL5NEXT_RECORD_POINTER 0x934 294#define CHANNEL6NEXT_RECORD_POINTER 0x938 295#define CHANNEL7NEXT_RECORD_POINTER 0x93C 296#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 297#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 298#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 299#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C 300#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 301#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 302#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 303#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C 304#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 305#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 306#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 307#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c 308#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 309#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 310#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 311#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c 312#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 313#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 314#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 315#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac 316#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 317#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 318#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 319#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac 320#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 321#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 322#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 323#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc 324#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 325#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 326#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 327#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc 328 329/* 330 * DMA Channel Control 331 */ 332 333#define CHANNEL0CONTROL 0x840 334#define CHANNEL0CONTROL_HIGH 0x880 335 336#define CHANNEL1CONTROL 0x844 337#define CHANNEL1CONTROL_HIGH 0x884 338 339#define CHANNEL2CONTROL 0x848 340#define CHANNEL2CONTROL_HIGH 0x888 341 342#define CHANNEL3CONTROL 0x84C 343#define CHANNEL3CONTROL_HIGH 0x88C 344 345#define CHANNEL4CONTROL 0x940 346#define CHANNEL4CONTROL_HIGH 0x980 347 348#define CHANNEL5CONTROL 0x944 349#define CHANNEL5CONTROL_HIGH 0x984 350 351#define CHANNEL6CONTROL 0x948 352#define CHANNEL6CONTROL_HIGH 0x988 353 354#define CHANNEL7CONTROL 0x94C 355#define CHANNEL7CONTROL_HIGH 0x98C 356 357 358/* 359 * DMA Arbiter 360 */ 361 362#define ARBITER_CONTROL_0_3 0x860 363#define ARBITER_CONTROL_4_7 0x960 364 365 366/* 367 * DMA Interrupt 368 */ 369 370#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 371#define CHANELS0_3_INTERRUPT_MASK 0x8c4 372#define CHANELS0_3_ERROR_ADDRESS 0x8c8 373#define CHANELS0_3_ERROR_SELECT 0x8cc 374#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 375#define CHANELS4_7_INTERRUPT_MASK 0x9c4 376#define CHANELS4_7_ERROR_ADDRESS 0x9c8 377#define CHANELS4_7_ERROR_SELECT 0x9cc 378 379 380/* 381 * DMA Debug (for internal use) 382 */ 383 384#define DMA_X0_ADDRESS 0x8e0 385#define DMA_X0_COMMAND_AND_ID 0x8e4 386#define DMA_X0_WRITE_DATA_LOW 0x8e8 387#define DMA_X0_WRITE_DATA_HIGH 0x8ec 388#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 389#define DMA_X0_READ_DATA_LOW 0x8f0 390#define DMA_X0_READ_DATA_HIGH 0x8f4 391#define DMA_X0_READ_ID 0x8fc 392#define DMA_X1_ADDRESS 0x9e0 393#define DMA_X1_COMMAND_AND_ID 0x9e4 394#define DMA_X1_WRITE_DATA_LOW 0x9e8 395#define DMA_X1_WRITE_DATA_HIGH 0x9ec 396#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 397#define DMA_X1_READ_DATA_LOW 0x9f0 398#define DMA_X1_READ_DATA_HIGH 0x9f4 399#define DMA_X1_READ_ID 0x9fc 400 401/* 402 * Timer_Counter 403 */ 404 405#define TIMER_COUNTER0 0x850 406#define TIMER_COUNTER1 0x854 407#define TIMER_COUNTER2 0x858 408#define TIMER_COUNTER3 0x85C 409#define TIMER_COUNTER_0_3_CONTROL 0x864 410#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 411#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c 412#define TIMER_COUNTER4 0x950 413#define TIMER_COUNTER5 0x954 414#define TIMER_COUNTER6 0x958 415#define TIMER_COUNTER7 0x95C 416#define TIMER_COUNTER_4_7_CONTROL 0x964 417#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 418#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c 419 420/* 421 * PCI Slave Address Decoding 422 */ 423 424#define PCI_0SCS_0_BANK_SIZE 0xc08 425#define PCI_1SCS_0_BANK_SIZE 0xc88 426#define PCI_0SCS_1_BANK_SIZE 0xd08 427#define PCI_1SCS_1_BANK_SIZE 0xd88 428#define PCI_0SCS_2_BANK_SIZE 0xc0c 429#define PCI_1SCS_2_BANK_SIZE 0xc8c 430#define PCI_0SCS_3_BANK_SIZE 0xd0c 431#define PCI_1SCS_3_BANK_SIZE 0xd8c 432#define PCI_0CS_0_BANK_SIZE 0xc10 433#define PCI_1CS_0_BANK_SIZE 0xc90 434#define PCI_0CS_1_BANK_SIZE 0xd10 435#define PCI_1CS_1_BANK_SIZE 0xd90 436#define PCI_0CS_2_BANK_SIZE 0xd18 437#define PCI_1CS_2_BANK_SIZE 0xd98 438#define PCI_0CS_3_BANK_SIZE 0xc14 439#define PCI_1CS_3_BANK_SIZE 0xc94 440#define PCI_0CS_BOOT_BANK_SIZE 0xd14 441#define PCI_1CS_BOOT_BANK_SIZE 0xd94 442#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c 443#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c 444#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 445#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 446#define PCI_0P2P_I_O_BAR_SIZE 0xd24 447#define PCI_1P2P_I_O_BAR_SIZE 0xda4 448#define PCI_0CPU_BAR_SIZE 0xd28 449#define PCI_1CPU_BAR_SIZE 0xda8 450#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 451#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 452#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 453#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 454#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 455#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 456#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c 457#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c 458#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 459#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 460#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 461#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 462#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 463#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 464#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c 465#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c 466#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 467#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 468#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 469#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 470#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 471#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 472#define PCI_0DAC_CPU_BAR_SIZE 0xe2c 473#define PCI_1DAC_CPU_BAR_SIZE 0xeac 474#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c 475#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac 476#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c 477#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc 478#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 479#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 480#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 481#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 482#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c 483#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc 484#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c 485#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc 486#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 487#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 488#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 489#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 490#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 491#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 492#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 493#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 494#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 495#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 496#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c 497#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc 498#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 499#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 500#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 501#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 502#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 503#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 504#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c 505#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec 506#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 507#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 508#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 509#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 510#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 511#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 512#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 513#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 514#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c 515#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c 516#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 517#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 518#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 519#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 520#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 521#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 522#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c 523#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c 524#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 525#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 526#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 527#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 528#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 529#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 530#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c 531#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac 532#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 533#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 534#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 535#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 536#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 537#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 538#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c 539#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc 540 541/* 542 * PCI Control 543 */ 544 545#define PCI_0COMMAND 0xc00 546#define PCI_1COMMAND 0xc80 547#define PCI_0MODE 0xd00 548#define PCI_1MODE 0xd80 549#define PCI_0TIMEOUT_RETRY 0xc04 550#define PCI_1TIMEOUT_RETRY 0xc84 551#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 552#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 553#define MSI_0TRIGGER_TIMER 0xc38 554#define MSI_1TRIGGER_TIMER 0xcb8 555#define PCI_0ARBITER_CONTROL 0x1d00 556#define PCI_1ARBITER_CONTROL 0x1d80 557/* changing untill here */ 558#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 559#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c 560#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 561#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 562#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c 563#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 564#define PCI_0P2P_CONFIGURATION 0x1d14 565#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 566#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 567#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 568#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 569#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 570#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 571#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 572#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 573#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 574#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 575#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 576#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 577#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 578#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 579#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 580#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 581#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 582#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 583#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 584#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 585#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 586#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 587#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 588#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 589#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 590#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c 591#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 592#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 593#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c 594#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 595#define PCI_1P2P_CONFIGURATION 0x1d94 596#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 597#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 598#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 599#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 600#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 601#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 602#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 603#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 604#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 605#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 606#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 607#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 608#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 609#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 610#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 611#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 612#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 613#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 614#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 615#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 616#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 617#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 618#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 619#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 620 621/* 622 * PCI Snoop Control 623 */ 624 625#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 626#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 627#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 628#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 629#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 630#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 631#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 632#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 633#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 634#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 635#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 636#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 637#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 638#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 639#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 640#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 641#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 642#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 643#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 644#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 645#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 646#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 647#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 648#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 649 650/* 651 * PCI Configuration Address 652 */ 653 654#define PCI_0CONFIGURATION_ADDRESS 0xcf8 655#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc 656#define PCI_1CONFIGURATION_ADDRESS 0xc78 657#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c 658#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 659#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 660 661/* 662 * PCI Error Report 663 */ 664 665#define PCI_0SERR_MASK 0xc28 666#define PCI_0ERROR_ADDRESS_LOW 0x1d40 667#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 668#define PCI_0ERROR_DATA_LOW 0x1d48 669#define PCI_0ERROR_DATA_HIGH 0x1d4c 670#define PCI_0ERROR_COMMAND 0x1d50 671#define PCI_0ERROR_CAUSE 0x1d58 672#define PCI_0ERROR_MASK 0x1d5c 673 674#define PCI_1SERR_MASK 0xca8 675#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 676#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 677#define PCI_1ERROR_DATA_LOW 0x1dc8 678#define PCI_1ERROR_DATA_HIGH 0x1dcc 679#define PCI_1ERROR_COMMAND 0x1dd0 680#define PCI_1ERROR_CAUSE 0x1dd8 681#define PCI_1ERROR_MASK 0x1ddc 682 683 684/* 685 * Lslave Debug (for internal use) 686 */ 687 688#define L_SLAVE_X0_ADDRESS 0x1d20 689#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 690#define L_SLAVE_X1_ADDRESS 0x1d28 691#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c 692#define L_SLAVE_WRITE_DATA_LOW 0x1d30 693#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 694#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 695#define L_SLAVE_READ_DATA_LOW 0x1d38 696#define L_SLAVE_READ_DATA_HIGH 0x1d3c 697#define L_SLAVE_READ_ID 0x1d64 698 699 700/* 701 * Interrupts 702 */ 703 704#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 705#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 706#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c 707#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c 708#define CPU_SELECT_CAUSE_REGISTER 0xc70 709#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 710#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 711#define PCI_0SELECT_CAUSE 0xc74 712#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 713#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 714#define PCI_1SELECT_CAUSE 0xcf4 715#define CPU_INT_0_MASK 0xe60 716#define CPU_INT_1_MASK 0xe64 717#define CPU_INT_2_MASK 0xe68 718#define CPU_INT_3_MASK 0xe6c 719 720/* 721 * I20 Support registers 722 */ 723 724#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010 725#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014 726#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018 727#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C 728#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020 729#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024 730#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028 731#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C 732#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030 733#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034 734#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040 735#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044 736#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050 737#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054 738#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060 739#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064 740#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068 741#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C 742#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070 743#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074 744#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8 745#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC 746 747#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090 748#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094 749#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098 750#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C 751#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0 752#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4 753#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8 754#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC 755#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0 756#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4 757#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0 758#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4 759#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0 760#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4 761#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0 762#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4 763#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8 764#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC 765#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0 766#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4 767#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078 768#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C 769 770#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10 771#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14 772#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18 773#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C 774#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20 775#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24 776#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28 777#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C 778#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30 779#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34 780#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40 781#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44 782#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50 783#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54 784#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60 785#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64 786#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68 787#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C 788#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70 789#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74 790#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8 791#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC 792 793#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90 794#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94 795#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98 796#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C 797#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0 798#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4 799#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8 800#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC 801#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0 802#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4 803#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0 804#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4 805#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0 806#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4 807#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0 808#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4 809#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8 810#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC 811#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0 812#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4 813#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78 814#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C 815 816/* 817 * Communication Unit Registers 818 */ 819 820#define ETHERNET_0_ADDRESS_CONTROL_LOW 821#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 822#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 823#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c 824#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 825#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 826#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 827#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 828#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 829#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 830#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c 831#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 832#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 833#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 834#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 835#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 836#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 837#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c 838#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 839#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 840#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 841#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 842#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 843#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 844#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c 845#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 846#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 847#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 848#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 849#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 850#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac 851#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 852#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 853#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 854#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 855#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 856#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc 857#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 858#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 859#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 860#define SERIAL_INIT_LAST_DATA 0xf324 861#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 862#define COMM_UNIT_ARBITER_CONTROL 0xf300 863#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 864#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 865#define COMM_UNIT_INTERRUPT_MASK 0xf314 866#define COMM_UNIT_ERROR_ADDRESS 0xf314 867 868/* 869 * Cunit Debug (for internal use) 870 */ 871 872#define CUNIT_ADDRESS 0xf340 873#define CUNIT_COMMAND_AND_ID 0xf344 874#define CUNIT_WRITE_DATA_LOW 0xf348 875#define CUNIT_WRITE_DATA_HIGH 0xf34c 876#define CUNIT_WRITE_BYTE_ENABLE 0xf358 877#define CUNIT_READ_DATA_LOW 0xf350 878#define CUNIT_READ_DATA_HIGH 0xf354 879#define CUNIT_READ_ID 0xf35c 880 881/* 882 * Fast Ethernet Unit Registers 883 */ 884 885/* Ethernet */ 886 887#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 888#define ETHERNET_SMI_REGISTER 0x2010 889 890/* Ethernet 0 */ 891 892#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 893#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 894#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 895#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 896#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 897#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 898#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 899#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 900#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 901#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 902#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 903#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 904#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 905#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 906#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 907#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c 908#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 909#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 910#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 911#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac 912#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 913#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 914#define ETHERNET0_MIB_COUNTER_BASE 0x2500 915 916/* Ethernet 1 */ 917 918#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 919#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 920#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 921#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 922#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 923#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 924#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 925#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 926#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 927#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 928#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 929#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 930#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 931#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 932#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 933#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c 934#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 935#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 936#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 937#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac 938#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 939#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 940#define ETHERNET1_MIB_COUNTER_BASE 0x2900 941 942/* Ethernet 2 */ 943 944#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 945#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 946#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 947#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 948#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 949#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 950#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 951#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 952#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 953#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 954#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 955#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 956#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 957#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 958#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 959#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c 960#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 961#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 962#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 963#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac 964#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 965#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 966#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 967 968/* 969 * SDMA Registers 970 */ 971 972#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 973#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 974#define CHANNEL0_COMMAND_REGISTER 0x4008 975#define CHANNEL0_RX_CMD_STATUS 0x4800 976#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 977#define CHANNEL0_RX_BUFFER_POINTER 0x4808 978#define CHANNEL0_RX_NEXT_POINTER 0x480c 979#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 980#define CHANNEL0_TX_CMD_STATUS 0x4C00 981#define CHANNEL0_TX_PACKET_SIZE 0x4C04 982#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 983#define CHANNEL0_TX_NEXT_POINTER 0x4C0c 984#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 985#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 986#define CHANNEL1_CONFIGURATION_REGISTER 0x6000 987#define CHANNEL1_COMMAND_REGISTER 0x6008 988#define CHANNEL1_RX_CMD_STATUS 0x6800 989#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804 990#define CHANNEL1_RX_BUFFER_POINTER 0x6808 991#define CHANNEL1_RX_NEXT_POINTER 0x680c 992#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 993#define CHANNEL1_TX_CMD_STATUS 0x6C00 994#define CHANNEL1_TX_PACKET_SIZE 0x6C04 995#define CHANNEL1_TX_BUFFER_POINTER 0x6C08 996#define CHANNEL1_TX_NEXT_POINTER 0x6C0c 997#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 998#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 999#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 1000 1001/* SDMA Interrupt */ 1002 1003#define SDMA_CAUSE 0xb820 1004#define SDMA_MASK 0xb8a0 1005 1006 1007/* 1008 * Baude Rate Generators Registers 1009 */ 1010 1011/* BRG 0 */ 1012 1013#define BRG0_CONFIGURATION_REGISTER 0xb200 1014#define BRG0_BAUDE_TUNING_REGISTER 0xb204 1015 1016/* BRG 1 */ 1017 1018#define BRG1_CONFIGURATION_REGISTER 0xb208 1019#define BRG1_BAUDE_TUNING_REGISTER 0xb20c 1020 1021/* BRG 2 */ 1022 1023#define BRG2_CONFIGURATION_REGISTER 0xb210 1024#define BRG2_BAUDE_TUNING_REGISTER 0xb214 1025 1026/* BRG Interrupts */ 1027 1028#define BRG_CAUSE_REGISTER 0xb834 1029#define BRG_MASK_REGISTER 0xb8b4 1030 1031/* MISC */ 1032 1033#define MAIN_ROUTING_REGISTER 0xb400 1034#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 1035#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 1036#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c 1037#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 1038#define WATCHDOG_VALUE_REGISTER 0xb414 1039 1040 1041/* 1042 * Flex TDM Registers 1043 */ 1044 1045/* FTDM Port */ 1046 1047#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 1048#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 1049#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 1050#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c 1051#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 1052#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 1053#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 1054 1055/* FTDM Interrupts */ 1056 1057#define FTDM_CAUSE_REGISTER 0xb830 1058#define FTDM_MASK_REGISTER 0xb8b0 1059 1060 1061/* 1062 * GPP Interface Registers 1063 */ 1064 1065#define GPP_IO_CONTROL 0xf100 1066#define GPP_LEVEL_CONTROL 0xf110 1067#define GPP_VALUE 0xf104 1068#define GPP_INTERRUPT_CAUSE 0xf108 1069#define GPP_INTERRUPT_MASK 0xf10c 1070 1071#define MPP_CONTROL0 0xf000 1072#define MPP_CONTROL1 0xf004 1073#define MPP_CONTROL2 0xf008 1074#define MPP_CONTROL3 0xf00c 1075#define DEBUG_PORT_MULTIPLEX 0xf014 1076#define SERIAL_PORT_MULTIPLEX 0xf010 1077 1078/* 1079 * I2C Registers 1080 */ 1081 1082#define I2C_SLAVE_ADDRESS 0xc000 1083#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 1084#define I2C_DATA 0xc004 1085#define I2C_CONTROL 0xc008 1086#define I2C_STATUS_BAUDE_RATE 0xc00C 1087#define I2C_SOFT_RESET 0xc01c 1088 1089/* 1090 * MPSC Registers 1091 */ 1092 1093/* 1094 * MPSC0 1095 */ 1096 1097#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 1098#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 1099#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 1100#define CHANNEL0_REGISTER1 0x800c 1101#define CHANNEL0_REGISTER2 0x8010 1102#define CHANNEL0_REGISTER3 0x8014 1103#define CHANNEL0_REGISTER4 0x8018 1104#define CHANNEL0_REGISTER5 0x801c 1105#define CHANNEL0_REGISTER6 0x8020 1106#define CHANNEL0_REGISTER7 0x8024 1107#define CHANNEL0_REGISTER8 0x8028 1108#define CHANNEL0_REGISTER9 0x802c 1109#define CHANNEL0_REGISTER10 0x8030 1110#define CHANNEL0_REGISTER11 0x8034 1111 1112/* 1113 * MPSC1 1114 */ 1115 1116#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000 1117#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004 1118#define MPSC1_PROTOCOL_CONFIGURATION 0x9008 1119#define CHANNEL1_REGISTER1 0x900c 1120#define CHANNEL1_REGISTER2 0x9010 1121#define CHANNEL1_REGISTER3 0x9014 1122#define CHANNEL1_REGISTER4 0x9018 1123#define CHANNEL1_REGISTER5 0x901c 1124#define CHANNEL1_REGISTER6 0x9020 1125#define CHANNEL1_REGISTER7 0x9024 1126#define CHANNEL1_REGISTER8 0x9028 1127#define CHANNEL1_REGISTER9 0x902c 1128#define CHANNEL1_REGISTER10 0x9030 1129#define CHANNEL1_REGISTER11 0x9034 1130 1131/* 1132 * MPSCs Interupts 1133 */ 1134 1135#define MPSC0_CAUSE 0xb804 1136#define MPSC0_MASK 0xb884 1137#define MPSC1_CAUSE 0xb80c 1138#define MPSC1_MASK 0xb88c 1139 1140#endif /* __ASM_MIPS_MV64240_H */ 1141