1/*
2 * include/asm-xtensa/tlbflush.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TLBFLUSH_H
12#define _XTENSA_TLBFLUSH_H
13
14#ifdef __KERNEL__
15
16#include <linux/stringify.h>
17#include <asm/processor.h>
18
19#define DTLB_WAY_PGD	7
20
21#define ITLB_ARF_WAYS	4
22#define DTLB_ARF_WAYS	4
23
24#define ITLB_HIT_BIT	3
25#define DTLB_HIT_BIT	4
26
27#ifndef __ASSEMBLY__
28
29/* TLB flushing:
30 *
31 *  - flush_tlb_all() flushes all processes TLB entries
32 *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
33 *  - flush_tlb_page(mm, vmaddr) flushes a single page
34 *  - flush_tlb_range(mm, start, end) flushes a range of pages
35 */
36
37extern void flush_tlb_all(void);
38extern void flush_tlb_mm(struct mm_struct*);
39extern void flush_tlb_page(struct vm_area_struct*,unsigned long);
40extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long);
41
42#define flush_tlb_kernel_range(start,end) flush_tlb_all()
43
44
45/* This is calld in munmap when we have freed up some page-table pages.
46 * We don't need to do anything here, there's nothing special about our
47 * page-table pages.
48 */
49
50static inline void flush_tlb_pgtables(struct mm_struct *mm,
51                                      unsigned long start, unsigned long end)
52{
53}
54
55/* TLB operations. */
56
57static inline unsigned long itlb_probe(unsigned long addr)
58{
59	unsigned long tmp;
60	__asm__ __volatile__("pitlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
61	return tmp;
62}
63
64static inline unsigned long dtlb_probe(unsigned long addr)
65{
66	unsigned long tmp;
67	__asm__ __volatile__("pdtlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
68	return tmp;
69}
70
71static inline void invalidate_itlb_entry (unsigned long probe)
72{
73	__asm__ __volatile__("iitlb  %0; isync\n\t" : : "a" (probe));
74}
75
76static inline void invalidate_dtlb_entry (unsigned long probe)
77{
78	__asm__ __volatile__("idtlb  %0; dsync\n\t" : : "a" (probe));
79}
80
81/* Use the .._no_isync functions with caution.  Generally, these are
82 * handy for bulk invalidates followed by a single 'isync'.  The
83 * caller must follow up with an 'isync', which can be relatively
84 * expensive on some Xtensa implementations.
85 */
86static inline void invalidate_itlb_entry_no_isync (unsigned entry)
87{
88	/* Caller must follow up with 'isync'. */
89	__asm__ __volatile__ ("iitlb  %0\n" : : "a" (entry) );
90}
91
92static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
93{
94	/* Caller must follow up with 'isync'. */
95	__asm__ __volatile__ ("idtlb  %0\n" : : "a" (entry) );
96}
97
98static inline void set_itlbcfg_register (unsigned long val)
99{
100	__asm__ __volatile__("wsr  %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t"
101			     : : "a" (val));
102}
103
104static inline void set_dtlbcfg_register (unsigned long val)
105{
106	__asm__ __volatile__("wsr  %0, "__stringify(DTLBCFG)"; dsync\n\t"
107	    		     : : "a" (val));
108}
109
110static inline void set_ptevaddr_register (unsigned long val)
111{
112	__asm__ __volatile__(" wsr  %0, "__stringify(PTEVADDR)"; isync\n"
113			     : : "a" (val));
114}
115
116static inline unsigned long read_ptevaddr_register (void)
117{
118	unsigned long tmp;
119	__asm__ __volatile__("rsr  %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp));
120	return tmp;
121}
122
123static inline void write_dtlb_entry (pte_t entry, int way)
124{
125	__asm__ __volatile__("wdtlb  %1, %0; dsync\n\t"
126			     : : "r" (way), "r" (entry) );
127}
128
129static inline void write_itlb_entry (pte_t entry, int way)
130{
131	__asm__ __volatile__("witlb  %1, %0; isync\n\t"
132	                     : : "r" (way), "r" (entry) );
133}
134
135static inline void invalidate_page_directory (void)
136{
137	invalidate_dtlb_entry (DTLB_WAY_PGD);
138	invalidate_dtlb_entry (DTLB_WAY_PGD+1);
139	invalidate_dtlb_entry (DTLB_WAY_PGD+2);
140}
141
142static inline void invalidate_itlb_mapping (unsigned address)
143{
144	unsigned long tlb_entry;
145	if (((tlb_entry = itlb_probe(address)) & (1 << ITLB_HIT_BIT)) != 0)
146		invalidate_itlb_entry(tlb_entry);
147}
148
149static inline void invalidate_dtlb_mapping (unsigned address)
150{
151	unsigned long tlb_entry;
152	if (((tlb_entry = dtlb_probe(address)) & (1 << DTLB_HIT_BIT)) != 0)
153		invalidate_dtlb_entry(tlb_entry);
154}
155
156#define check_pgt_cache()	do { } while (0)
157
158
159/*
160 * DO NOT USE THESE FUNCTIONS.  These instructions aren't part of the Xtensa
161 * ISA and exist only for test purposes..
162 * You may find it helpful for MMU debugging, however.
163 *
164 * 'at' is the unmodified input register
165 * 'as' is the output register, as follows (specific to the Linux config):
166 *
167 *      as[31..12] contain the virtual address
168 *      as[11..08] are meaningless
169 *      as[07..00] contain the asid
170 */
171
172static inline unsigned long read_dtlb_virtual (int way)
173{
174	unsigned long tmp;
175	__asm__ __volatile__("rdtlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
176	return tmp;
177}
178
179static inline unsigned long read_dtlb_translation (int way)
180{
181	unsigned long tmp;
182	__asm__ __volatile__("rdtlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
183	return tmp;
184}
185
186static inline unsigned long read_itlb_virtual (int way)
187{
188	unsigned long tmp;
189	__asm__ __volatile__("ritlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
190	return tmp;
191}
192
193static inline unsigned long read_itlb_translation (int way)
194{
195	unsigned long tmp;
196	__asm__ __volatile__("ritlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
197	return tmp;
198}
199
200#endif	/* __ASSEMBLY__ */
201#endif	/* __KERNEL__ */
202#endif	/* _XTENSA_TLBFLUSH_H */
203