1#ifndef __SPARC64_PCI_H 2#define __SPARC64_PCI_H 3 4#ifdef __KERNEL__ 5 6#include <linux/fs.h> 7#include <linux/mm.h> 8 9/* Can be used to override the logic in pci_scan_bus for skipping 10 * already-configured bus numbers - to be used for buggy BIOSes 11 * or architectures with incomplete PCI setup by the loader. 12 */ 13#define pcibios_assign_all_busses() 0 14#define pcibios_scan_all_fns(a, b) 0 15 16#define PCIBIOS_MIN_IO 0UL 17#define PCIBIOS_MIN_MEM 0UL 18 19#define PCI_IRQ_NONE 0xffffffff 20 21#define PCI_CACHE_LINE_BYTES 64 22 23static inline void pcibios_set_master(struct pci_dev *dev) 24{ 25 /* No special bus mastering setup handling */ 26} 27 28static inline void pcibios_penalize_isa_irq(int irq, int active) 29{ 30 /* We don't do dynamic PCI IRQ allocation */ 31} 32 33/* Dynamic DMA mapping stuff. 34 */ 35 36/* The PCI address space does not equal the physical memory 37 * address space. The networking and block device layers use 38 * this boolean for bounce buffer decisions. 39 */ 40#define PCI_DMA_BUS_IS_PHYS (0) 41 42#include <asm/scatterlist.h> 43 44struct pci_dev; 45 46struct pci_iommu_ops { 47 void *(*alloc_consistent)(struct pci_dev *, size_t, dma_addr_t *, gfp_t); 48 void (*free_consistent)(struct pci_dev *, size_t, void *, dma_addr_t); 49 dma_addr_t (*map_single)(struct pci_dev *, void *, size_t, int); 50 void (*unmap_single)(struct pci_dev *, dma_addr_t, size_t, int); 51 int (*map_sg)(struct pci_dev *, struct scatterlist *, int, int); 52 void (*unmap_sg)(struct pci_dev *, struct scatterlist *, int, int); 53 void (*dma_sync_single_for_cpu)(struct pci_dev *, dma_addr_t, size_t, int); 54 void (*dma_sync_sg_for_cpu)(struct pci_dev *, struct scatterlist *, int, int); 55}; 56 57extern const struct pci_iommu_ops *pci_iommu_ops; 58 59/* Allocate and map kernel buffer using consistent mode DMA for a device. 60 * hwdev should be valid struct pci_dev pointer for PCI devices. 61 */ 62static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle) 63{ 64 return pci_iommu_ops->alloc_consistent(hwdev, size, dma_handle, GFP_ATOMIC); 65} 66 67/* Free and unmap a consistent DMA buffer. 68 * cpu_addr is what was returned from pci_alloc_consistent, 69 * size must be the same as what as passed into pci_alloc_consistent, 70 * and likewise dma_addr must be the same as what *dma_addrp was set to. 71 * 72 * References to the memory and mappings associated with cpu_addr/dma_addr 73 * past this call are illegal. 74 */ 75static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) 76{ 77 return pci_iommu_ops->free_consistent(hwdev, size, vaddr, dma_handle); 78} 79 80/* Map a single buffer of the indicated size for DMA in streaming mode. 81 * The 32-bit bus address to use is returned. 82 * 83 * Once the device is given the dma address, the device owns this memory 84 * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed. 85 */ 86static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) 87{ 88 return pci_iommu_ops->map_single(hwdev, ptr, size, direction); 89} 90 91/* Unmap a single streaming mode DMA translation. The dma_addr and size 92 * must match what was provided for in a previous pci_map_single call. All 93 * other usages are undefined. 94 * 95 * After this call, reads by the cpu to the buffer are guaranteed to see 96 * whatever the device wrote there. 97 */ 98static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction) 99{ 100 pci_iommu_ops->unmap_single(hwdev, dma_addr, size, direction); 101} 102 103/* No highmem on sparc64, plus we have an IOMMU, so mapping pages is easy. */ 104#define pci_map_page(dev, page, off, size, dir) \ 105 pci_map_single(dev, (page_address(page) + (off)), size, dir) 106#define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir) 107 108/* pci_unmap_{single,page} is not a nop, thus... */ 109#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 110 dma_addr_t ADDR_NAME; 111#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 112 __u32 LEN_NAME; 113#define pci_unmap_addr(PTR, ADDR_NAME) \ 114 ((PTR)->ADDR_NAME) 115#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 116 (((PTR)->ADDR_NAME) = (VAL)) 117#define pci_unmap_len(PTR, LEN_NAME) \ 118 ((PTR)->LEN_NAME) 119#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 120 (((PTR)->LEN_NAME) = (VAL)) 121 122/* Map a set of buffers described by scatterlist in streaming 123 * mode for DMA. This is the scatter-gather version of the 124 * above pci_map_single interface. Here the scatter gather list 125 * elements are each tagged with the appropriate dma address 126 * and length. They are obtained via sg_dma_{address,length}(SG). 127 * 128 * NOTE: An implementation may be able to use a smaller number of 129 * DMA address/length pairs than there are SG table elements. 130 * (for example via virtual mapping capabilities) 131 * The routine returns the number of addr/length pairs actually 132 * used, at most nents. 133 * 134 * Device ownership issues as mentioned above for pci_map_single are 135 * the same here. 136 */ 137static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) 138{ 139 return pci_iommu_ops->map_sg(hwdev, sg, nents, direction); 140} 141 142/* Unmap a set of streaming mode DMA translations. 143 * Again, cpu read rules concerning calls here are the same as for 144 * pci_unmap_single() above. 145 */ 146static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction) 147{ 148 pci_iommu_ops->unmap_sg(hwdev, sg, nhwents, direction); 149} 150 151/* Make physical memory consistent for a single 152 * streaming mode DMA translation after a transfer. 153 * 154 * If you perform a pci_map_single() but wish to interrogate the 155 * buffer using the cpu, yet do not wish to teardown the PCI dma 156 * mapping, you must call this function before doing so. At the 157 * next point you give the PCI dma address back to the card, you 158 * must first perform a pci_dma_sync_for_device, and then the 159 * device again owns the buffer. 160 */ 161static inline void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction) 162{ 163 pci_iommu_ops->dma_sync_single_for_cpu(hwdev, dma_handle, size, direction); 164} 165 166static inline void 167pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, 168 size_t size, int direction) 169{ 170 /* No flushing needed to sync cpu writes to the device. */ 171 BUG_ON(direction == PCI_DMA_NONE); 172} 173 174/* Make physical memory consistent for a set of streaming 175 * mode DMA translations after a transfer. 176 * 177 * The same as pci_dma_sync_single_* but for a scatter-gather list, 178 * same rules and usage. 179 */ 180static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction) 181{ 182 pci_iommu_ops->dma_sync_sg_for_cpu(hwdev, sg, nelems, direction); 183} 184 185static inline void 186pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, 187 int nelems, int direction) 188{ 189 /* No flushing needed to sync cpu writes to the device. */ 190 BUG_ON(direction == PCI_DMA_NONE); 191} 192 193/* Return whether the given PCI device DMA address mask can 194 * be supported properly. For example, if your device can 195 * only drive the low 24-bits during PCI bus mastering, then 196 * you would pass 0x00ffffff as the mask to this function. 197 */ 198extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); 199 200/* PCI IOMMU mapping bypass support. */ 201 202/* PCI 64-bit addressing works for all slots on all controller 203 * types on sparc64. However, it requires that the device 204 * can drive enough of the 64 bits. 205 */ 206#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) 207#define PCI64_ADDR_BASE 0xfffc000000000000UL 208 209/* Usage of the pci_dac_foo interfaces is only valid if this 210 * test passes. 211 */ 212#define pci_dac_dma_supported(pci_dev, mask) \ 213 ((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0) 214 215static inline dma64_addr_t 216pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) 217{ 218 return (PCI64_ADDR_BASE + 219 __pa(page_address(page)) + offset); 220} 221 222static inline struct page * 223pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) 224{ 225 unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE; 226 227 return virt_to_page(__va(paddr)); 228} 229 230static inline unsigned long 231pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) 232{ 233 return (dma_addr & ~PAGE_MASK); 234} 235 236static inline void 237pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) 238{ 239 /* DAC cycle addressing does not make use of the 240 * PCI controller's streaming cache, so nothing to do. 241 */ 242} 243 244static inline void 245pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) 246{ 247 /* DAC cycle addressing does not make use of the 248 * PCI controller's streaming cache, so nothing to do. 249 */ 250} 251 252#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) 253 254static inline int pci_dma_mapping_error(dma_addr_t dma_addr) 255{ 256 return (dma_addr == PCI_DMA_ERROR_CODE); 257} 258 259#ifdef CONFIG_PCI 260static inline void pci_dma_burst_advice(struct pci_dev *pdev, 261 enum pci_dma_burst_strategy *strat, 262 unsigned long *strategy_parameter) 263{ 264 unsigned long cacheline_size; 265 u8 byte; 266 267 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 268 if (byte == 0) 269 cacheline_size = 1024; 270 else 271 cacheline_size = (int) byte * 4; 272 273 *strat = PCI_DMA_BURST_BOUNDARY; 274 *strategy_parameter = cacheline_size; 275} 276#endif 277 278/* Return the index of the PCI controller for device PDEV. */ 279 280extern int pci_domain_nr(struct pci_bus *bus); 281static inline int pci_proc_domain(struct pci_bus *bus) 282{ 283 return 1; 284} 285 286/* Platform support for /proc/bus/pci/X/Y mmap()s. */ 287 288#define HAVE_PCI_MMAP 289#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA 290#define get_pci_unmapped_area get_fb_unmapped_area 291 292extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 293 enum pci_mmap_state mmap_state, 294 int write_combine); 295 296extern void 297pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 298 struct resource *res); 299 300extern void 301pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 302 struct pci_bus_region *region); 303 304extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *); 305 306static inline void pcibios_add_platform_entries(struct pci_dev *dev) 307{ 308} 309 310static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 311{ 312 return PCI_IRQ_NONE; 313} 314 315struct device_node; 316extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev); 317 318#endif /* __KERNEL__ */ 319 320#endif /* __SPARC64_PCI_H */ 321