1/* $Id: irq.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * irq.h: IRQ registers on the Sparc. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7#ifndef _SPARC_IRQ_H 8#define _SPARC_IRQ_H 9 10#include <linux/linkage.h> 11#include <linux/threads.h> /* For NR_CPUS */ 12#include <linux/interrupt.h> 13 14#include <asm/system.h> /* For SUN4M_NCPUS */ 15#include <asm/btfixup.h> 16 17#define __irq_ino(irq) irq 18#define __irq_pil(irq) irq 19 20#define NR_IRQS 16 21 22#define irq_canonicalize(irq) (irq) 23 24/* Dave Redman (djhr@tadpole.co.uk) 25 * changed these to function pointers.. it saves cycles and will allow 26 * the irq dependencies to be split into different files at a later date 27 * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size. 28 * Jakub Jelinek (jj@sunsite.mff.cuni.cz) 29 * Changed these to btfixup entities... It saves cycles :) 30 */ 31BTFIXUPDEF_CALL(void, disable_irq, unsigned int) 32BTFIXUPDEF_CALL(void, enable_irq, unsigned int) 33BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int) 34BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int) 35BTFIXUPDEF_CALL(void, clear_clock_irq, void) 36BTFIXUPDEF_CALL(void, clear_profile_irq, int) 37BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int) 38 39static inline void disable_irq_nosync(unsigned int irq) 40{ 41 BTFIXUP_CALL(disable_irq)(irq); 42} 43 44static inline void disable_irq(unsigned int irq) 45{ 46 BTFIXUP_CALL(disable_irq)(irq); 47} 48 49static inline void enable_irq(unsigned int irq) 50{ 51 BTFIXUP_CALL(enable_irq)(irq); 52} 53 54static inline void disable_pil_irq(unsigned int irq) 55{ 56 BTFIXUP_CALL(disable_pil_irq)(irq); 57} 58 59static inline void enable_pil_irq(unsigned int irq) 60{ 61 BTFIXUP_CALL(enable_pil_irq)(irq); 62} 63 64static inline void clear_clock_irq(void) 65{ 66 BTFIXUP_CALL(clear_clock_irq)(); 67} 68 69static inline void clear_profile_irq(int irq) 70{ 71 BTFIXUP_CALL(clear_profile_irq)(irq); 72} 73 74static inline void load_profile_irq(int cpu, int limit) 75{ 76 BTFIXUP_CALL(load_profile_irq)(cpu, limit); 77} 78 79extern void (*sparc_init_timers)(irq_handler_t lvl10_irq); 80extern void claim_ticker14(irq_handler_t irq_handler, 81 int irq, 82 unsigned int timeout); 83 84#ifdef CONFIG_SMP 85BTFIXUPDEF_CALL(void, set_cpu_int, int, int) 86BTFIXUPDEF_CALL(void, clear_cpu_int, int, int) 87BTFIXUPDEF_CALL(void, set_irq_udt, int) 88 89#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level) 90#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level) 91#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu) 92#endif 93 94extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname); 95 96/* On the sun4m, just like the timers, we have both per-cpu and master 97 * interrupt registers. 98 */ 99 100/* These registers are used for sending/receiving irqs from/to 101 * different cpu's. 102 */ 103struct sun4m_intreg_percpu { 104 unsigned int tbt; /* Interrupts still pending for this cpu. */ 105 106 /* These next two registers are WRITE-ONLY and are only 107 * "on bit" sensitive, "off bits" written have NO affect. 108 */ 109 unsigned int clear; /* Clear this cpus irqs here. */ 110 unsigned int set; /* Set this cpus irqs here. */ 111 unsigned char space[PAGE_SIZE - 12]; 112}; 113 114/* 115 * djhr 116 * Actually the clear and set fields in this struct are misleading.. 117 * according to the SLAVIO manual (and the same applies for the SEC) 118 * the clear field clears bits in the mask which will ENABLE that IRQ 119 * the set field sets bits in the mask to DISABLE the IRQ. 120 * 121 * Also the undirected_xx address in the SLAVIO is defined as 122 * RESERVED and write only.. 123 * 124 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor 125 * sun4m machines, for MP the layout makes more sense. 126 */ 127struct sun4m_intregs { 128 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS]; 129 unsigned int tbt; /* IRQ's that are still pending. */ 130 unsigned int irqs; /* Master IRQ bits. */ 131 132 /* Again, like the above, two these registers are WRITE-ONLY. */ 133 unsigned int clear; /* Clear master IRQ's by setting bits here. */ 134 unsigned int set; /* Set master IRQ's by setting bits here. */ 135 136 /* This register is both READ and WRITE. */ 137 unsigned int undirected_target; /* Which cpu gets undirected irqs. */ 138}; 139 140extern struct sun4m_intregs *sun4m_interrupts; 141 142/* 143 * Bit field defines for the interrupt registers on various 144 * Sparc machines. 145 */ 146 147/* The sun4c interrupt register. */ 148#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */ 149#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */ 150#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */ 151#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */ 152#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */ 153#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ 154#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ 155 156/* Dave Redman (djhr@tadpole.co.uk) 157 * The sun4m interrupt registers. 158 */ 159#define SUN4M_INT_ENABLE 0x80000000 160#define SUN4M_INT_E14 0x00000080 161#define SUN4M_INT_E10 0x00080000 162 163#define SUN4M_HARD_INT(x) (0x000000001 << (x)) 164#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) 165 166#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ 167#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ 168#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */ 169#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */ 170#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ 171#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ 172#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ 173#define SUN4M_INT_REALTIME 0x00080000 /* system timer */ 174#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ 175#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ 176#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ 177#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ 178#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ 179#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ 180 181#define SUN4M_INT_SBUS(x) (1 << (x+7)) 182#define SUN4M_INT_VME(x) (1 << (x)) 183 184#endif 185