1/* $Id: dma.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * include/asm-sparc/dma.h 3 * 4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7#ifndef _ASM_SPARC_DMA_H 8#define _ASM_SPARC_DMA_H 9 10#include <linux/kernel.h> 11#include <linux/types.h> 12 13#include <asm/vac-ops.h> /* for invalidate's, etc. */ 14#include <asm/sbus.h> 15#include <asm/delay.h> 16#include <asm/oplib.h> 17#include <asm/system.h> 18#include <asm/io.h> 19#include <linux/spinlock.h> 20 21struct page; 22extern spinlock_t dma_spin_lock; 23 24static __inline__ unsigned long claim_dma_lock(void) 25{ 26 unsigned long flags; 27 spin_lock_irqsave(&dma_spin_lock, flags); 28 return flags; 29} 30 31static __inline__ void release_dma_lock(unsigned long flags) 32{ 33 spin_unlock_irqrestore(&dma_spin_lock, flags); 34} 35 36/* These are irrelevant for Sparc DMA, but we leave it in so that 37 * things can compile. 38 */ 39#define MAX_DMA_CHANNELS 8 40#define MAX_DMA_ADDRESS (~0UL) 41#define DMA_MODE_READ 1 42#define DMA_MODE_WRITE 2 43 44/* Useful constants */ 45#define SIZE_16MB (16*1024*1024) 46#define SIZE_64K (64*1024) 47 48/* SBUS DMA controller reg offsets */ 49#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ 50#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */ 51#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */ 52#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */ 53 54/* DVMA chip revisions */ 55enum dvma_rev { 56 dvmarev0, 57 dvmaesc1, 58 dvmarev1, 59 dvmarev2, 60 dvmarev3, 61 dvmarevplus, 62 dvmahme 63}; 64 65#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) 66 67/* Linux DMA information structure, filled during probe. */ 68struct sbus_dma { 69 struct sbus_dma *next; 70 struct sbus_dev *sdev; 71 void __iomem *regs; 72 73 /* Status, misc info */ 74 int node; /* Prom node for this DMA device */ 75 int running; /* Are we doing DMA now? */ 76 int allocated; /* Are we "owned" by anyone yet? */ 77 78 /* Transfer information. */ 79 unsigned long addr; /* Start address of current transfer */ 80 int nbytes; /* Size of current transfer */ 81 int realbytes; /* For splitting up large transfers, etc. */ 82 83 /* DMA revision */ 84 enum dvma_rev revision; 85}; 86 87extern struct sbus_dma *dma_chain; 88 89/* Broken hardware... */ 90#ifdef CONFIG_SUN4 91/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken? 92 * Or is rev0 present only on sun4 boxes? -jj */ 93#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1) 94#else 95#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) 96#endif 97#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) 98 99/* Main routines in dma.c */ 100extern void dvma_init(struct sbus_bus *); 101 102/* Fields in the cond_reg register */ 103/* First, the version identification bits */ 104#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ 105#define DMA_VERS0 0x00000000 /* Sunray DMA version */ 106#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ 107#define DMA_VERS1 0x80000000 /* DMA rev 1 */ 108#define DMA_VERS2 0xa0000000 /* DMA rev 2 */ 109#define DMA_VERHME 0xb0000000 /* DMA hme gate array */ 110#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ 111 112#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ 113#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ 114#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ 115#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ 116#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ 117#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ 118#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ 119#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ 120#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ 121#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */ 122#define DMA_ST_WRITE 0x00000100 /* write from device to memory */ 123#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ 124#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ 125#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ 126#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ 127#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ 128#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ 129#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ 130#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */ 131#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ 132#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ 133#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ 134#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ 135#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */ 136#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */ 137#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */ 138#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ 139#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ 140#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */ 141#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */ 142#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ 143#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ 144#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ 145#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ 146#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ 147#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ 148#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ 149#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ 150#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */ 151#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ 152#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ 153#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ 154#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */ 155 156/* Values describing the burst-size property from the PROM */ 157#define DMA_BURST1 0x01 158#define DMA_BURST2 0x02 159#define DMA_BURST4 0x04 160#define DMA_BURST8 0x08 161#define DMA_BURST16 0x10 162#define DMA_BURST32 0x20 163#define DMA_BURST64 0x40 164#define DMA_BURSTBITS 0x7f 165 166/* Determine highest possible final transfer address given a base */ 167#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) 168 169/* Yes, I hack a lot of elisp in my spare time... */ 170#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) 171#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) 172#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) 173#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) 174#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) 175#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) 176#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) 177#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) 178#define DMA_BEGINDMA_W(regs) \ 179 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) 180#define DMA_BEGINDMA_R(regs) \ 181 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) 182 183/* For certain DMA chips, we need to disable ints upon irq entry 184 * and turn them back on when we are done. So in any ESP interrupt 185 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT 186 * when leaving the handler. You have been warned... 187 */ 188#define DMA_IRQ_ENTRY(dma, dregs) do { \ 189 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ 190 } while (0) 191 192#define DMA_IRQ_EXIT(dma, dregs) do { \ 193 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ 194 } while(0) 195 196 197#define for_each_dvma(dma) \ 198 for((dma) = dma_chain; (dma); (dma) = (dma)->next) 199 200extern int get_dma_list(char *); 201extern int request_dma(unsigned int, __const__ char *); 202extern void free_dma(unsigned int); 203 204/* From PCI */ 205 206#ifdef CONFIG_PCI 207extern int isa_dma_bridge_buggy; 208#else 209#define isa_dma_bridge_buggy (0) 210#endif 211 212/* Routines for data transfer buffers. */ 213BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long) 214BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long) 215 216#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len) 217#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len) 218 219/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */ 220BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus) 221BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus) 222BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus) 223BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus) 224 225#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus) 226#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus) 227#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus) 228#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus) 229 230/* 231 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep. 232 * 233 * The mmu_map_dma_area establishes two mappings in one go. 234 * These mappings point to pages normally mapped at 'va' (linear address). 235 * First mapping is for CPU visible address at 'a', uncached. 236 * This is an alias, but it works because it is an uncached mapping. 237 * Second mapping is for device visible address, or "bus" address. 238 * The bus address is returned at '*pba'. 239 * 240 * These functions seem distinct, but are hard to split. On sun4c, 241 * at least for now, 'a' is equal to bus address, and retured in *pba. 242 * On sun4m, page attributes depend on the CPU type, so we have to 243 * know if we are mapping RAM or I/O, so it has to be an additional argument 244 * to a separate mapping function for CPU visible mappings. 245 */ 246BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len) 247BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa) 248BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len) 249 250#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len) 251#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len) 252#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba) 253 254#endif /* !(_ASM_SPARC_DMA_H) */ 255