1/* 2 * include/asm-sh/cpu-sh4/mmu_context.h 3 * 4 * Copyright (C) 1999 Niibe Yutaka 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H 11#define __ASM_CPU_SH4_MMU_CONTEXT_H 12 13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ 14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 15#define MMU_TTB 0xFF000008 /* Translation table base register */ 16#define MMU_TEA 0xFF00000C /* TLB Exception Address */ 17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ 18 19#define MMUCR 0xFF000010 /* MMU Control Register */ 20 21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 23#define MMU_PAGE_ASSOC_BIT 0x80 24 25#define MMU_NTLB_ENTRIES 64 /* for 7750 */ 26#ifdef CONFIG_SH_STORE_QUEUES 27#define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */ 28#else 29#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ 30#endif 31 32#define MMU_ITLB_DATA_ARRAY 0xF3000000 33#define MMU_UTLB_DATA_ARRAY 0xF7000000 34 35#define MMU_UTLB_ENTRIES 64 36#define MMU_U_ENTRY_SHIFT 8 37#define MMU_UTLB_VALID 0x100 38#define MMU_ITLB_ENTRIES 4 39#define MMU_I_ENTRY_SHIFT 8 40#define MMU_ITLB_VALID 0x100 41 42#define TRA 0xff000020 43#define EXPEVT 0xff000024 44#define INTEVT 0xff000028 45 46#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 47