1#ifndef __ASM_POWERPC_CPUTABLE_H 2#define __ASM_POWERPC_CPUTABLE_H 3 4#include <asm/asm-compat.h> 5 6#define PPC_FEATURE_32 0x80000000 7#define PPC_FEATURE_64 0x40000000 8#define PPC_FEATURE_601_INSTR 0x20000000 9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 10#define PPC_FEATURE_HAS_FPU 0x08000000 11#define PPC_FEATURE_HAS_MMU 0x04000000 12#define PPC_FEATURE_HAS_4xxMAC 0x02000000 13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 14#define PPC_FEATURE_HAS_SPE 0x00800000 15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 17#define PPC_FEATURE_NO_TB 0x00100000 18#define PPC_FEATURE_POWER4 0x00080000 19#define PPC_FEATURE_POWER5 0x00040000 20#define PPC_FEATURE_POWER5_PLUS 0x00020000 21#define PPC_FEATURE_CELL 0x00010000 22#define PPC_FEATURE_BOOKE 0x00008000 23#define PPC_FEATURE_SMT 0x00004000 24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 25#define PPC_FEATURE_ARCH_2_05 0x00001000 26#define PPC_FEATURE_PA6T 0x00000800 27#define PPC_FEATURE_HAS_DFP 0x00000400 28#define PPC_FEATURE_POWER6_EXT 0x00000200 29 30#define PPC_FEATURE_TRUE_LE 0x00000002 31#define PPC_FEATURE_PPC_LE 0x00000001 32 33#ifdef __KERNEL__ 34#ifndef __ASSEMBLY__ 35 36/* This structure can grow, it's real size is used by head.S code 37 * via the mkdefs mechanism. 38 */ 39struct cpu_spec; 40 41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 42typedef void (*cpu_restore_t)(void); 43 44enum powerpc_oprofile_type { 45 PPC_OPROFILE_INVALID = 0, 46 PPC_OPROFILE_RS64 = 1, 47 PPC_OPROFILE_POWER4 = 2, 48 PPC_OPROFILE_G4 = 3, 49 PPC_OPROFILE_BOOKE = 4, 50 PPC_OPROFILE_CELL = 5, 51 PPC_OPROFILE_PA6T = 6, 52}; 53 54enum powerpc_pmc_type { 55 PPC_PMC_DEFAULT = 0, 56 PPC_PMC_IBM = 1, 57 PPC_PMC_PA6T = 2, 58}; 59 60struct cpu_spec { 61 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 62 unsigned int pvr_mask; 63 unsigned int pvr_value; 64 65 char *cpu_name; 66 unsigned long cpu_features; /* Kernel features */ 67 unsigned int cpu_user_features; /* Userland features */ 68 69 /* cache line sizes */ 70 unsigned int icache_bsize; 71 unsigned int dcache_bsize; 72 73 /* number of performance monitor counters */ 74 unsigned int num_pmcs; 75 enum powerpc_pmc_type pmc_type; 76 77 /* this is called to initialize various CPU bits like L1 cache, 78 * BHT, SPD, etc... from head.S before branching to identify_machine 79 */ 80 cpu_setup_t cpu_setup; 81 /* Used to restore cpu setup on secondary processors and at resume */ 82 cpu_restore_t cpu_restore; 83 84 /* Used by oprofile userspace to select the right counters */ 85 char *oprofile_cpu_type; 86 87 /* Processor specific oprofile operations */ 88 enum powerpc_oprofile_type oprofile_type; 89 90 /* Bit locations inside the mmcra change */ 91 unsigned long oprofile_mmcra_sihv; 92 unsigned long oprofile_mmcra_sipr; 93 94 /* Bits to clear during an oprofile exception */ 95 unsigned long oprofile_mmcra_clear; 96 97 /* Name of processor class, for the ELF AT_PLATFORM entry */ 98 char *platform; 99}; 100 101extern struct cpu_spec *cur_cpu_spec; 102 103extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 104 105extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 106extern void do_feature_fixups(unsigned long value, void *fixup_start, 107 void *fixup_end); 108 109#endif /* __ASSEMBLY__ */ 110 111/* CPU kernel features */ 112 113/* Retain the 32b definitions all use bottom half of word */ 114#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) 115#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 116#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 117#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 118#define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 119#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 120#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 121#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080) 122#define CPU_FTR_601 ASM_CONST(0x0000000000000100) 123#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) 124#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 125#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 126#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 127#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 128#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 129#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) 130#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000) 131#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 132#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 133#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) 134#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 135#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 136#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 137#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 138 139/* 140 * Add the 64-bit processor unique features in the top half of the word; 141 * on 32-bit, make the names available but defined to be 0. 142 */ 143#ifdef __powerpc64__ 144#define LONG_ASM_CONST(x) ASM_CONST(x) 145#else 146#define LONG_ASM_CONST(x) 0 147#endif 148 149#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) 150#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000) 151#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000) 152#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000) 153#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 154#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 155#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 156#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 157#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000) 158#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) 159#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) 160#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 161#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 162#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 163#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 164#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 165 166#ifndef __ASSEMBLY__ 167 168#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \ 169 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ 170 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE) 171 172/* We only set the altivec features if the kernel was compiled with altivec 173 * support 174 */ 175#ifdef CONFIG_ALTIVEC 176#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 177#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 178#else 179#define CPU_FTR_ALTIVEC_COMP 0 180#define PPC_FEATURE_HAS_ALTIVEC_COMP 0 181#endif 182 183/* We need to mark all pages as being coherent if we're SMP or we 184 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires 185 * it for PCI "streaming/prefetch" to work properly. 186 */ 187#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_PPC_83xx) 188#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 189#else 190#define CPU_FTR_COMMON 0 191#endif 192 193/* The powersave features NAP & DOZE seems to confuse BDI when 194 debugging. So if a BDI is used, disable theses 195 */ 196#ifndef CONFIG_BDI_SWITCH 197#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 198#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 199#else 200#define CPU_FTR_MAYBE_CAN_DOZE 0 201#define CPU_FTR_MAYBE_CAN_NAP 0 202#endif 203 204#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 205 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 206 !defined(CONFIG_BOOKE)) 207 208#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) 209#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 211 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 212#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 213 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ 214 CPU_FTR_PPC_LE) 215#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 217 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 218#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 219 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 220 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 221 CPU_FTR_PPC_LE) 222#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 223 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 224 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 225 CPU_FTR_PPC_LE) 226#define CPU_FTRS_750CL (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 227 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 228 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 229 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 230#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 231 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 232 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 233 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) 234#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 235 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 236 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 237 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) 238#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 239 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 240 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 241 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 242#define CPU_FTRS_750GX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 243 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 244 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 245 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 246#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 247 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 248 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ 249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 250#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 251 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 252 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ 253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 254#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 255 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 257 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 258#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 259 CPU_FTR_USE_TB | \ 260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 261 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 262 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 263 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 264#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 265 CPU_FTR_USE_TB | \ 266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 267 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 269#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 270 CPU_FTR_USE_TB | \ 271 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 272 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ 273 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 274#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 275 CPU_FTR_USE_TB | \ 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 277 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 278 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 279 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 280#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 281 CPU_FTR_USE_TB | \ 282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 283 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 285 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 286#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 287 CPU_FTR_USE_TB | \ 288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 289 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 290 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 291 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) 292#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 293 CPU_FTR_USE_TB | \ 294 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 295 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 296 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 297 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 298#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 299 CPU_FTR_USE_TB | \ 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 301 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 302 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 303 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 304#define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 305 CPU_FTR_USE_TB | \ 306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 307 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 308 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 309 CPU_FTR_PPC_LE) 310#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 311 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 312#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 313 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) 314#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 315 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ 316 CPU_FTR_COMMON) 317#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 318 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ 319 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 320#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 321 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) 322#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) 323#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 324 CPU_FTR_NODSISRALIGN) 325#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 326 CPU_FTR_NODSISRALIGN) 327#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) 328#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 329 CPU_FTR_NODSISRALIGN) 330#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 331 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) 332#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 333 334/* 64-bit CPUs */ 335#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 336 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) 337#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 338 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ 339 CPU_FTR_MMCRA | CPU_FTR_CTRL) 340#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 342 CPU_FTR_MMCRA) 343#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 344 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 345 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) 346#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 347 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 348 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 349 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 350 CPU_FTR_PURR) 351#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 352 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 353 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 354 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 355 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 356 CPU_FTR_DSCR) 357#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 358 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 359 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 360 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG) 361#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 362 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ 363 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 364 CPU_FTR_PURR | CPU_FTR_REAL_LE) 365#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 366 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) 367 368#ifdef __powerpc64__ 369#define CPU_FTRS_POSSIBLE \ 370 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 371 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 372 CPU_FTRS_CELL | CPU_FTRS_PA6T) 373#else 374enum { 375 CPU_FTRS_POSSIBLE = 376#if CLASSIC_PPC 377 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 378 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 379 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 380 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 381 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 382 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 383 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 384 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 385 CPU_FTRS_CLASSIC32 | 386#else 387 CPU_FTRS_GENERIC_32 | 388#endif 389#ifdef CONFIG_8xx 390 CPU_FTRS_8XX | 391#endif 392#ifdef CONFIG_40x 393 CPU_FTRS_40X | 394#endif 395#ifdef CONFIG_44x 396 CPU_FTRS_44X | 397#endif 398#ifdef CONFIG_E200 399 CPU_FTRS_E200 | 400#endif 401#ifdef CONFIG_E500 402 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 403#endif 404 0, 405}; 406#endif /* __powerpc64__ */ 407 408#ifdef __powerpc64__ 409#define CPU_FTRS_ALWAYS \ 410 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 411 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 412 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 413#else 414enum { 415 CPU_FTRS_ALWAYS = 416#if CLASSIC_PPC 417 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 418 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 419 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 420 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 421 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 422 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 423 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 424 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 425 CPU_FTRS_CLASSIC32 & 426#else 427 CPU_FTRS_GENERIC_32 & 428#endif 429#ifdef CONFIG_8xx 430 CPU_FTRS_8XX & 431#endif 432#ifdef CONFIG_40x 433 CPU_FTRS_40X & 434#endif 435#ifdef CONFIG_44x 436 CPU_FTRS_44X & 437#endif 438#ifdef CONFIG_E200 439 CPU_FTRS_E200 & 440#endif 441#ifdef CONFIG_E500 442 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 443#endif 444 CPU_FTRS_POSSIBLE, 445}; 446#endif /* __powerpc64__ */ 447 448static inline int cpu_has_feature(unsigned long feature) 449{ 450 return (CPU_FTRS_ALWAYS & feature) || 451 (CPU_FTRS_POSSIBLE 452 & cur_cpu_spec->cpu_features 453 & feature); 454} 455 456#endif /* !__ASSEMBLY__ */ 457 458#ifdef __ASSEMBLY__ 459 460#define BEGIN_FTR_SECTION_NESTED(label) label: 461#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97) 462#define END_FTR_SECTION_NESTED(msk, val, label) \ 463 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) 464#define END_FTR_SECTION(msk, val) \ 465 END_FTR_SECTION_NESTED(msk, val, 97) 466 467#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) 468#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) 469#endif /* __ASSEMBLY__ */ 470 471#endif /* __KERNEL__ */ 472#endif /* __ASM_POWERPC_CPUTABLE_H */ 473