1#ifndef __ASM_PARISC_PCI_H 2#define __ASM_PARISC_PCI_H 3 4#include <asm/scatterlist.h> 5 6 7 8/* 9** HP PCI platforms generally support multiple bus adapters. 10** (workstations 1-~4, servers 2-~32) 11** 12** Newer platforms number the busses across PCI bus adapters *sparsely*. 13** E.g. 0, 8, 16, ... 14** 15** Under a PCI bus, most HP platforms support PPBs up to two or three 16** levels deep. See "Bit3" product line. 17*/ 18#define PCI_MAX_BUSSES 256 19 20 21/* To be used as: mdelay(pci_post_reset_delay); 22 * 23 * post_reset is the time the kernel should stall to prevent anyone from 24 * accessing the PCI bus once #RESET is de-asserted. 25 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 26 * this makes the boot time much longer than necessary. 27 * 20ms seems to work for all the HP PCI implementations to date. 28 */ 29#define pci_post_reset_delay 50 30 31 32/* 33** pci_hba_data (aka H2P_OBJECT in HP/UX) 34** 35** This is the "common" or "base" data structure which HBA drivers 36** (eg Dino or LBA) are required to place at the top of their own 37** platform_data structure. I've heard this called "C inheritance" too. 38** 39** Data needed by pcibios layer belongs here. 40*/ 41struct pci_hba_data { 42 void __iomem *base_addr; /* aka Host Physical Address */ 43 const struct parisc_device *dev; /* device from PA bus walk */ 44 struct pci_bus *hba_bus; /* primary PCI bus below HBA */ 45 int hba_num; /* I/O port space access "key" */ 46 struct resource bus_num; /* PCI bus numbers */ 47 struct resource io_space; /* PIOP */ 48 struct resource lmmio_space; /* bus addresses < 4Gb */ 49 struct resource elmmio_space; /* additional bus addresses < 4Gb */ 50 struct resource gmmio_space; /* bus addresses > 4Gb */ 51 52 /* NOTE: Dino code assumes it can use *all* of the lmmio_space, 53 * elmmio_space and gmmio_space as a contiguous array of 54 * resources. This #define represents the array size */ 55 #define DINO_MAX_LMMIO_RESOURCES 3 56 57 unsigned long lmmio_space_offset; /* CPU view - PCI view */ 58 void * iommu; /* IOMMU this device is under */ 59 /* REVISIT - spinlock to protect resources? */ 60 61 #define HBA_NAME_SIZE 16 62 char io_name[HBA_NAME_SIZE]; 63 char lmmio_name[HBA_NAME_SIZE]; 64 char elmmio_name[HBA_NAME_SIZE]; 65 char gmmio_name[HBA_NAME_SIZE]; 66}; 67 68#define HBA_DATA(d) ((struct pci_hba_data *) (d)) 69 70#define HBA_PORT_SPACE_BITS 16 71 72#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) 73#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) 74 75#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) 76#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) 77 78#ifdef CONFIG_64BIT 79#define PCI_F_EXTEND 0xffffffff00000000UL 80#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a) 81 82/* We need to know if an address is LMMMIO or GMMIO. 83 * LMMIO requires mangling and GMMIO we must use as-is. 84 */ 85static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a) 86{ 87 return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND); 88} 89 90/* 91** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses. 92** See pci.c for more conversions used by Generic PCI code. 93** 94** Platform characteristics/firmware guarantee that 95** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO 96** (2) PA_VIEW == IO_VIEW for GMMIO 97*/ 98#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \ 99 ? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \ 100 : (a)) /* GMMIO */ 101#define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \ 102 ? (a) + hba->lmmio_space_offset \ 103 : (a)) 104 105#else /* !CONFIG_64BIT */ 106 107#define PCI_BUS_ADDR(hba,a) (a) 108#define PCI_HOST_ADDR(hba,a) (a) 109#define PCI_F_EXTEND 0UL 110#define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */ 111 112#endif /* !CONFIG_64BIT */ 113 114/* 115** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus 116** (This eliminates some of the warnings). 117*/ 118struct pci_bus; 119struct pci_dev; 120 121/* 122 * If the PCI device's view of memory is the same as the CPU's view of memory, 123 * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use 124 * this boolean for bounce buffer decisions. 125 */ 126#ifdef CONFIG_PA20 127/* All PA-2.0 machines have an IOMMU. */ 128#define PCI_DMA_BUS_IS_PHYS 0 129#define parisc_has_iommu() do { } while (0) 130#else 131 132#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) 133extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ 134#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys 135#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) 136#else 137#define PCI_DMA_BUS_IS_PHYS 1 138#define parisc_has_iommu() do { } while (0) 139#endif 140 141#endif /* !CONFIG_PA20 */ 142 143 144/* 145** Most PCI devices (eg Tulip, NCR720) also export the same registers 146** to both MMIO and I/O port space. Due to poor performance of I/O Port 147** access under HP PCI bus adapters, strongly recommend the use of MMIO 148** address space. 149** 150** While I'm at it more PA programming notes: 151** 152** 1) MMIO stores (writes) are posted operations. This means the processor 153** gets an "ACK" before the write actually gets to the device. A read 154** to the same device (or typically the bus adapter above it) will 155** force in-flight write transaction(s) out to the targeted device 156** before the read can complete. 157** 158** 2) The Programmed I/O (PIO) data may not always be strongly ordered with 159** respect to DMA on all platforms. Ie PIO data can reach the processor 160** before in-flight DMA reaches memory. Since most SMP PA platforms 161** are I/O coherent, it generally doesn't matter...but sometimes 162** it does. 163** 164** I've helped device driver writers debug both types of problems. 165*/ 166struct pci_port_ops { 167 u8 (*inb) (struct pci_hba_data *hba, u16 port); 168 u16 (*inw) (struct pci_hba_data *hba, u16 port); 169 u32 (*inl) (struct pci_hba_data *hba, u16 port); 170 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); 171 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); 172 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); 173}; 174 175 176struct pci_bios_ops { 177 void (*init)(void); 178 void (*fixup_bus)(struct pci_bus *bus); 179}; 180 181/* pci_unmap_{single,page} is not a nop, thus... */ 182#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 183 dma_addr_t ADDR_NAME; 184#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 185 __u32 LEN_NAME; 186#define pci_unmap_addr(PTR, ADDR_NAME) \ 187 ((PTR)->ADDR_NAME) 188#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 189 (((PTR)->ADDR_NAME) = (VAL)) 190#define pci_unmap_len(PTR, LEN_NAME) \ 191 ((PTR)->LEN_NAME) 192#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 193 (((PTR)->LEN_NAME) = (VAL)) 194 195/* 196** Stuff declared in arch/parisc/kernel/pci.c 197*/ 198extern struct pci_port_ops *pci_port; 199extern struct pci_bios_ops *pci_bios; 200 201#ifdef CONFIG_PCI 202extern void pcibios_register_hba(struct pci_hba_data *); 203extern void pcibios_set_master(struct pci_dev *); 204#else 205extern inline void pcibios_register_hba(struct pci_hba_data *x) 206{ 207} 208#endif 209 210/* 211 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() 212 * 0 == check if bridge is numbered before re-numbering. 213 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. 214 * 215 * We *should* set this to zero for "legacy" platforms and one 216 * for PAT platforms. 217 * 218 * But legacy platforms also need to renumber the busses below a Host 219 * Bus controller. Adding a 4-port Tulip card on the first PCI root 220 * bus of a C200 resulted in the secondary bus being numbered as 1. 221 * The second PCI host bus controller's root bus had already been 222 * assigned bus number 1 by firmware and sysfs complained. 223 * 224 * Firmware isn't doing anything wrong here since each controller 225 * is its own PCI domain. It's simpler and easier for us to renumber 226 * the busses rather than treat each Dino as a separate PCI domain. 227 * Eventually, we may want to introduce PCI domains for Superdome or 228 * rp7420/8420 boxes and then revisit this issue. 229 */ 230#define pcibios_assign_all_busses() (1) 231#define pcibios_scan_all_fns(a, b) (0) 232 233#define PCIBIOS_MIN_IO 0x10 234#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ 235 236/* Don't support DAC yet. */ 237#define pci_dac_dma_supported(pci_dev, mask) (0) 238 239/* export the pci_ DMA API in terms of the dma_ one */ 240#include <asm-generic/pci-dma-compat.h> 241 242#ifdef CONFIG_PCI 243static inline void pci_dma_burst_advice(struct pci_dev *pdev, 244 enum pci_dma_burst_strategy *strat, 245 unsigned long *strategy_parameter) 246{ 247 unsigned long cacheline_size; 248 u8 byte; 249 250 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 251 if (byte == 0) 252 cacheline_size = 1024; 253 else 254 cacheline_size = (int) byte * 4; 255 256 *strat = PCI_DMA_BURST_MULTIPLE; 257 *strategy_parameter = cacheline_size; 258} 259#endif 260 261extern void 262pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 263 struct resource *res); 264 265extern void 266pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 267 struct pci_bus_region *region); 268 269static inline struct resource * 270pcibios_select_root(struct pci_dev *pdev, struct resource *res) 271{ 272 struct resource *root = NULL; 273 274 if (res->flags & IORESOURCE_IO) 275 root = &ioport_resource; 276 if (res->flags & IORESOURCE_MEM) 277 root = &iomem_resource; 278 279 return root; 280} 281 282static inline void pcibios_add_platform_entries(struct pci_dev *dev) 283{ 284} 285 286static inline void pcibios_penalize_isa_irq(int irq, int active) 287{ 288 /* We don't need to penalize isa irq's */ 289} 290 291static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 292{ 293 return channel ? 15 : 14; 294} 295 296#endif /* __ASM_PARISC_PCI_H */ 297