1/* ********************************************************************* 2 * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package 3 * 4 * Register Definitions File: bcm1480_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the BCM1280 and BCM1480. 8 * 9 * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32#ifndef _BCM1480_REGS_H 33#define _BCM1480_REGS_H 34 35#include "sb1250_defs.h" 36 37/* ********************************************************************* 38 * Pull in the BCM1250's registers since a great deal of the 1480's 39 * functions are the same as the BCM1250. 40 ********************************************************************* */ 41 42#include "sb1250_regs.h" 43 44 45/* ********************************************************************* 46 * Some general notes: 47 * 48 * Register addresses are grouped by function and follow the order 49 * of the User Manual. 50 * 51 * For the most part, when there is more than one peripheral 52 * of the same type on the SOC, the constants below will be 53 * offsets from the base of each peripheral. For example, 54 * the MAC registers are described as offsets from the first 55 * MAC register, and there will be a MAC_REGISTER() macro 56 * to calculate the base address of a given MAC. 57 * 58 * The information in this file is based on the BCM1X55/BCM1X80 59 * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. 60 * 61 * This file is basically a "what's new" header file. Since the 62 * BCM1250 and the new BCM1480 (and derivatives) share many common 63 * features, this file contains only what's new or changed from 64 * the 1250. (above, you can see that we include the 1250 symbols 65 * to get the base functionality). 66 * 67 * In software, be sure to use the correct symbols, particularly 68 * for blocks that are different between the two chip families. 69 * All BCM1480-specific symbols have _BCM1480_ in their names, 70 * and all BCM1250-specific and "base" functions that are common in 71 * both chips have no special names (this is for compatibility with 72 * older include files). Therefore, if you're working with the 73 * SCD, which is very different on each chip, A_SCD_xxx implies 74 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 75 * version. 76 ********************************************************************* */ 77 78 79/* ********************************************************************* 80 * Memory Controller Registers (Section 6) 81 ********************************************************************* */ 82 83#define A_BCM1480_MC_BASE_0 0x0010050000 84#define A_BCM1480_MC_BASE_1 0x0010051000 85#define A_BCM1480_MC_BASE_2 0x0010052000 86#define A_BCM1480_MC_BASE_3 0x0010053000 87#define BCM1480_MC_REGISTER_SPACING 0x1000 88 89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) 90#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) 91 92#define R_BCM1480_MC_CONFIG 0x0000000100 93#define R_BCM1480_MC_CS_START 0x0000000120 94#define R_BCM1480_MC_CS_END 0x0000000140 95#define S_BCM1480_MC_CS_STARTEND 24 96 97#define R_BCM1480_MC_CS01_ROW0 0x0000000180 98#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 99#define R_BCM1480_MC_CS23_ROW0 0x0000000200 100#define R_BCM1480_MC_CS23_ROW1 0x0000000220 101#define R_BCM1480_MC_CS01_COL0 0x0000000280 102#define R_BCM1480_MC_CS01_COL1 0x00000002A0 103#define R_BCM1480_MC_CS23_COL0 0x0000000300 104#define R_BCM1480_MC_CS23_COL1 0x0000000320 105 106#define R_BCM1480_MC_CSX_BASE 0x0000000180 107#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ 108#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ 109#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ 110#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ 111#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ 112 113#define R_BCM1480_MC_CS01_BA 0x0000000380 114#define R_BCM1480_MC_CS23_BA 0x00000003A0 115#define R_BCM1480_MC_DRAMCMD 0x0000000400 116#define R_BCM1480_MC_DRAMMODE 0x0000000420 117#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 118#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG 119#define R_BCM1480_MC_TEST_DATA 0x0000000480 120#define R_BCM1480_MC_TEST_ECC 0x00000004A0 121#define R_BCM1480_MC_TIMING1 0x00000004C0 122#define R_BCM1480_MC_TIMING2 0x00000004E0 123#define R_BCM1480_MC_DLL_CFG 0x0000000500 124#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 125 126#if SIBYTE_HDR_FEATURE(1480, PASS2) 127#define R_BCM1480_MC_ODT 0x0000000460 128#define R_BCM1480_MC_ECC_STATUS 0x0000000540 129#endif 130 131/* Global registers (single instance) */ 132#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 133#define A_BCM1480_MC_GLB_INTLV 0x0010054120 134#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 135#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 136#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 137#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 138 139/* ********************************************************************* 140 * L2 Cache Control Registers (Section 5) 141 ********************************************************************* */ 142 143#define A_BCM1480_L2_BASE 0x0010040000 144 145#define A_BCM1480_L2_READ_TAG 0x0010040018 146#define A_BCM1480_L2_ECC_TAG 0x0010040038 147#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 148#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 149#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 150#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ 151#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ 152#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) 153#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ 154#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ 155#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) 156#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) 157#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) 158#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) 159#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ 160#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ 161#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ 162#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ 163#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ 164#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ 165#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) 166#define A_BCM1480_L2_BANK_BASE 0x00D0300000 167#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) 168#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 169 170 171/* ********************************************************************* 172 * PCI-X Interface Registers (Section 7) 173 ********************************************************************* */ 174 175#define A_BCM1480_PCI_BASE 0x0010061400 176 177#define A_BCM1480_PCI_RESET 0x0010061400 178#define A_BCM1480_PCI_DLL 0x0010061500 179 180#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 181 182/* ********************************************************************* 183 * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) 184 ********************************************************************* */ 185 186/* No register changes with Rev.C BCM1250, but one additional MAC */ 187 188#define A_BCM1480_MAC_BASE_2 0x0010066000 189 190#ifndef A_MAC_BASE_2 191#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 192#endif 193 194#define A_BCM1480_MAC_BASE_3 0x0010067000 195#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 196 197#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 198 199#ifndef R_MAC_DMA_OODPKTLOST 200#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST 201#endif 202 203 204/* ********************************************************************* 205 * DUART Registers (Section 14) 206 ********************************************************************* */ 207 208/* No significant differences from BCM1250, two DUARTs */ 209 210/* Conventions, per user manual: 211 * DUART generic, channels A,B,C,D 212 * DUART0 implementing channels A,B 213 * DUART1 inplementing channels C,D 214 */ 215 216#define BCM1480_DUART_NUM_PORTS 4 217 218#define A_BCM1480_DUART0 0x0010060000 219#define A_BCM1480_DUART1 0x0010060400 220#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) 221 222#define BCM1480_DUART_CHANREG_SPACING 0x100 223#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ 224 + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ 225 + (reg)) 226#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) 227 228#define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) 229#define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) 230 231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) 232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) 233#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT) 234 235/* 236 * These constants are the absolute addresses. 237 */ 238 239#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 240#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 241#define A_BCM1480_DUART_STATUS_C 0x0010060420 242#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 243#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 244#define A_BCM1480_DUART_CMD_C 0x0010060450 245#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 246#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 247#define A_BCM1480_DUART_OPCR_C 0x0010060480 248#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 249 250#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 251#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 252#define A_BCM1480_DUART_STATUS_D 0x0010060520 253#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 254#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 255#define A_BCM1480_DUART_CMD_D 0x0010060550 256#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 257#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 258#define A_BCM1480_DUART_OPCR_D 0x0010060580 259#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 260 261#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 262#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 263#define A_BCM1480_DUART_ISR_C 0x0010060620 264#define A_BCM1480_DUART_IMR_C 0x0010060630 265#define A_BCM1480_DUART_ISR_D 0x0010060640 266#define A_BCM1480_DUART_IMR_D 0x0010060650 267#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 268#define A_BCM1480_DUART_OPCR_CD 0x0010060670 269#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 270#define A_BCM1480_DUART_ISR_CD 0x0010060690 271#define A_BCM1480_DUART_IMR_CD 0x00100606A0 272#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 273#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 274#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 275#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 276 277 278/* ********************************************************************* 279 * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) 280 ********************************************************************* */ 281 282#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 283#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 284 285/* ********************************************************************* 286 * GPIO Registers (Section 17) 287 ********************************************************************* */ 288 289/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ 290 291#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 292#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) 293 294#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE 295#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE 296 297/* ********************************************************************* 298 * SMBus Registers (Section 18) 299 ********************************************************************* */ 300 301/* No changes from BCM1250 */ 302 303/* ********************************************************************* 304 * Timer Registers (Sections 4.6) 305 ********************************************************************* */ 306 307/* BCM1480 has two additional watchdogs */ 308 309/* Watchdog timers */ 310 311#define A_BCM1480_SCD_WDOG_2 0x0010022050 312#define A_BCM1480_SCD_WDOG_3 0x0010022150 313 314#define BCM1480_SCD_NUM_WDOGS 4 315 316#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) 317#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) 318 319#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 320#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 321#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 322 323#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 324#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 325#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 326 327/* BCM1480 has two additional compare registers */ 328 329#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT 330#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 331#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 332#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 333#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 334#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 335 336/* ********************************************************************* 337 * System Control Registers (Section 4.2) 338 ********************************************************************* */ 339 340/* Scratch register in different place */ 341 342#define A_BCM1480_SCD_SCRATCH 0x100200A0 343 344/* ********************************************************************* 345 * System Address Trap Registers (Section 4.9) 346 ********************************************************************* */ 347 348/* No changes from BCM1250 */ 349 350/* ********************************************************************* 351 * System Interrupt Mapper Registers (Sections 4.3-4.5) 352 ********************************************************************* */ 353 354#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 355#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 356#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 357#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 358#define BCM1480_IMR_REGISTER_SPACING 0x2000 359#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 360 361#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) 362#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) 363 364/* Most IMR registers are 128 bits, implemented as non-contiguous 365 64-bit registers high (_H) and low (_L) */ 366#define BCM1480_IMR_HL_SPACING 0x1000 367 368#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 369#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 370#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 371#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 372#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 373#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 374#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 375#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 376#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 377#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 378#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 379#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 380#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 381#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 382#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 383#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 384#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 385 386#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 387#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 388#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 389#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 390#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 391#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 392#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 393#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 394 395#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 396#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 397#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 398#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 399#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 400 401#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ 402 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) 403#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) 404 405#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 406#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 407 408/* 409 * these macros work together to build the address of a mailbox 410 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) 411 * for mbox_0_set_cpu2 returns 0x00100240C8 412 */ 413#define R_BCM1480_IMR_MAILBOX_CPU 0x00 414#define R_BCM1480_IMR_MAILBOX_SET 0x08 415#define R_BCM1480_IMR_MAILBOX_CLR 0x10 416#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 417#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ 418 (A_BCM1480_IMR_CPU0_BASE + \ 419 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ 420 (cpu * BCM1480_IMR_REGISTER_SPACING) + \ 421 (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) 422 423/* ********************************************************************* 424 * System Performance Counter Registers (Section 4.7) 425 ********************************************************************* */ 426 427/* BCM1480 has four more performance counter registers, and two control 428 registers. */ 429 430#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 431 432#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 433#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 434#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 435#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 436 437#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 438#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 439#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 440#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 441 442#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 443#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 444#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 445#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 446 447#define BCM1480_SCD_NUM_PERF_CNT 8 448#define BCM1480_SCD_PERF_CNT_SPACING 8 449#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING)) 450 451/* ********************************************************************* 452 * System Bus Watcher Registers (Section 4.8) 453 ********************************************************************* */ 454 455 456/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ 457 458#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 459 460/* ********************************************************************* 461 * System Debug Controller Registers (Section 19) 462 ********************************************************************* */ 463 464/* Same as 1250 */ 465 466/* ********************************************************************* 467 * System Trace Unit Registers (Sections 4.10) 468 ********************************************************************* */ 469 470/* Same as 1250 */ 471 472/* ********************************************************************* 473 * Data Mover DMA Registers (Section 10.7) 474 ********************************************************************* */ 475 476/* Same as 1250 */ 477 478 479/* ********************************************************************* 480 * HyperTransport Interface Registers (Section 8) 481 ********************************************************************* */ 482 483#define BCM1480_HT_NUM_PORTS 3 484#define BCM1480_HT_PORT_SPACING 0x800 485#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) 486 487#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 488#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 489#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 490#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 491 492 493/* ********************************************************************* 494 * Node Controller Registers (Section 9) 495 ********************************************************************* */ 496 497#define A_BCM1480_NC_BASE 0x00DFBD0000 498 499#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 500#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 501#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 502#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 503#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 504#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 505#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 506 507#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 508#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 509#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 510#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 511 512#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 513#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 514#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 515#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 516#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 517#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 518#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 519#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 520#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 521#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 522#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 523#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 524#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 525 526#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 527#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 528 529 530/* ********************************************************************* 531 * H&R Block Configuration Registers (Section 12.4) 532 ********************************************************************* */ 533 534#define A_BCM1480_HR_BASE_0 0x00DF820000 535#define A_BCM1480_HR_BASE_1 0x00DF8A0000 536#define A_BCM1480_HR_BASE_2 0x00DF920000 537#define BCM1480_HR_REGISTER_SPACING 0x80000 538 539#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) 540#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) 541 542#define R_BCM1480_HR_CFG 0x0000000000 543 544#define R_BCM1480_HR_MAPPING 0x0000010010 545 546#define BCM1480_HR_RULE_SPACING 0x0000000010 547#define BCM1480_HR_NUM_RULES 16 548#define BCM1480_HR_OP_OFFSET 0x0000000100 549#define BCM1480_HR_TYPE_OFFSET 0x0000000108 550#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 551#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 552 553#define BCM1480_HR_LEAF_SPACING 0x0000000010 554#define BCM1480_HR_NUM_LEAVES 10 555#define BCM1480_HR_LEAF_OFFSET 0x0000000300 556#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) 557 558#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 559 560#define BCM1480_HR_PATH_SPACING 0x0000000010 561#define BCM1480_HR_NUM_PATHS 16 562#define BCM1480_HR_PATH_OFFSET 0x0000000600 563#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) 564 565#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 566 567#define BCM1480_HR_ROUTE_SPACING 8 568#define BCM1480_HR_NUM_ROUTES 512 569#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 570#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) 571 572 573/* checked to here - ehs */ 574/* ********************************************************************* 575 * Packet Manager DMA Registers (Section 12.5) 576 ********************************************************************* */ 577 578#define A_BCM1480_PM_BASE 0x0010056000 579 580#define A_BCM1480_PMI_LCL_0 0x0010058000 581#define A_BCM1480_PMO_LCL_0 0x001005C000 582#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) 583#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) 584 585#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 586#define BCM1480_PM_NUM_CHANNELS 32 587 588#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 589#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) 590#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 591#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) 592 593#define BCM1480_PM_INT_PACKING 8 594#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 595#define BCM1480_PM_INT_NUM_FUNCTIONS 3 596 597/* 598 * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) 599 */ 600 601#define R_BCM1480_PM_BASE_SIZE 0x0000000000 602#define R_BCM1480_PM_CNT 0x0000000008 603#define R_BCM1480_PM_PFCNT 0x0000000010 604#define R_BCM1480_PM_LAST 0x0000000018 605#define R_BCM1480_PM_PFINDX 0x0000000020 606#define R_BCM1480_PM_INT_WMK 0x0000000028 607#define R_BCM1480_PM_CONFIG0 0x0000000030 608#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 609#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ 610#define R_BCM1480_PM_INT_CNFG 0x0000000088 611#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 612#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ 613#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ 614 615/* 616 * Global Registers (Not Channelized) 617 */ 618 619#define A_BCM1480_PMI_GLB_0 0x0010056000 620#define A_BCM1480_PMO_GLB_0 0x0010057000 621 622/* 623 * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 624 */ 625 626#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ 627 628#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) 629 630/* 631 * Interrupt mapping registers 632 */ 633 634 635#define A_BCM1480_PMI_INT_0 0x0010056800 636#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) 637#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) 638#define A_BCM1480_PMO_INT_0 0x0010057800 639#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) 640#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) 641 642/* 643 * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 644 */ 645 646#define R_BCM1480_PM_INT_ST 0x0000000000 647#define R_BCM1480_PM_INT_MSK 0x0000000040 648#define R_BCM1480_PM_INT_CLR 0x0000000080 649#define R_BCM1480_PM_MRGD_INT 0x00000000C0 650 651/* 652 * Debug registers (global) 653 */ 654 655#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 656#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 657#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 658#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 659#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 660#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 661 662/* ********************************************************************* 663 * Switch performance counters 664 ********************************************************************* */ 665 666#define A_BCM1480_SWPERF_CFG 0xdfb91800 667#define A_BCM1480_SWPERF_CNT0 0xdfb91880 668#define A_BCM1480_SWPERF_CNT1 0xdfb91888 669#define A_BCM1480_SWPERF_CNT2 0xdfb91890 670#define A_BCM1480_SWPERF_CNT3 0xdfb91898 671 672 673/* ********************************************************************* 674 * Switch Trace Unit 675 ********************************************************************* */ 676 677#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 678#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 679#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 680#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 681#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 682#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 683#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 684 685#define A_BCM1480_SWTRC_CFG 0xDFB91500 686#define A_BCM1480_SWTRC_READ 0xDFB91508 687 688#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 689 690#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) 691#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) 692#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) 693 694#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) 695#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) 696#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) 697#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) 698 699 700 701/* ********************************************************************* 702 * High-Speed Port Registers (Section 13) 703 ********************************************************************* */ 704 705#define A_BCM1480_HSP_BASE_0 0x00DF810000 706#define A_BCM1480_HSP_BASE_1 0x00DF890000 707#define A_BCM1480_HSP_BASE_2 0x00DF910000 708#define BCM1480_HSP_REGISTER_SPACING 0x80000 709 710#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) 711#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) 712 713#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 714#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 715#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 716#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 717#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 718#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 719 720#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 721#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 722 723#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 724#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 725#define R_BCM1480_HSP_RX_TEST 0x0000000810 726#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 727#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 728#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 729#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 730#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 731 732#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 733 734#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 735#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 736#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 737#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 738#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 739#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 740#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 741#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 742#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) 743 744#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 745#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 746#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 747#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 748#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 749#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 750 751#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 752#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 753#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 754#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 755#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 756#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 757#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 758#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 759#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) 760 761#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 762#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 763#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 764#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 765#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 766#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 767#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 768 769#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 770#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 771#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 772 773#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 774#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 775#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 776#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 777#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 778#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 779#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 780#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 781#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) 782#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 783#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 784#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 785#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 786#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 787#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 788 789#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 790#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 791#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 792#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 793#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) 794#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 795#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 796 797#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 798#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 799#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 800#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 801#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) 802#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 803#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 804 805#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 806#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 807 808#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 809#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 810#define R_BCM1480_HSP_TX_TEST 0x0000040810 811 812#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 813#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 814#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 815#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 816#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 817#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 818#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 819 820#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 821#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 822 823#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 824#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) 825 826 827 828/* ********************************************************************* 829 * Physical Address Map (Table 10 and Figure 7) 830 ********************************************************************* */ 831 832#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 833#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 834#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 835#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 836#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) 837#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) 838#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) 839#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) 840#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) 841#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) 842#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) 843#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) 844#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) 845#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) 846#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 847#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 848#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) 849#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) 850#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) 851#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) 852#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) 853#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) 854#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 855#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 856#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 857#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 858#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 859#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) 860#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 861#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 862#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 863#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 864#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 865#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) 866#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) 867#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) 868#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) 869#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) 870 871 872/* ********************************************************************* 873 * L2 Cache as RAM (Table 54) 874 ********************************************************************* */ 875 876#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 877#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 878#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) 879#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) 880#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) 881#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) 882#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) 883#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) 884#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) 885#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) 886#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) 887 888#endif /* _BCM1480_REGS_H */ 889