1/* 2 * Defines for the TJSYS JMR-TX3927 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000-2001 Toshiba Corporation 9 */ 10#ifndef __ASM_TX3927_JMR3927_H 11#define __ASM_TX3927_JMR3927_H 12 13#include <asm/jmr3927/tx3927.h> 14#include <asm/addrspace.h> 15#include <asm/system.h> 16 17/* CS */ 18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 19#define JMR3927_ROMCE1 0x1e000000 /* 4M */ 20#define JMR3927_ROMCE2 0x14000000 /* 16M */ 21#define JMR3927_ROMCE3 0x10000000 /* 64M */ 22#define JMR3927_ROMCE5 0x1d000000 /* 4M */ 23#define JMR3927_SDCS0 0x00000000 /* 32M */ 24#define JMR3927_SDCS1 0x02000000 /* 32M */ 25/* PCI Direct Mappings */ 26 27#define JMR3927_PCIMEM 0x08000000 28#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ 29#define JMR3927_PCIIO 0x15000000 30#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ 31 32#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ 33#define JMR3927_PORT_BASE KSEG1 34 35/* Address map (virtual address) */ 36#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) 37#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) 38#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) 39#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) 40#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) 41 42#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) 43#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) 44#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) 45#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) 46#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) 47#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) 48#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) 49#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) 50#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) 51#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) 52#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) 53 54/* Flash ROM */ 55#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) 56#define JMR3927_FLASH_SIZE 0x00400000 57 58/* bits for IOC_REV/IOC_BREV (high byte) */ 59#define JMR3927_IDT_MASK 0xfc 60#define JMR3927_REV_MASK 0x03 61#define JMR3927_IOC_IDT 0xe0 62 63/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ 64#define JMR3927_IOC_INTB_PCIA 0 65#define JMR3927_IOC_INTB_PCIB 1 66#define JMR3927_IOC_INTB_PCIC 2 67#define JMR3927_IOC_INTB_PCID 3 68#define JMR3927_IOC_INTB_MODEM 4 69#define JMR3927_IOC_INTB_INT6 5 70#define JMR3927_IOC_INTB_INT7 6 71#define JMR3927_IOC_INTB_SOFT 7 72#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) 73#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) 74#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) 75#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) 76#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) 77#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) 78#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) 79#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) 80 81/* bits for IOC_RESET (high byte) */ 82#define JMR3927_IOC_RESET_CPU 1 83#define JMR3927_IOC_RESET_PCI 2 84 85#if defined(__BIG_ENDIAN) 86#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) 87#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) 88#elif defined(__LITTLE_ENDIAN) 89#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) 90#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) 91#else 92#error "No Endian" 93#endif 94 95/* LED macro */ 96#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) 97 98#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) 99 100/* DIPSW4 macro */ 101#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0) 102#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) 103#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) 104#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) 105 106/* 107 * IRQ mappings 108 */ 109 110/* These are the virtual IRQ numbers, we divide all IRQ's into 111 * 'spaces', the 'space' determines where and how to enable/disable 112 * that particular IRQ on an JMR machine. Add new 'spaces' as new 113 * IRQ hardware is supported. 114 */ 115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 117 118#define JMR3927_IRQ_IRC 16 119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 121 122#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) 123#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) 124#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) 125#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) 126#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) 127#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) 128#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) 129#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) 130#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) 131#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) 132#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) 133#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) 134#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) 135#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1) 136#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2) 137#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) 138#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) 139#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) 140#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) 141#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) 142#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) 143#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) 144#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) 145 146/* IOC (PCI, MODEM) */ 147#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 148/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 149#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 150/* Clock Tick (10ms) */ 151#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 152 153/* Clocks */ 154#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 155#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ 156#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ 157 158#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */ 159 160 161/* 162 * TX3927 Pin Configuration: 163 * 164 * PCFG bits Avail Dead 165 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] 166 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] 167 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, 168 * GDBGE* PIO[2:1] 169 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] 170 * SELTMR[2:0]:000 TIMER[1:0] 171 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], 172 * DMAREQ[1],DMAACK[1] 173 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] 174 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] 175 * SELDONE:1 DMADONE PIO[7] 176 * 177 * Usable pins are: 178 * RXD[1;0],TXD[1:0],CTS[0],RTS[0], 179 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] 180 * INT[3:0] 181 */ 182 183#endif /* __ASM_TX3927_JMR3927_H */ 184