1/****************************************************************************/
2
3/*
4 *	m532xsim.h -- ColdFire 5329 registers
5 */
6
7/****************************************************************************/
8#ifndef	m532xsim_h
9#define	m532xsim_h
10/****************************************************************************/
11
12#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
13#define MCF_REG16(x) (*(volatile unsigned short *)(x))
14#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
15
16#define MCFINT_VECBASE      64
17#define MCFINT_UART0        26          /* Interrupt number for UART0 */
18#define MCFINT_UART1        27          /* Interrupt number for UART1 */
19
20#define MCF_WTM_WCR	MCF_REG16(0xFC098000)
21
22/*
23 *	Define the 532x SIM register set addresses.
24 */
25#define	MCFSIM_IPRL		0xFC048004
26#define	MCFSIM_IPRH		0xFC048000
27#define	MCFSIM_IPR		MCFSIM_IPRL
28#define	MCFSIM_IMRL		0xFC04800C
29#define	MCFSIM_IMRH		0xFC048008
30#define	MCFSIM_IMR		MCFSIM_IMRL
31#define	MCFSIM_ICR0		0xFC048040
32#define	MCFSIM_ICR1		0xFC048041
33#define	MCFSIM_ICR2		0xFC048042
34#define	MCFSIM_ICR3		0xFC048043
35#define	MCFSIM_ICR4		0xFC048044
36#define	MCFSIM_ICR5		0xFC048045
37#define	MCFSIM_ICR6		0xFC048046
38#define	MCFSIM_ICR7		0xFC048047
39#define	MCFSIM_ICR8		0xFC048048
40#define	MCFSIM_ICR9		0xFC048049
41#define	MCFSIM_ICR10		0xFC04804A
42#define	MCFSIM_ICR11		0xFC04804B
43
44/*
45 *	Some symbol defines for the above...
46 */
47#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
48#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
49#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
50#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
51#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
52#define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
53#define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
54#define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
55#define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */
56
57
58#define	MCFSIM_IMR_MASKALL	0xFFFFFFFF	/* All SIM intr sources */
59
60#define MCFSIM_IMR_SIMR0	0xFC04801C
61#define MCFSIM_IMR_SIMR1	0xFC04C01C
62#define MCFSIM_IMR_CIMR0	0xFC04801D
63#define MCFSIM_IMR_CIMR1	0xFC04C01D
64
65#define MCFSIM_ICR_TIMER1	(0xFC048040+32)
66#define MCFSIM_ICR_TIMER2	(0xFC048040+33)
67
68
69/*
70 *	Macro to set IMR register. It is 32 bits on the 5307.
71 */
72#define	mcf_getimr()		\
73	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
74
75#define	mcf_setimr(imr)		\
76	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
77
78#define	mcf_getipr()		\
79	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
80
81#define	mcf_getiprl()		\
82	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
83
84#define	mcf_getiprh()		\
85	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
86
87
88#define mcf_enable_irq0(irq)		\
89	*((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
90
91#define mcf_enable_irq1(irq)		\
92	*((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
93
94#define mcf_disable_irq0(irq)		\
95	*((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
96
97#define mcf_disable_irq1(irq)		\
98	*((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
99
100/*
101 *	Define the Cache register flags.
102 */
103#define	CACR_EC			(1<<31)
104#define	CACR_ESB		(1<<29)
105#define	CACR_DPI		(1<<28)
106#define	CACR_HLCK		(1<<27)
107#define	CACR_CINVA		(1<<24)
108#define	CACR_DNFB		(1<<10)
109#define	CACR_DCM_WTHRU		(0<<8)
110#define	CACR_DCM_WBACK		(1<<8)
111#define	CACR_DCM_OFF_PRE	(2<<8)
112#define	CACR_DCM_OFF_IMP	(3<<8)
113#define	CACR_DW			(1<<5)
114
115#define	ACR_BASE_POS		24
116#define	ACR_MASK_POS		16
117#define	ACR_ENABLE		(1<<15)
118#define	ACR_USER		(0<<13)
119#define	ACR_SUPER		(1<<13)
120#define	ACR_ANY			(2<<13)
121#define	ACR_CM_WTHRU		(0<<5)
122#define	ACR_CM_WBACK		(1<<5)
123#define	ACR_CM_OFF_PRE		(2<<5)
124#define	ACR_CM_OFF_IMP		(3<<5)
125#define	ACR_WPROTECT		(1<<2)
126
127/*********************************************************************
128 *
129 * Inter-IC (I2C) Module
130 *
131 *********************************************************************/
132
133/* Read/Write access macros for general use */
134#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address
135#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
136#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
137#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
138#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O
139
140/* Bit level definitions and macros */
141#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)
142
143#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))
144
145#define MCF532x_I2C_I2CR_IEN    (0x80)	// I2C enable
146#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
147#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
148#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
149#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
150#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
151
152#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
153#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
154#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
155#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
156#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
157#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
158#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
159
160#define MCF532x_PAR_FECI2C	(volatile u8 *) (0xFC0A4053)
161
162
163/*
164 *	The M5329EVB board needs a help getting its devices initialized
165 *	at kernel start time if dBUG doesn't set it up (for example
166 *	it is not used), so we need to do it manually.
167 */
168#ifdef __ASSEMBLER__
169.macro m5329EVB_setup
170	movel	#0xFC098000, %a7
171	movel	#0x0, (%a7)
172#define CORE_SRAM	0x80000000
173#define CORE_SRAM_SIZE	0x8000
174	movel	#CORE_SRAM, %d0
175	addl	#0x221, %d0
176	movec	%d0,%RAMBAR1
177	movel	#CORE_SRAM, %sp
178	addl	#CORE_SRAM_SIZE, %sp
179	jsr	sysinit
180.endm
181#define	PLATFORM_SETUP	m5329EVB_setup
182
183#endif /* __ASSEMBLER__ */
184
185/*********************************************************************
186 *
187 * Chip Configuration Module (CCM)
188 *
189 *********************************************************************/
190
191/* Register read/write macros */
192#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
193#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
194#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
195#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
196#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
197#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
198#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)
199
200/* Bit definitions and macros for MCF_CCM_CCR */
201#define MCF_CCM_CCR_RESERVED      (0x0001)
202#define MCF_CCM_CCR_PLL_MODE      (0x0003)
203#define MCF_CCM_CCR_OSC_MODE      (0x0005)
204#define MCF_CCM_CCR_BOOTPS(x)     (((x)&0x0003)<<3|0x0001)
205#define MCF_CCM_CCR_LOAD          (0x0021)
206#define MCF_CCM_CCR_LIMP          (0x0041)
207#define MCF_CCM_CCR_CSC(x)        (((x)&0x0003)<<8|0x0001)
208
209/* Bit definitions and macros for MCF_CCM_RCON */
210#define MCF_CCM_RCON_RESERVED     (0x0001)
211#define MCF_CCM_RCON_PLL_MODE     (0x0003)
212#define MCF_CCM_RCON_OSC_MODE     (0x0005)
213#define MCF_CCM_RCON_BOOTPS(x)    (((x)&0x0003)<<3|0x0001)
214#define MCF_CCM_RCON_LOAD         (0x0021)
215#define MCF_CCM_RCON_LIMP         (0x0041)
216#define MCF_CCM_RCON_CSC(x)       (((x)&0x0003)<<8|0x0001)
217
218/* Bit definitions and macros for MCF_CCM_CIR */
219#define MCF_CCM_CIR_PRN(x)        (((x)&0x003F)<<0)
220#define MCF_CCM_CIR_PIN(x)        (((x)&0x03FF)<<6)
221
222/* Bit definitions and macros for MCF_CCM_MISCCR */
223#define MCF_CCM_MISCCR_USBSRC     (0x0001)
224#define MCF_CCM_MISCCR_USBDIV     (0x0002)
225#define MCF_CCM_MISCCR_SSI_SRC    (0x0010)
226#define MCF_CCM_MISCCR_TIM_DMA   (0x0020)
227#define MCF_CCM_MISCCR_SSI_PUS    (0x0040)
228#define MCF_CCM_MISCCR_SSI_PUE    (0x0080)
229#define MCF_CCM_MISCCR_LCD_CHEN   (0x0100)
230#define MCF_CCM_MISCCR_LIMP       (0x1000)
231#define MCF_CCM_MISCCR_PLL_LOCK   (0x2000)
232
233/* Bit definitions and macros for MCF_CCM_CDR */
234#define MCF_CCM_CDR_SSIDIV(x)     (((x)&0x000F)<<0)
235#define MCF_CCM_CDR_LPDIV(x)      (((x)&0x000F)<<8)
236
237/* Bit definitions and macros for MCF_CCM_UHCSR */
238#define MCF_CCM_UHCSR_XPDE        (0x0001)
239#define MCF_CCM_UHCSR_UHMIE       (0x0002)
240#define MCF_CCM_UHCSR_WKUP        (0x0004)
241#define MCF_CCM_UHCSR_PORTIND(x)  (((x)&0x0003)<<14)
242
243/* Bit definitions and macros for MCF_CCM_UOCSR */
244#define MCF_CCM_UOCSR_XPDE        (0x0001)
245#define MCF_CCM_UOCSR_UOMIE       (0x0002)
246#define MCF_CCM_UOCSR_WKUP        (0x0004)
247#define MCF_CCM_UOCSR_PWRFLT      (0x0008)
248#define MCF_CCM_UOCSR_SEND        (0x0010)
249#define MCF_CCM_UOCSR_VVLD        (0x0020)
250#define MCF_CCM_UOCSR_BVLD        (0x0040)
251#define MCF_CCM_UOCSR_AVLD        (0x0080)
252#define MCF_CCM_UOCSR_DPPU        (0x0100)
253#define MCF_CCM_UOCSR_DCR_VBUS    (0x0200)
254#define MCF_CCM_UOCSR_CRG_VBUS    (0x0400)
255#define MCF_CCM_UOCSR_DRV_VBUS    (0x0800)
256#define MCF_CCM_UOCSR_DMPD        (0x1000)
257#define MCF_CCM_UOCSR_DPPD        (0x2000)
258#define MCF_CCM_UOCSR_PORTIND(x)  (((x)&0x0003)<<14)
259
260/*********************************************************************
261 *
262 * DMA Timers (DTIM)
263 *
264 *********************************************************************/
265
266/* Register read/write macros */
267#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
268#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
269#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
270#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
271#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
272#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
273#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
274#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)
275#define MCF_DTIM1_DTER           MCF_REG08(0xFC074003)
276#define MCF_DTIM1_DTRR           MCF_REG32(0xFC074004)
277#define MCF_DTIM1_DTCR           MCF_REG32(0xFC074008)
278#define MCF_DTIM1_DTCN           MCF_REG32(0xFC07400C)
279#define MCF_DTIM2_DTMR           MCF_REG16(0xFC078000)
280#define MCF_DTIM2_DTXMR          MCF_REG08(0xFC078002)
281#define MCF_DTIM2_DTER           MCF_REG08(0xFC078003)
282#define MCF_DTIM2_DTRR           MCF_REG32(0xFC078004)
283#define MCF_DTIM2_DTCR           MCF_REG32(0xFC078008)
284#define MCF_DTIM2_DTCN           MCF_REG32(0xFC07800C)
285#define MCF_DTIM3_DTMR           MCF_REG16(0xFC07C000)
286#define MCF_DTIM3_DTXMR          MCF_REG08(0xFC07C002)
287#define MCF_DTIM3_DTER           MCF_REG08(0xFC07C003)
288#define MCF_DTIM3_DTRR           MCF_REG32(0xFC07C004)
289#define MCF_DTIM3_DTCR           MCF_REG32(0xFC07C008)
290#define MCF_DTIM3_DTCN           MCF_REG32(0xFC07C00C)
291#define MCF_DTIM_DTMR(x)         MCF_REG16(0xFC070000+((x)*0x4000))
292#define MCF_DTIM_DTXMR(x)        MCF_REG08(0xFC070002+((x)*0x4000))
293#define MCF_DTIM_DTER(x)         MCF_REG08(0xFC070003+((x)*0x4000))
294#define MCF_DTIM_DTRR(x)         MCF_REG32(0xFC070004+((x)*0x4000))
295#define MCF_DTIM_DTCR(x)         MCF_REG32(0xFC070008+((x)*0x4000))
296#define MCF_DTIM_DTCN(x)         MCF_REG32(0xFC07000C+((x)*0x4000))
297
298/* Bit definitions and macros for MCF_DTIM_DTMR */
299#define MCF_DTIM_DTMR_RST        (0x0001)
300#define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
301#define MCF_DTIM_DTMR_FRR        (0x0008)
302#define MCF_DTIM_DTMR_ORRI       (0x0010)
303#define MCF_DTIM_DTMR_OM         (0x0020)
304#define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
305#define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
306#define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
307#define MCF_DTIM_DTMR_CE_FALL    (0x0080)
308#define MCF_DTIM_DTMR_CE_RISE    (0x0040)
309#define MCF_DTIM_DTMR_CE_NONE    (0x0000)
310#define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
311#define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
312#define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
313#define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
314
315/* Bit definitions and macros for MCF_DTIM_DTXMR */
316#define MCF_DTIM_DTXMR_MODE16    (0x01)
317#define MCF_DTIM_DTXMR_DMAEN     (0x80)
318
319/* Bit definitions and macros for MCF_DTIM_DTER */
320#define MCF_DTIM_DTER_CAP        (0x01)
321#define MCF_DTIM_DTER_REF        (0x02)
322
323/* Bit definitions and macros for MCF_DTIM_DTRR */
324#define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
325
326/* Bit definitions and macros for MCF_DTIM_DTCR */
327#define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
328
329/* Bit definitions and macros for MCF_DTIM_DTCN */
330#define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
331
332/*********************************************************************
333 *
334 * FlexBus Chip Selects (FBCS)
335 *
336 *********************************************************************/
337
338/* Register read/write macros */
339#define MCF_FBCS0_CSAR		MCF_REG32(0xFC008000)
340#define MCF_FBCS0_CSMR		MCF_REG32(0xFC008004)
341#define MCF_FBCS0_CSCR		MCF_REG32(0xFC008008)
342#define MCF_FBCS1_CSAR		MCF_REG32(0xFC00800C)
343#define MCF_FBCS1_CSMR		MCF_REG32(0xFC008010)
344#define MCF_FBCS1_CSCR		MCF_REG32(0xFC008014)
345#define MCF_FBCS2_CSAR		MCF_REG32(0xFC008018)
346#define MCF_FBCS2_CSMR		MCF_REG32(0xFC00801C)
347#define MCF_FBCS2_CSCR		MCF_REG32(0xFC008020)
348#define MCF_FBCS3_CSAR		MCF_REG32(0xFC008024)
349#define MCF_FBCS3_CSMR		MCF_REG32(0xFC008028)
350#define MCF_FBCS3_CSCR		MCF_REG32(0xFC00802C)
351#define MCF_FBCS4_CSAR		MCF_REG32(0xFC008030)
352#define MCF_FBCS4_CSMR		MCF_REG32(0xFC008034)
353#define MCF_FBCS4_CSCR		MCF_REG32(0xFC008038)
354#define MCF_FBCS5_CSAR		MCF_REG32(0xFC00803C)
355#define MCF_FBCS5_CSMR		MCF_REG32(0xFC008040)
356#define MCF_FBCS5_CSCR		MCF_REG32(0xFC008044)
357#define MCF_FBCS_CSAR(x)	MCF_REG32(0xFC008000+((x)*0x00C))
358#define MCF_FBCS_CSMR(x)	MCF_REG32(0xFC008004+((x)*0x00C))
359#define MCF_FBCS_CSCR(x)	MCF_REG32(0xFC008008+((x)*0x00C))
360
361/* Bit definitions and macros for MCF_FBCS_CSAR */
362#define MCF_FBCS_CSAR_BA(x)	((x)&0xFFFF0000)
363
364/* Bit definitions and macros for MCF_FBCS_CSMR */
365#define MCF_FBCS_CSMR_V		(0x00000001)
366#define MCF_FBCS_CSMR_WP	(0x00000100)
367#define MCF_FBCS_CSMR_BAM(x)	(((x)&0x0000FFFF)<<16)
368#define MCF_FBCS_CSMR_BAM_4G	(0xFFFF0000)
369#define MCF_FBCS_CSMR_BAM_2G	(0x7FFF0000)
370#define MCF_FBCS_CSMR_BAM_1G	(0x3FFF0000)
371#define MCF_FBCS_CSMR_BAM_1024M	(0x3FFF0000)
372#define MCF_FBCS_CSMR_BAM_512M	(0x1FFF0000)
373#define MCF_FBCS_CSMR_BAM_256M	(0x0FFF0000)
374#define MCF_FBCS_CSMR_BAM_128M	(0x07FF0000)
375#define MCF_FBCS_CSMR_BAM_64M	(0x03FF0000)
376#define MCF_FBCS_CSMR_BAM_32M	(0x01FF0000)
377#define MCF_FBCS_CSMR_BAM_16M	(0x00FF0000)
378#define MCF_FBCS_CSMR_BAM_8M	(0x007F0000)
379#define MCF_FBCS_CSMR_BAM_4M	(0x003F0000)
380#define MCF_FBCS_CSMR_BAM_2M	(0x001F0000)
381#define MCF_FBCS_CSMR_BAM_1M	(0x000F0000)
382#define MCF_FBCS_CSMR_BAM_1024K	(0x000F0000)
383#define MCF_FBCS_CSMR_BAM_512K	(0x00070000)
384#define MCF_FBCS_CSMR_BAM_256K	(0x00030000)
385#define MCF_FBCS_CSMR_BAM_128K	(0x00010000)
386#define MCF_FBCS_CSMR_BAM_64K	(0x00000000)
387
388/* Bit definitions and macros for MCF_FBCS_CSCR */
389#define MCF_FBCS_CSCR_BSTW	(0x00000008)
390#define MCF_FBCS_CSCR_BSTR	(0x00000010)
391#define MCF_FBCS_CSCR_BEM	(0x00000020)
392#define MCF_FBCS_CSCR_PS(x)	(((x)&0x00000003)<<6)
393#define MCF_FBCS_CSCR_AA	(0x00000100)
394#define MCF_FBCS_CSCR_SBM	(0x00000200)
395#define MCF_FBCS_CSCR_WS(x)	(((x)&0x0000003F)<<10)
396#define MCF_FBCS_CSCR_WRAH(x)	(((x)&0x00000003)<<16)
397#define MCF_FBCS_CSCR_RDAH(x)	(((x)&0x00000003)<<18)
398#define MCF_FBCS_CSCR_ASET(x)	(((x)&0x00000003)<<20)
399#define MCF_FBCS_CSCR_SWSEN	(0x00800000)
400#define MCF_FBCS_CSCR_SWS(x)	(((x)&0x0000003F)<<26)
401#define MCF_FBCS_CSCR_PS_8	(0x0040)
402#define MCF_FBCS_CSCR_PS_16	(0x0080)
403#define MCF_FBCS_CSCR_PS_32	(0x0000)
404
405/*********************************************************************
406 *
407 * General Purpose I/O (GPIO)
408 *
409 *********************************************************************/
410
411/* Register read/write macros */
412#define MCF_GPIO_PODR_FECH		MCF_REG08(0xFC0A4000)
413#define MCF_GPIO_PODR_FECL		MCF_REG08(0xFC0A4001)
414#define MCF_GPIO_PODR_SSI		MCF_REG08(0xFC0A4002)
415#define MCF_GPIO_PODR_BUSCTL		MCF_REG08(0xFC0A4003)
416#define MCF_GPIO_PODR_BE		MCF_REG08(0xFC0A4004)
417#define MCF_GPIO_PODR_CS		MCF_REG08(0xFC0A4005)
418#define MCF_GPIO_PODR_PWM		MCF_REG08(0xFC0A4006)
419#define MCF_GPIO_PODR_FECI2C		MCF_REG08(0xFC0A4007)
420#define MCF_GPIO_PODR_UART		MCF_REG08(0xFC0A4009)
421#define MCF_GPIO_PODR_QSPI		MCF_REG08(0xFC0A400A)
422#define MCF_GPIO_PODR_TIMER		MCF_REG08(0xFC0A400B)
423#define MCF_GPIO_PODR_LCDDATAH		MCF_REG08(0xFC0A400D)
424#define MCF_GPIO_PODR_LCDDATAM		MCF_REG08(0xFC0A400E)
425#define MCF_GPIO_PODR_LCDDATAL		MCF_REG08(0xFC0A400F)
426#define MCF_GPIO_PODR_LCDCTLH		MCF_REG08(0xFC0A4010)
427#define MCF_GPIO_PODR_LCDCTLL		MCF_REG08(0xFC0A4011)
428#define MCF_GPIO_PDDR_FECH		MCF_REG08(0xFC0A4014)
429#define MCF_GPIO_PDDR_FECL		MCF_REG08(0xFC0A4015)
430#define MCF_GPIO_PDDR_SSI		MCF_REG08(0xFC0A4016)
431#define MCF_GPIO_PDDR_BUSCTL		MCF_REG08(0xFC0A4017)
432#define MCF_GPIO_PDDR_BE		MCF_REG08(0xFC0A4018)
433#define MCF_GPIO_PDDR_CS		MCF_REG08(0xFC0A4019)
434#define MCF_GPIO_PDDR_PWM		MCF_REG08(0xFC0A401A)
435#define MCF_GPIO_PDDR_FECI2C		MCF_REG08(0xFC0A401B)
436#define MCF_GPIO_PDDR_UART		MCF_REG08(0xFC0A401C)
437#define MCF_GPIO_PDDR_QSPI		MCF_REG08(0xFC0A401E)
438#define MCF_GPIO_PDDR_TIMER		MCF_REG08(0xFC0A401F)
439#define MCF_GPIO_PDDR_LCDDATAH		MCF_REG08(0xFC0A4021)
440#define MCF_GPIO_PDDR_LCDDATAM		MCF_REG08(0xFC0A4022)
441#define MCF_GPIO_PDDR_LCDDATAL		MCF_REG08(0xFC0A4023)
442#define MCF_GPIO_PDDR_LCDCTLH		MCF_REG08(0xFC0A4024)
443#define MCF_GPIO_PDDR_LCDCTLL		MCF_REG08(0xFC0A4025)
444#define MCF_GPIO_PPDSDR_FECH		MCF_REG08(0xFC0A4028)
445#define MCF_GPIO_PPDSDR_FECL		MCF_REG08(0xFC0A4029)
446#define MCF_GPIO_PPDSDR_SSI		MCF_REG08(0xFC0A402A)
447#define MCF_GPIO_PPDSDR_BUSCTL		MCF_REG08(0xFC0A402B)
448#define MCF_GPIO_PPDSDR_BE		MCF_REG08(0xFC0A402C)
449#define MCF_GPIO_PPDSDR_CS		MCF_REG08(0xFC0A402D)
450#define MCF_GPIO_PPDSDR_PWM		MCF_REG08(0xFC0A402E)
451#define MCF_GPIO_PPDSDR_FECI2C		MCF_REG08(0xFC0A402F)
452#define MCF_GPIO_PPDSDR_UART		MCF_REG08(0xFC0A4031)
453#define MCF_GPIO_PPDSDR_QSPI		MCF_REG08(0xFC0A4032)
454#define MCF_GPIO_PPDSDR_TIMER		MCF_REG08(0xFC0A4033)
455#define MCF_GPIO_PPDSDR_LCDDATAH	MCF_REG08(0xFC0A4035)
456#define MCF_GPIO_PPDSDR_LCDDATAM	MCF_REG08(0xFC0A4036)
457#define MCF_GPIO_PPDSDR_LCDDATAL	MCF_REG08(0xFC0A4037)
458#define MCF_GPIO_PPDSDR_LCDCTLH		MCF_REG08(0xFC0A4038)
459#define MCF_GPIO_PPDSDR_LCDCTLL		MCF_REG08(0xFC0A4039)
460#define MCF_GPIO_PCLRR_FECH		MCF_REG08(0xFC0A403C)
461#define MCF_GPIO_PCLRR_FECL		MCF_REG08(0xFC0A403D)
462#define MCF_GPIO_PCLRR_SSI		MCF_REG08(0xFC0A403E)
463#define MCF_GPIO_PCLRR_BUSCTL		MCF_REG08(0xFC0A403F)
464#define MCF_GPIO_PCLRR_BE		MCF_REG08(0xFC0A4040)
465#define MCF_GPIO_PCLRR_CS		MCF_REG08(0xFC0A4041)
466#define MCF_GPIO_PCLRR_PWM		MCF_REG08(0xFC0A4042)
467#define MCF_GPIO_PCLRR_FECI2C		MCF_REG08(0xFC0A4043)
468#define MCF_GPIO_PCLRR_UART		MCF_REG08(0xFC0A4045)
469#define MCF_GPIO_PCLRR_QSPI		MCF_REG08(0xFC0A4046)
470#define MCF_GPIO_PCLRR_TIMER		MCF_REG08(0xFC0A4047)
471#define MCF_GPIO_PCLRR_LCDDATAH		MCF_REG08(0xFC0A4049)
472#define MCF_GPIO_PCLRR_LCDDATAM		MCF_REG08(0xFC0A404A)
473#define MCF_GPIO_PCLRR_LCDDATAL		MCF_REG08(0xFC0A404B)
474#define MCF_GPIO_PCLRR_LCDCTLH		MCF_REG08(0xFC0A404C)
475#define MCF_GPIO_PCLRR_LCDCTLL		MCF_REG08(0xFC0A404D)
476#define MCF_GPIO_PAR_FEC		MCF_REG08(0xFC0A4050)
477#define MCF_GPIO_PAR_PWM		MCF_REG08(0xFC0A4051)
478#define MCF_GPIO_PAR_BUSCTL		MCF_REG08(0xFC0A4052)
479#define MCF_GPIO_PAR_FECI2C		MCF_REG08(0xFC0A4053)
480#define MCF_GPIO_PAR_BE			MCF_REG08(0xFC0A4054)
481#define MCF_GPIO_PAR_CS			MCF_REG08(0xFC0A4055)
482#define MCF_GPIO_PAR_SSI		MCF_REG16(0xFC0A4056)
483#define MCF_GPIO_PAR_UART		MCF_REG16(0xFC0A4058)
484#define MCF_GPIO_PAR_QSPI		MCF_REG16(0xFC0A405A)
485#define MCF_GPIO_PAR_TIMER		MCF_REG08(0xFC0A405C)
486#define MCF_GPIO_PAR_LCDDATA		MCF_REG08(0xFC0A405D)
487#define MCF_GPIO_PAR_LCDCTL		MCF_REG16(0xFC0A405E)
488#define MCF_GPIO_PAR_IRQ		MCF_REG16(0xFC0A4060)
489#define MCF_GPIO_MSCR_FLEXBUS		MCF_REG08(0xFC0A4064)
490#define MCF_GPIO_MSCR_SDRAM		MCF_REG08(0xFC0A4065)
491#define MCF_GPIO_DSCR_I2C		MCF_REG08(0xFC0A4068)
492#define MCF_GPIO_DSCR_PWM		MCF_REG08(0xFC0A4069)
493#define MCF_GPIO_DSCR_FEC		MCF_REG08(0xFC0A406A)
494#define MCF_GPIO_DSCR_UART		MCF_REG08(0xFC0A406B)
495#define MCF_GPIO_DSCR_QSPI		MCF_REG08(0xFC0A406C)
496#define MCF_GPIO_DSCR_TIMER		MCF_REG08(0xFC0A406D)
497#define MCF_GPIO_DSCR_SSI		MCF_REG08(0xFC0A406E)
498#define MCF_GPIO_DSCR_LCD		MCF_REG08(0xFC0A406F)
499#define MCF_GPIO_DSCR_DEBUG		MCF_REG08(0xFC0A4070)
500#define MCF_GPIO_DSCR_CLKRST		MCF_REG08(0xFC0A4071)
501#define MCF_GPIO_DSCR_IRQ		MCF_REG08(0xFC0A4072)
502
503/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
504#define MCF_GPIO_PODR_FECH_PODR_FECH0              (0x01)
505#define MCF_GPIO_PODR_FECH_PODR_FECH1              (0x02)
506#define MCF_GPIO_PODR_FECH_PODR_FECH2              (0x04)
507#define MCF_GPIO_PODR_FECH_PODR_FECH3              (0x08)
508#define MCF_GPIO_PODR_FECH_PODR_FECH4              (0x10)
509#define MCF_GPIO_PODR_FECH_PODR_FECH5              (0x20)
510#define MCF_GPIO_PODR_FECH_PODR_FECH6              (0x40)
511#define MCF_GPIO_PODR_FECH_PODR_FECH7              (0x80)
512
513/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
514#define MCF_GPIO_PODR_FECL_PODR_FECL0              (0x01)
515#define MCF_GPIO_PODR_FECL_PODR_FECL1              (0x02)
516#define MCF_GPIO_PODR_FECL_PODR_FECL2              (0x04)
517#define MCF_GPIO_PODR_FECL_PODR_FECL3              (0x08)
518#define MCF_GPIO_PODR_FECL_PODR_FECL4              (0x10)
519#define MCF_GPIO_PODR_FECL_PODR_FECL5              (0x20)
520#define MCF_GPIO_PODR_FECL_PODR_FECL6              (0x40)
521#define MCF_GPIO_PODR_FECL_PODR_FECL7              (0x80)
522
523/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
524#define MCF_GPIO_PODR_SSI_PODR_SSI0                (0x01)
525#define MCF_GPIO_PODR_SSI_PODR_SSI1                (0x02)
526#define MCF_GPIO_PODR_SSI_PODR_SSI2                (0x04)
527#define MCF_GPIO_PODR_SSI_PODR_SSI3                (0x08)
528#define MCF_GPIO_PODR_SSI_PODR_SSI4                (0x10)
529
530/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
531#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0         (0x01)
532#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1          (0x02)
533#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2          (0x04)
534#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3          (0x08)
535
536/* Bit definitions and macros for MCF_GPIO_PODR_BE */
537#define MCF_GPIO_PODR_BE_PODR_BE0                  (0x01)
538#define MCF_GPIO_PODR_BE_PODR_BE1                  (0x02)
539#define MCF_GPIO_PODR_BE_PODR_BE2                  (0x04)
540#define MCF_GPIO_PODR_BE_PODR_BE3                  (0x08)
541
542/* Bit definitions and macros for MCF_GPIO_PODR_CS */
543#define MCF_GPIO_PODR_CS_PODR_CS1                  (0x02)
544#define MCF_GPIO_PODR_CS_PODR_CS2                  (0x04)
545#define MCF_GPIO_PODR_CS_PODR_CS3                  (0x08)
546#define MCF_GPIO_PODR_CS_PODR_CS4                  (0x10)
547#define MCF_GPIO_PODR_CS_PODR_CS5                  (0x20)
548
549/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
550#define MCF_GPIO_PODR_PWM_PODR_PWM2                (0x04)
551#define MCF_GPIO_PODR_PWM_PODR_PWM3                (0x08)
552#define MCF_GPIO_PODR_PWM_PODR_PWM4                (0x10)
553#define MCF_GPIO_PODR_PWM_PODR_PWM5                (0x20)
554
555/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
556#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0          (0x01)
557#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1          (0x02)
558#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2          (0x04)
559#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3          (0x08)
560
561/* Bit definitions and macros for MCF_GPIO_PODR_UART */
562#define MCF_GPIO_PODR_UART_PODR_UART0              (0x01)
563#define MCF_GPIO_PODR_UART_PODR_UART1              (0x02)
564#define MCF_GPIO_PODR_UART_PODR_UART2              (0x04)
565#define MCF_GPIO_PODR_UART_PODR_UART3              (0x08)
566#define MCF_GPIO_PODR_UART_PODR_UART4              (0x10)
567#define MCF_GPIO_PODR_UART_PODR_UART5              (0x20)
568#define MCF_GPIO_PODR_UART_PODR_UART6              (0x40)
569#define MCF_GPIO_PODR_UART_PODR_UART7              (0x80)
570
571/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
572#define MCF_GPIO_PODR_QSPI_PODR_QSPI0              (0x01)
573#define MCF_GPIO_PODR_QSPI_PODR_QSPI1              (0x02)
574#define MCF_GPIO_PODR_QSPI_PODR_QSPI2              (0x04)
575#define MCF_GPIO_PODR_QSPI_PODR_QSPI3              (0x08)
576#define MCF_GPIO_PODR_QSPI_PODR_QSPI4              (0x10)
577#define MCF_GPIO_PODR_QSPI_PODR_QSPI5              (0x20)
578
579/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
580#define MCF_GPIO_PODR_TIMER_PODR_TIMER0            (0x01)
581#define MCF_GPIO_PODR_TIMER_PODR_TIMER1            (0x02)
582#define MCF_GPIO_PODR_TIMER_PODR_TIMER2            (0x04)
583#define MCF_GPIO_PODR_TIMER_PODR_TIMER3            (0x08)
584
585/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
586#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0      (0x01)
587#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1      (0x02)
588
589/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
590#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0      (0x01)
591#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1      (0x02)
592#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2      (0x04)
593#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3      (0x08)
594#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4      (0x10)
595#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5      (0x20)
596#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6      (0x40)
597#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7      (0x80)
598
599/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
600#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0      (0x01)
601#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1      (0x02)
602#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2      (0x04)
603#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3      (0x08)
604#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4      (0x10)
605#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5      (0x20)
606#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6      (0x40)
607#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7      (0x80)
608
609/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
610#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0        (0x01)
611
612/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
613#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0        (0x01)
614#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1        (0x02)
615#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2        (0x04)
616#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3        (0x08)
617#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4        (0x10)
618#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5        (0x20)
619#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6        (0x40)
620#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7        (0x80)
621
622/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
623#define MCF_GPIO_PDDR_FECH_PDDR_FECH0              (0x01)
624#define MCF_GPIO_PDDR_FECH_PDDR_FECH1              (0x02)
625#define MCF_GPIO_PDDR_FECH_PDDR_FECH2              (0x04)
626#define MCF_GPIO_PDDR_FECH_PDDR_FECH3              (0x08)
627#define MCF_GPIO_PDDR_FECH_PDDR_FECH4              (0x10)
628#define MCF_GPIO_PDDR_FECH_PDDR_FECH5              (0x20)
629#define MCF_GPIO_PDDR_FECH_PDDR_FECH6              (0x40)
630#define MCF_GPIO_PDDR_FECH_PDDR_FECH7              (0x80)
631
632/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
633#define MCF_GPIO_PDDR_FECL_PDDR_FECL0              (0x01)
634#define MCF_GPIO_PDDR_FECL_PDDR_FECL1              (0x02)
635#define MCF_GPIO_PDDR_FECL_PDDR_FECL2              (0x04)
636#define MCF_GPIO_PDDR_FECL_PDDR_FECL3              (0x08)
637#define MCF_GPIO_PDDR_FECL_PDDR_FECL4              (0x10)
638#define MCF_GPIO_PDDR_FECL_PDDR_FECL5              (0x20)
639#define MCF_GPIO_PDDR_FECL_PDDR_FECL6              (0x40)
640#define MCF_GPIO_PDDR_FECL_PDDR_FECL7              (0x80)
641
642/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
643#define MCF_GPIO_PDDR_SSI_PDDR_SSI0                (0x01)
644#define MCF_GPIO_PDDR_SSI_PDDR_SSI1                (0x02)
645#define MCF_GPIO_PDDR_SSI_PDDR_SSI2                (0x04)
646#define MCF_GPIO_PDDR_SSI_PDDR_SSI3                (0x08)
647#define MCF_GPIO_PDDR_SSI_PDDR_SSI4                (0x10)
648
649/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
650#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0         (0x01)
651#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1          (0x02)
652#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2          (0x04)
653#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3          (0x08)
654
655/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
656#define MCF_GPIO_PDDR_BE_PDDR_BE0                  (0x01)
657#define MCF_GPIO_PDDR_BE_PDDR_BE1                  (0x02)
658#define MCF_GPIO_PDDR_BE_PDDR_BE2                  (0x04)
659#define MCF_GPIO_PDDR_BE_PDDR_BE3                  (0x08)
660
661/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
662#define MCF_GPIO_PDDR_CS_PDDR_CS1                  (0x02)
663#define MCF_GPIO_PDDR_CS_PDDR_CS2                  (0x04)
664#define MCF_GPIO_PDDR_CS_PDDR_CS3                  (0x08)
665#define MCF_GPIO_PDDR_CS_PDDR_CS4                  (0x10)
666#define MCF_GPIO_PDDR_CS_PDDR_CS5                  (0x20)
667
668/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
669#define MCF_GPIO_PDDR_PWM_PDDR_PWM2                (0x04)
670#define MCF_GPIO_PDDR_PWM_PDDR_PWM3                (0x08)
671#define MCF_GPIO_PDDR_PWM_PDDR_PWM4                (0x10)
672#define MCF_GPIO_PDDR_PWM_PDDR_PWM5                (0x20)
673
674/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
675#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0          (0x01)
676#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1          (0x02)
677#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2          (0x04)
678#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3          (0x08)
679
680/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
681#define MCF_GPIO_PDDR_UART_PDDR_UART0              (0x01)
682#define MCF_GPIO_PDDR_UART_PDDR_UART1              (0x02)
683#define MCF_GPIO_PDDR_UART_PDDR_UART2              (0x04)
684#define MCF_GPIO_PDDR_UART_PDDR_UART3              (0x08)
685#define MCF_GPIO_PDDR_UART_PDDR_UART4              (0x10)
686#define MCF_GPIO_PDDR_UART_PDDR_UART5              (0x20)
687#define MCF_GPIO_PDDR_UART_PDDR_UART6              (0x40)
688#define MCF_GPIO_PDDR_UART_PDDR_UART7              (0x80)
689
690/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
691#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0              (0x01)
692#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1              (0x02)
693#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2              (0x04)
694#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3              (0x08)
695#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4              (0x10)
696#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5              (0x20)
697
698/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
699#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0            (0x01)
700#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1            (0x02)
701#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2            (0x04)
702#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3            (0x08)
703
704/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
705#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0      (0x01)
706#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1      (0x02)
707
708/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
709#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0      (0x01)
710#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1      (0x02)
711#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2      (0x04)
712#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3      (0x08)
713#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4      (0x10)
714#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5      (0x20)
715#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6      (0x40)
716#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7      (0x80)
717
718/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
719#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0      (0x01)
720#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1      (0x02)
721#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2      (0x04)
722#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3      (0x08)
723#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4      (0x10)
724#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5      (0x20)
725#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6      (0x40)
726#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7      (0x80)
727
728/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
729#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0        (0x01)
730
731/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
732#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0        (0x01)
733#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1        (0x02)
734#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2        (0x04)
735#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3        (0x08)
736#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4        (0x10)
737#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5        (0x20)
738#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6        (0x40)
739#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7        (0x80)
740
741/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
742#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0          (0x01)
743#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1          (0x02)
744#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2          (0x04)
745#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3          (0x08)
746#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4          (0x10)
747#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5          (0x20)
748#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6          (0x40)
749#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7          (0x80)
750
751/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
752#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0          (0x01)
753#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1          (0x02)
754#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2          (0x04)
755#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3          (0x08)
756#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4          (0x10)
757#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5          (0x20)
758#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6          (0x40)
759#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7          (0x80)
760
761/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
762#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0            (0x01)
763#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1            (0x02)
764#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2            (0x04)
765#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3            (0x08)
766#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4            (0x10)
767
768/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
769#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0       (0x01)
770#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1      (0x02)
771#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2      (0x04)
772#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3      (0x08)
773
774/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
775#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0              (0x01)
776#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1              (0x02)
777#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2              (0x04)
778#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3              (0x08)
779
780/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
781#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1              (0x02)
782#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2              (0x04)
783#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3              (0x08)
784#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4              (0x10)
785#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5              (0x20)
786
787/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
788#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2            (0x04)
789#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3            (0x08)
790#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4            (0x10)
791#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5            (0x20)
792
793/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
794#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0      (0x01)
795#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1      (0x02)
796#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2      (0x04)
797#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3      (0x08)
798
799/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
800#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0          (0x01)
801#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1          (0x02)
802#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2          (0x04)
803#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3          (0x08)
804#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4          (0x10)
805#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5          (0x20)
806#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6          (0x40)
807#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7          (0x80)
808
809/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
810#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0          (0x01)
811#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1          (0x02)
812#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2          (0x04)
813#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3          (0x08)
814#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4          (0x10)
815#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5          (0x20)
816
817/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
818#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0        (0x01)
819#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1        (0x02)
820#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2        (0x04)
821#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3        (0x08)
822
823/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
824#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0  (0x01)
825#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1  (0x02)
826
827/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
828#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0  (0x01)
829#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1  (0x02)
830#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2  (0x04)
831#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3  (0x08)
832#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4  (0x10)
833#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5  (0x20)
834#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6  (0x40)
835#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7  (0x80)
836
837/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
838#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0  (0x01)
839#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1  (0x02)
840#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2  (0x04)
841#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3  (0x08)
842#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4  (0x10)
843#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5  (0x20)
844#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6  (0x40)
845#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7  (0x80)
846
847/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
848#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0    (0x01)
849
850/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
851#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0    (0x01)
852#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1    (0x02)
853#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2    (0x04)
854#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3    (0x08)
855#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4    (0x10)
856#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5    (0x20)
857#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6    (0x40)
858#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7    (0x80)
859
860/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
861#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0            (0x01)
862#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1            (0x02)
863#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2            (0x04)
864#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3            (0x08)
865#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4            (0x10)
866#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5            (0x20)
867#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6            (0x40)
868#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7            (0x80)
869
870/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
871#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0            (0x01)
872#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1            (0x02)
873#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2            (0x04)
874#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3            (0x08)
875#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4            (0x10)
876#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5            (0x20)
877#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6            (0x40)
878#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7            (0x80)
879
880/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
881#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0              (0x01)
882#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1              (0x02)
883#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2              (0x04)
884#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3              (0x08)
885#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4              (0x10)
886
887/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
888#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0        (0x01)
889#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1        (0x02)
890#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2        (0x04)
891#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3        (0x08)
892
893/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
894#define MCF_GPIO_PCLRR_BE_PCLRR_BE0                (0x01)
895#define MCF_GPIO_PCLRR_BE_PCLRR_BE1                (0x02)
896#define MCF_GPIO_PCLRR_BE_PCLRR_BE2                (0x04)
897#define MCF_GPIO_PCLRR_BE_PCLRR_BE3                (0x08)
898
899/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
900#define MCF_GPIO_PCLRR_CS_PCLRR_CS1                (0x02)
901#define MCF_GPIO_PCLRR_CS_PCLRR_CS2                (0x04)
902#define MCF_GPIO_PCLRR_CS_PCLRR_CS3                (0x08)
903#define MCF_GPIO_PCLRR_CS_PCLRR_CS4                (0x10)
904#define MCF_GPIO_PCLRR_CS_PCLRR_CS5                (0x20)
905
906/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
907#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2              (0x04)
908#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3              (0x08)
909#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4              (0x10)
910#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5              (0x20)
911
912/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
913#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0        (0x01)
914#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1        (0x02)
915#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2        (0x04)
916#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3        (0x08)
917
918/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
919#define MCF_GPIO_PCLRR_UART_PCLRR_UART0            (0x01)
920#define MCF_GPIO_PCLRR_UART_PCLRR_UART1            (0x02)
921#define MCF_GPIO_PCLRR_UART_PCLRR_UART2            (0x04)
922#define MCF_GPIO_PCLRR_UART_PCLRR_UART3            (0x08)
923#define MCF_GPIO_PCLRR_UART_PCLRR_UART4            (0x10)
924#define MCF_GPIO_PCLRR_UART_PCLRR_UART5            (0x20)
925#define MCF_GPIO_PCLRR_UART_PCLRR_UART6            (0x40)
926#define MCF_GPIO_PCLRR_UART_PCLRR_UART7            (0x80)
927
928/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
929#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0            (0x01)
930#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1            (0x02)
931#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2            (0x04)
932#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3            (0x08)
933#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4            (0x10)
934#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5            (0x20)
935
936/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
937#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0          (0x01)
938#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1          (0x02)
939#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2          (0x04)
940#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3          (0x08)
941
942/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
943#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0    (0x01)
944#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1    (0x02)
945
946/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
947#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0    (0x01)
948#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1    (0x02)
949#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2    (0x04)
950#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3    (0x08)
951#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4    (0x10)
952#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5    (0x20)
953#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6    (0x40)
954#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7    (0x80)
955
956/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
957#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0    (0x01)
958#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1    (0x02)
959#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2    (0x04)
960#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3    (0x08)
961#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4    (0x10)
962#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5    (0x20)
963#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6    (0x40)
964#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7    (0x80)
965
966/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
967#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0      (0x01)
968
969/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
970#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0      (0x01)
971#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1      (0x02)
972#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2      (0x04)
973#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3      (0x08)
974#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4      (0x10)
975#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5      (0x20)
976#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6      (0x40)
977#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7      (0x80)
978
979/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
980#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x)            (((x)&0x03)<<0)
981#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x)             (((x)&0x03)<<2)
982#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO           (0x00)
983#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1          (0x04)
984#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC            (0x0C)
985#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO          (0x00)
986#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART          (0x01)
987#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC           (0x03)
988
989/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
990#define MCF_GPIO_PAR_PWM_PAR_PWM1(x)               (((x)&0x03)<<0)
991#define MCF_GPIO_PAR_PWM_PAR_PWM3(x)               (((x)&0x03)<<2)
992#define MCF_GPIO_PAR_PWM_PAR_PWM5                  (0x10)
993#define MCF_GPIO_PAR_PWM_PAR_PWM7                  (0x20)
994
995/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
996#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x)              (((x)&0x03)<<3)
997#define MCF_GPIO_PAR_BUSCTL_PAR_RWB                (0x20)
998#define MCF_GPIO_PAR_BUSCTL_PAR_TA                 (0x40)
999#define MCF_GPIO_PAR_BUSCTL_PAR_OE                 (0x80)
1000#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO            (0x00)
1001#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE              (0x80)
1002#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO            (0x00)
1003#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA              (0x40)
1004#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO           (0x00)
1005#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB            (0x20)
1006#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO            (0x00)
1007#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0           (0x10)
1008#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS              (0x18)
1009
1010/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
1011#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x)             (((x)&0x03)<<0)
1012#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x)             (((x)&0x03)<<2)
1013#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x)            (((x)&0x03)<<4)
1014#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x)             (((x)&0x03)<<6)
1015#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO           (0x00)
1016#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2          (0x40)
1017#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL            (0x80)
1018#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC           (0xC0)
1019#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO          (0x00)
1020#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2         (0x10)
1021#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA           (0x20)
1022#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO         (0x30)
1023#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO           (0x00)
1024#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2          (0x04)
1025#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL            (0x0C)
1026#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO           (0x00)
1027#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2          (0x02)
1028#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA            (0x03)
1029
1030/* Bit definitions and macros for MCF_GPIO_PAR_BE */
1031#define MCF_GPIO_PAR_BE_PAR_BE0                    (0x01)
1032#define MCF_GPIO_PAR_BE_PAR_BE1                    (0x02)
1033#define MCF_GPIO_PAR_BE_PAR_BE2                    (0x04)
1034#define MCF_GPIO_PAR_BE_PAR_BE3                    (0x08)
1035
1036/* Bit definitions and macros for MCF_GPIO_PAR_CS */
1037#define MCF_GPIO_PAR_CS_PAR_CS1                    (0x02)
1038#define MCF_GPIO_PAR_CS_PAR_CS2                    (0x04)
1039#define MCF_GPIO_PAR_CS_PAR_CS3                    (0x08)
1040#define MCF_GPIO_PAR_CS_PAR_CS4                    (0x10)
1041#define MCF_GPIO_PAR_CS_PAR_CS5                    (0x20)
1042#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO            (0x00)
1043#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1           (0x01)
1044#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1             (0x03)
1045
1046/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
1047#define MCF_GPIO_PAR_SSI_PAR_MCLK                  (0x0080)
1048#define MCF_GPIO_PAR_SSI_PAR_TXD(x)                (((x)&0x0003)<<8)
1049#define MCF_GPIO_PAR_SSI_PAR_RXD(x)                (((x)&0x0003)<<10)
1050#define MCF_GPIO_PAR_SSI_PAR_FS(x)                 (((x)&0x0003)<<12)
1051#define MCF_GPIO_PAR_SSI_PAR_BCLK(x)               (((x)&0x0003)<<14)
1052
1053/* Bit definitions and macros for MCF_GPIO_PAR_UART */
1054#define MCF_GPIO_PAR_UART_PAR_UTXD0                (0x0001)
1055#define MCF_GPIO_PAR_UART_PAR_URXD0                (0x0002)
1056#define MCF_GPIO_PAR_UART_PAR_URTS0                (0x0004)
1057#define MCF_GPIO_PAR_UART_PAR_UCTS0                (0x0008)
1058#define MCF_GPIO_PAR_UART_PAR_UTXD1(x)             (((x)&0x0003)<<4)
1059#define MCF_GPIO_PAR_UART_PAR_URXD1(x)             (((x)&0x0003)<<6)
1060#define MCF_GPIO_PAR_UART_PAR_URTS1(x)             (((x)&0x0003)<<8)
1061#define MCF_GPIO_PAR_UART_PAR_UCTS1(x)             (((x)&0x0003)<<10)
1062#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO           (0x0000)
1063#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK       (0x0800)
1064#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7        (0x0400)
1065#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1          (0x0C00)
1066#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO           (0x0000)
1067#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS         (0x0200)
1068#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6        (0x0100)
1069#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1          (0x0300)
1070#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO           (0x0000)
1071#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD        (0x0080)
1072#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5        (0x0040)
1073#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1          (0x00C0)
1074#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO           (0x0000)
1075#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD        (0x0020)
1076#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4        (0x0010)
1077#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1          (0x0030)
1078
1079/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
1080#define MCF_GPIO_PAR_QSPI_PAR_SCK(x)               (((x)&0x0003)<<4)
1081#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x)              (((x)&0x0003)<<6)
1082#define MCF_GPIO_PAR_QSPI_PAR_DIN(x)               (((x)&0x0003)<<8)
1083#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x)              (((x)&0x0003)<<10)
1084#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x)              (((x)&0x0003)<<12)
1085#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x)              (((x)&0x0003)<<14)
1086
1087/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
1088#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x)             (((x)&0x03)<<0)
1089#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x)             (((x)&0x03)<<2)
1090#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x)             (((x)&0x03)<<4)
1091#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x)             (((x)&0x03)<<6)
1092#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO           (0x00)
1093#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3          (0x80)
1094#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2          (0x40)
1095#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3           (0xC0)
1096#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO           (0x00)
1097#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2          (0x20)
1098#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2          (0x10)
1099#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2           (0x30)
1100#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO           (0x00)
1101#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1          (0x08)
1102#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1          (0x04)
1103#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1           (0x0C)
1104#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO           (0x00)
1105#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0          (0x02)
1106#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0          (0x01)
1107#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0           (0x03)
1108
1109/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
1110#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x)          (((x)&0x03)<<0)
1111#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x)         (((x)&0x03)<<2)
1112#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x)           (((x)&0x03)<<4)
1113#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x)           (((x)&0x03)<<6)
1114
1115/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
1116#define MCF_GPIO_PAR_LCDCTL_PAR_CLS                (0x0001)
1117#define MCF_GPIO_PAR_LCDCTL_PAR_PS                 (0x0002)
1118#define MCF_GPIO_PAR_LCDCTL_PAR_REV                (0x0004)
1119#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR            (0x0008)
1120#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST           (0x0010)
1121#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK              (0x0020)
1122#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC           (0x0040)
1123#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC          (0x0080)
1124#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE             (0x0100)
1125
1126/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
1127#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x)               (((x)&0x0003)<<4)
1128#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x)               (((x)&0x0003)<<6)
1129#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x)               (((x)&0x0003)<<8)
1130#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x)               (((x)&0x0003)<<10)
1131#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x)               (((x)&0x0003)<<12)
1132
1133/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
1134#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x)      (((x)&0x03)<<0)
1135#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x)       (((x)&0x03)<<2)
1136#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x)       (((x)&0x03)<<4)
1137
1138/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
1139#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x)          (((x)&0x03)<<0)
1140#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x)          (((x)&0x03)<<2)
1141#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x)         (((x)&0x03)<<4)
1142
1143/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
1144#define MCF_GPIO_DSCR_I2C_I2C_DSE(x)               (((x)&0x03)<<0)
1145
1146/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
1147#define MCF_GPIO_DSCR_PWM_PWM_DSE(x)               (((x)&0x03)<<0)
1148
1149/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
1150#define MCF_GPIO_DSCR_FEC_FEC_DSE(x)               (((x)&0x03)<<0)
1151
1152/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
1153#define MCF_GPIO_DSCR_UART_UART0_DSE(x)            (((x)&0x03)<<0)
1154#define MCF_GPIO_DSCR_UART_UART1_DSE(x)            (((x)&0x03)<<2)
1155
1156/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
1157#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x)             (((x)&0x03)<<0)
1158
1159/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
1160#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x)           (((x)&0x03)<<0)
1161
1162/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
1163#define MCF_GPIO_DSCR_SSI_SSI_DSE(x)               (((x)&0x03)<<0)
1164
1165/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
1166#define MCF_GPIO_DSCR_LCD_LCD_DSE(x)               (((x)&0x03)<<0)
1167
1168/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
1169#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x)           (((x)&0x03)<<0)
1170
1171/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
1172#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x)         (((x)&0x03)<<0)
1173
1174/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1175#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x)               (((x)&0x03)<<0)
1176
1177/*********************************************************************
1178 *
1179 * Interrupt Controller (INTC)
1180 *
1181 *********************************************************************/
1182
1183/* Register read/write macros */
1184#define MCF_INTC0_IPRH             MCF_REG32(0xFC048000)
1185#define MCF_INTC0_IPRL             MCF_REG32(0xFC048004)
1186#define MCF_INTC0_IMRH             MCF_REG32(0xFC048008)
1187#define MCF_INTC0_IMRL             MCF_REG32(0xFC04800C)
1188#define MCF_INTC0_INTFRCH          MCF_REG32(0xFC048010)
1189#define MCF_INTC0_INTFRCL          MCF_REG32(0xFC048014)
1190#define MCF_INTC0_ICONFIG          MCF_REG16(0xFC04801A)
1191#define MCF_INTC0_SIMR             MCF_REG08(0xFC04801C)
1192#define MCF_INTC0_CIMR             MCF_REG08(0xFC04801D)
1193#define MCF_INTC0_CLMASK           MCF_REG08(0xFC04801E)
1194#define MCF_INTC0_SLMASK           MCF_REG08(0xFC04801F)
1195#define MCF_INTC0_ICR0             MCF_REG08(0xFC048040)
1196#define MCF_INTC0_ICR1             MCF_REG08(0xFC048041)
1197#define MCF_INTC0_ICR2             MCF_REG08(0xFC048042)
1198#define MCF_INTC0_ICR3             MCF_REG08(0xFC048043)
1199#define MCF_INTC0_ICR4             MCF_REG08(0xFC048044)
1200#define MCF_INTC0_ICR5             MCF_REG08(0xFC048045)
1201#define MCF_INTC0_ICR6             MCF_REG08(0xFC048046)
1202#define MCF_INTC0_ICR7             MCF_REG08(0xFC048047)
1203#define MCF_INTC0_ICR8             MCF_REG08(0xFC048048)
1204#define MCF_INTC0_ICR9             MCF_REG08(0xFC048049)
1205#define MCF_INTC0_ICR10            MCF_REG08(0xFC04804A)
1206#define MCF_INTC0_ICR11            MCF_REG08(0xFC04804B)
1207#define MCF_INTC0_ICR12            MCF_REG08(0xFC04804C)
1208#define MCF_INTC0_ICR13            MCF_REG08(0xFC04804D)
1209#define MCF_INTC0_ICR14            MCF_REG08(0xFC04804E)
1210#define MCF_INTC0_ICR15            MCF_REG08(0xFC04804F)
1211#define MCF_INTC0_ICR16            MCF_REG08(0xFC048050)
1212#define MCF_INTC0_ICR17            MCF_REG08(0xFC048051)
1213#define MCF_INTC0_ICR18            MCF_REG08(0xFC048052)
1214#define MCF_INTC0_ICR19            MCF_REG08(0xFC048053)
1215#define MCF_INTC0_ICR20            MCF_REG08(0xFC048054)
1216#define MCF_INTC0_ICR21            MCF_REG08(0xFC048055)
1217#define MCF_INTC0_ICR22            MCF_REG08(0xFC048056)
1218#define MCF_INTC0_ICR23            MCF_REG08(0xFC048057)
1219#define MCF_INTC0_ICR24            MCF_REG08(0xFC048058)
1220#define MCF_INTC0_ICR25            MCF_REG08(0xFC048059)
1221#define MCF_INTC0_ICR26            MCF_REG08(0xFC04805A)
1222#define MCF_INTC0_ICR27            MCF_REG08(0xFC04805B)
1223#define MCF_INTC0_ICR28            MCF_REG08(0xFC04805C)
1224#define MCF_INTC0_ICR29            MCF_REG08(0xFC04805D)
1225#define MCF_INTC0_ICR30            MCF_REG08(0xFC04805E)
1226#define MCF_INTC0_ICR31            MCF_REG08(0xFC04805F)
1227#define MCF_INTC0_ICR32            MCF_REG08(0xFC048060)
1228#define MCF_INTC0_ICR33            MCF_REG08(0xFC048061)
1229#define MCF_INTC0_ICR34            MCF_REG08(0xFC048062)
1230#define MCF_INTC0_ICR35            MCF_REG08(0xFC048063)
1231#define MCF_INTC0_ICR36            MCF_REG08(0xFC048064)
1232#define MCF_INTC0_ICR37            MCF_REG08(0xFC048065)
1233#define MCF_INTC0_ICR38            MCF_REG08(0xFC048066)
1234#define MCF_INTC0_ICR39            MCF_REG08(0xFC048067)
1235#define MCF_INTC0_ICR40            MCF_REG08(0xFC048068)
1236#define MCF_INTC0_ICR41            MCF_REG08(0xFC048069)
1237#define MCF_INTC0_ICR42            MCF_REG08(0xFC04806A)
1238#define MCF_INTC0_ICR43            MCF_REG08(0xFC04806B)
1239#define MCF_INTC0_ICR44            MCF_REG08(0xFC04806C)
1240#define MCF_INTC0_ICR45            MCF_REG08(0xFC04806D)
1241#define MCF_INTC0_ICR46            MCF_REG08(0xFC04806E)
1242#define MCF_INTC0_ICR47            MCF_REG08(0xFC04806F)
1243#define MCF_INTC0_ICR48            MCF_REG08(0xFC048070)
1244#define MCF_INTC0_ICR49            MCF_REG08(0xFC048071)
1245#define MCF_INTC0_ICR50            MCF_REG08(0xFC048072)
1246#define MCF_INTC0_ICR51            MCF_REG08(0xFC048073)
1247#define MCF_INTC0_ICR52            MCF_REG08(0xFC048074)
1248#define MCF_INTC0_ICR53            MCF_REG08(0xFC048075)
1249#define MCF_INTC0_ICR54            MCF_REG08(0xFC048076)
1250#define MCF_INTC0_ICR55            MCF_REG08(0xFC048077)
1251#define MCF_INTC0_ICR56            MCF_REG08(0xFC048078)
1252#define MCF_INTC0_ICR57            MCF_REG08(0xFC048079)
1253#define MCF_INTC0_ICR58            MCF_REG08(0xFC04807A)
1254#define MCF_INTC0_ICR59            MCF_REG08(0xFC04807B)
1255#define MCF_INTC0_ICR60            MCF_REG08(0xFC04807C)
1256#define MCF_INTC0_ICR61            MCF_REG08(0xFC04807D)
1257#define MCF_INTC0_ICR62            MCF_REG08(0xFC04807E)
1258#define MCF_INTC0_ICR63            MCF_REG08(0xFC04807F)
1259#define MCF_INTC0_ICR(x)           MCF_REG08(0xFC048040+((x)*0x001))
1260#define MCF_INTC0_SWIACK           MCF_REG08(0xFC0480E0)
1261#define MCF_INTC0_L1IACK           MCF_REG08(0xFC0480E4)
1262#define MCF_INTC0_L2IACK           MCF_REG08(0xFC0480E8)
1263#define MCF_INTC0_L3IACK           MCF_REG08(0xFC0480EC)
1264#define MCF_INTC0_L4IACK           MCF_REG08(0xFC0480F0)
1265#define MCF_INTC0_L5IACK           MCF_REG08(0xFC0480F4)
1266#define MCF_INTC0_L6IACK           MCF_REG08(0xFC0480F8)
1267#define MCF_INTC0_L7IACK           MCF_REG08(0xFC0480FC)
1268#define MCF_INTC0_LIACK(x)         MCF_REG08(0xFC0480E4+((x)*0x004))
1269#define MCF_INTC1_IPRH             MCF_REG32(0xFC04C000)
1270#define MCF_INTC1_IPRL             MCF_REG32(0xFC04C004)
1271#define MCF_INTC1_IMRH             MCF_REG32(0xFC04C008)
1272#define MCF_INTC1_IMRL             MCF_REG32(0xFC04C00C)
1273#define MCF_INTC1_INTFRCH          MCF_REG32(0xFC04C010)
1274#define MCF_INTC1_INTFRCL          MCF_REG32(0xFC04C014)
1275#define MCF_INTC1_ICONFIG          MCF_REG16(0xFC04C01A)
1276#define MCF_INTC1_SIMR             MCF_REG08(0xFC04C01C)
1277#define MCF_INTC1_CIMR             MCF_REG08(0xFC04C01D)
1278#define MCF_INTC1_CLMASK           MCF_REG08(0xFC04C01E)
1279#define MCF_INTC1_SLMASK           MCF_REG08(0xFC04C01F)
1280#define MCF_INTC1_ICR0             MCF_REG08(0xFC04C040)
1281#define MCF_INTC1_ICR1             MCF_REG08(0xFC04C041)
1282#define MCF_INTC1_ICR2             MCF_REG08(0xFC04C042)
1283#define MCF_INTC1_ICR3             MCF_REG08(0xFC04C043)
1284#define MCF_INTC1_ICR4             MCF_REG08(0xFC04C044)
1285#define MCF_INTC1_ICR5             MCF_REG08(0xFC04C045)
1286#define MCF_INTC1_ICR6             MCF_REG08(0xFC04C046)
1287#define MCF_INTC1_ICR7             MCF_REG08(0xFC04C047)
1288#define MCF_INTC1_ICR8             MCF_REG08(0xFC04C048)
1289#define MCF_INTC1_ICR9             MCF_REG08(0xFC04C049)
1290#define MCF_INTC1_ICR10            MCF_REG08(0xFC04C04A)
1291#define MCF_INTC1_ICR11            MCF_REG08(0xFC04C04B)
1292#define MCF_INTC1_ICR12            MCF_REG08(0xFC04C04C)
1293#define MCF_INTC1_ICR13            MCF_REG08(0xFC04C04D)
1294#define MCF_INTC1_ICR14            MCF_REG08(0xFC04C04E)
1295#define MCF_INTC1_ICR15            MCF_REG08(0xFC04C04F)
1296#define MCF_INTC1_ICR16            MCF_REG08(0xFC04C050)
1297#define MCF_INTC1_ICR17            MCF_REG08(0xFC04C051)
1298#define MCF_INTC1_ICR18            MCF_REG08(0xFC04C052)
1299#define MCF_INTC1_ICR19            MCF_REG08(0xFC04C053)
1300#define MCF_INTC1_ICR20            MCF_REG08(0xFC04C054)
1301#define MCF_INTC1_ICR21            MCF_REG08(0xFC04C055)
1302#define MCF_INTC1_ICR22            MCF_REG08(0xFC04C056)
1303#define MCF_INTC1_ICR23            MCF_REG08(0xFC04C057)
1304#define MCF_INTC1_ICR24            MCF_REG08(0xFC04C058)
1305#define MCF_INTC1_ICR25            MCF_REG08(0xFC04C059)
1306#define MCF_INTC1_ICR26            MCF_REG08(0xFC04C05A)
1307#define MCF_INTC1_ICR27            MCF_REG08(0xFC04C05B)
1308#define MCF_INTC1_ICR28            MCF_REG08(0xFC04C05C)
1309#define MCF_INTC1_ICR29            MCF_REG08(0xFC04C05D)
1310#define MCF_INTC1_ICR30            MCF_REG08(0xFC04C05E)
1311#define MCF_INTC1_ICR31            MCF_REG08(0xFC04C05F)
1312#define MCF_INTC1_ICR32            MCF_REG08(0xFC04C060)
1313#define MCF_INTC1_ICR33            MCF_REG08(0xFC04C061)
1314#define MCF_INTC1_ICR34            MCF_REG08(0xFC04C062)
1315#define MCF_INTC1_ICR35            MCF_REG08(0xFC04C063)
1316#define MCF_INTC1_ICR36            MCF_REG08(0xFC04C064)
1317#define MCF_INTC1_ICR37            MCF_REG08(0xFC04C065)
1318#define MCF_INTC1_ICR38            MCF_REG08(0xFC04C066)
1319#define MCF_INTC1_ICR39            MCF_REG08(0xFC04C067)
1320#define MCF_INTC1_ICR40            MCF_REG08(0xFC04C068)
1321#define MCF_INTC1_ICR41            MCF_REG08(0xFC04C069)
1322#define MCF_INTC1_ICR42            MCF_REG08(0xFC04C06A)
1323#define MCF_INTC1_ICR43            MCF_REG08(0xFC04C06B)
1324#define MCF_INTC1_ICR44            MCF_REG08(0xFC04C06C)
1325#define MCF_INTC1_ICR45            MCF_REG08(0xFC04C06D)
1326#define MCF_INTC1_ICR46            MCF_REG08(0xFC04C06E)
1327#define MCF_INTC1_ICR47            MCF_REG08(0xFC04C06F)
1328#define MCF_INTC1_ICR48            MCF_REG08(0xFC04C070)
1329#define MCF_INTC1_ICR49            MCF_REG08(0xFC04C071)
1330#define MCF_INTC1_ICR50            MCF_REG08(0xFC04C072)
1331#define MCF_INTC1_ICR51            MCF_REG08(0xFC04C073)
1332#define MCF_INTC1_ICR52            MCF_REG08(0xFC04C074)
1333#define MCF_INTC1_ICR53            MCF_REG08(0xFC04C075)
1334#define MCF_INTC1_ICR54            MCF_REG08(0xFC04C076)
1335#define MCF_INTC1_ICR55            MCF_REG08(0xFC04C077)
1336#define MCF_INTC1_ICR56            MCF_REG08(0xFC04C078)
1337#define MCF_INTC1_ICR57            MCF_REG08(0xFC04C079)
1338#define MCF_INTC1_ICR58            MCF_REG08(0xFC04C07A)
1339#define MCF_INTC1_ICR59            MCF_REG08(0xFC04C07B)
1340#define MCF_INTC1_ICR60            MCF_REG08(0xFC04C07C)
1341#define MCF_INTC1_ICR61            MCF_REG08(0xFC04C07D)
1342#define MCF_INTC1_ICR62            MCF_REG08(0xFC04C07E)
1343#define MCF_INTC1_ICR63            MCF_REG08(0xFC04C07F)
1344#define MCF_INTC1_ICR(x)           MCF_REG08(0xFC04C040+((x)*0x001))
1345#define MCF_INTC1_SWIACK           MCF_REG08(0xFC04C0E0)
1346#define MCF_INTC1_L1IACK           MCF_REG08(0xFC04C0E4)
1347#define MCF_INTC1_L2IACK           MCF_REG08(0xFC04C0E8)
1348#define MCF_INTC1_L3IACK           MCF_REG08(0xFC04C0EC)
1349#define MCF_INTC1_L4IACK           MCF_REG08(0xFC04C0F0)
1350#define MCF_INTC1_L5IACK           MCF_REG08(0xFC04C0F4)
1351#define MCF_INTC1_L6IACK           MCF_REG08(0xFC04C0F8)
1352#define MCF_INTC1_L7IACK           MCF_REG08(0xFC04C0FC)
1353#define MCF_INTC1_LIACK(x)         MCF_REG08(0xFC04C0E4+((x)*0x004))
1354#define MCF_INTC_IPRH(x)           MCF_REG32(0xFC048000+((x)*0x4000))
1355#define MCF_INTC_IPRL(x)           MCF_REG32(0xFC048004+((x)*0x4000))
1356#define MCF_INTC_IMRH(x)           MCF_REG32(0xFC048008+((x)*0x4000))
1357#define MCF_INTC_IMRL(x)           MCF_REG32(0xFC04800C+((x)*0x4000))
1358#define MCF_INTC_INTFRCH(x)        MCF_REG32(0xFC048010+((x)*0x4000))
1359#define MCF_INTC_INTFRCL(x)        MCF_REG32(0xFC048014+((x)*0x4000))
1360#define MCF_INTC_ICONFIG(x)        MCF_REG16(0xFC04801A+((x)*0x4000))
1361#define MCF_INTC_SIMR(x)           MCF_REG08(0xFC04801C+((x)*0x4000))
1362#define MCF_INTC_CIMR(x)           MCF_REG08(0xFC04801D+((x)*0x4000))
1363#define MCF_INTC_CLMASK(x)         MCF_REG08(0xFC04801E+((x)*0x4000))
1364#define MCF_INTC_SLMASK(x)         MCF_REG08(0xFC04801F+((x)*0x4000))
1365#define MCF_INTC_ICR0(x)           MCF_REG08(0xFC048040+((x)*0x4000))
1366#define MCF_INTC_ICR1(x)           MCF_REG08(0xFC048041+((x)*0x4000))
1367#define MCF_INTC_ICR2(x)           MCF_REG08(0xFC048042+((x)*0x4000))
1368#define MCF_INTC_ICR3(x)           MCF_REG08(0xFC048043+((x)*0x4000))
1369#define MCF_INTC_ICR4(x)           MCF_REG08(0xFC048044+((x)*0x4000))
1370#define MCF_INTC_ICR5(x)           MCF_REG08(0xFC048045+((x)*0x4000))
1371#define MCF_INTC_ICR6(x)           MCF_REG08(0xFC048046+((x)*0x4000))
1372#define MCF_INTC_ICR7(x)           MCF_REG08(0xFC048047+((x)*0x4000))
1373#define MCF_INTC_ICR8(x)           MCF_REG08(0xFC048048+((x)*0x4000))
1374#define MCF_INTC_ICR9(x)           MCF_REG08(0xFC048049+((x)*0x4000))
1375#define MCF_INTC_ICR10(x)          MCF_REG08(0xFC04804A+((x)*0x4000))
1376#define MCF_INTC_ICR11(x)          MCF_REG08(0xFC04804B+((x)*0x4000))
1377#define MCF_INTC_ICR12(x)          MCF_REG08(0xFC04804C+((x)*0x4000))
1378#define MCF_INTC_ICR13(x)          MCF_REG08(0xFC04804D+((x)*0x4000))
1379#define MCF_INTC_ICR14(x)          MCF_REG08(0xFC04804E+((x)*0x4000))
1380#define MCF_INTC_ICR15(x)          MCF_REG08(0xFC04804F+((x)*0x4000))
1381#define MCF_INTC_ICR16(x)          MCF_REG08(0xFC048050+((x)*0x4000))
1382#define MCF_INTC_ICR17(x)          MCF_REG08(0xFC048051+((x)*0x4000))
1383#define MCF_INTC_ICR18(x)          MCF_REG08(0xFC048052+((x)*0x4000))
1384#define MCF_INTC_ICR19(x)          MCF_REG08(0xFC048053+((x)*0x4000))
1385#define MCF_INTC_ICR20(x)          MCF_REG08(0xFC048054+((x)*0x4000))
1386#define MCF_INTC_ICR21(x)          MCF_REG08(0xFC048055+((x)*0x4000))
1387#define MCF_INTC_ICR22(x)          MCF_REG08(0xFC048056+((x)*0x4000))
1388#define MCF_INTC_ICR23(x)          MCF_REG08(0xFC048057+((x)*0x4000))
1389#define MCF_INTC_ICR24(x)          MCF_REG08(0xFC048058+((x)*0x4000))
1390#define MCF_INTC_ICR25(x)          MCF_REG08(0xFC048059+((x)*0x4000))
1391#define MCF_INTC_ICR26(x)          MCF_REG08(0xFC04805A+((x)*0x4000))
1392#define MCF_INTC_ICR27(x)          MCF_REG08(0xFC04805B+((x)*0x4000))
1393#define MCF_INTC_ICR28(x)          MCF_REG08(0xFC04805C+((x)*0x4000))
1394#define MCF_INTC_ICR29(x)          MCF_REG08(0xFC04805D+((x)*0x4000))
1395#define MCF_INTC_ICR30(x)          MCF_REG08(0xFC04805E+((x)*0x4000))
1396#define MCF_INTC_ICR31(x)          MCF_REG08(0xFC04805F+((x)*0x4000))
1397#define MCF_INTC_ICR32(x)          MCF_REG08(0xFC048060+((x)*0x4000))
1398#define MCF_INTC_ICR33(x)          MCF_REG08(0xFC048061+((x)*0x4000))
1399#define MCF_INTC_ICR34(x)          MCF_REG08(0xFC048062+((x)*0x4000))
1400#define MCF_INTC_ICR35(x)          MCF_REG08(0xFC048063+((x)*0x4000))
1401#define MCF_INTC_ICR36(x)          MCF_REG08(0xFC048064+((x)*0x4000))
1402#define MCF_INTC_ICR37(x)          MCF_REG08(0xFC048065+((x)*0x4000))
1403#define MCF_INTC_ICR38(x)          MCF_REG08(0xFC048066+((x)*0x4000))
1404#define MCF_INTC_ICR39(x)          MCF_REG08(0xFC048067+((x)*0x4000))
1405#define MCF_INTC_ICR40(x)          MCF_REG08(0xFC048068+((x)*0x4000))
1406#define MCF_INTC_ICR41(x)          MCF_REG08(0xFC048069+((x)*0x4000))
1407#define MCF_INTC_ICR42(x)          MCF_REG08(0xFC04806A+((x)*0x4000))
1408#define MCF_INTC_ICR43(x)          MCF_REG08(0xFC04806B+((x)*0x4000))
1409#define MCF_INTC_ICR44(x)          MCF_REG08(0xFC04806C+((x)*0x4000))
1410#define MCF_INTC_ICR45(x)          MCF_REG08(0xFC04806D+((x)*0x4000))
1411#define MCF_INTC_ICR46(x)          MCF_REG08(0xFC04806E+((x)*0x4000))
1412#define MCF_INTC_ICR47(x)          MCF_REG08(0xFC04806F+((x)*0x4000))
1413#define MCF_INTC_ICR48(x)          MCF_REG08(0xFC048070+((x)*0x4000))
1414#define MCF_INTC_ICR49(x)          MCF_REG08(0xFC048071+((x)*0x4000))
1415#define MCF_INTC_ICR50(x)          MCF_REG08(0xFC048072+((x)*0x4000))
1416#define MCF_INTC_ICR51(x)          MCF_REG08(0xFC048073+((x)*0x4000))
1417#define MCF_INTC_ICR52(x)          MCF_REG08(0xFC048074+((x)*0x4000))
1418#define MCF_INTC_ICR53(x)          MCF_REG08(0xFC048075+((x)*0x4000))
1419#define MCF_INTC_ICR54(x)          MCF_REG08(0xFC048076+((x)*0x4000))
1420#define MCF_INTC_ICR55(x)          MCF_REG08(0xFC048077+((x)*0x4000))
1421#define MCF_INTC_ICR56(x)          MCF_REG08(0xFC048078+((x)*0x4000))
1422#define MCF_INTC_ICR57(x)          MCF_REG08(0xFC048079+((x)*0x4000))
1423#define MCF_INTC_ICR58(x)          MCF_REG08(0xFC04807A+((x)*0x4000))
1424#define MCF_INTC_ICR59(x)          MCF_REG08(0xFC04807B+((x)*0x4000))
1425#define MCF_INTC_ICR60(x)          MCF_REG08(0xFC04807C+((x)*0x4000))
1426#define MCF_INTC_ICR61(x)          MCF_REG08(0xFC04807D+((x)*0x4000))
1427#define MCF_INTC_ICR62(x)          MCF_REG08(0xFC04807E+((x)*0x4000))
1428#define MCF_INTC_ICR63(x)          MCF_REG08(0xFC04807F+((x)*0x4000))
1429#define MCF_INTC_SWIACK(x)         MCF_REG08(0xFC0480E0+((x)*0x4000))
1430#define MCF_INTC_L1IACK(x)         MCF_REG08(0xFC0480E4+((x)*0x4000))
1431#define MCF_INTC_L2IACK(x)         MCF_REG08(0xFC0480E8+((x)*0x4000))
1432#define MCF_INTC_L3IACK(x)         MCF_REG08(0xFC0480EC+((x)*0x4000))
1433#define MCF_INTC_L4IACK(x)         MCF_REG08(0xFC0480F0+((x)*0x4000))
1434#define MCF_INTC_L5IACK(x)         MCF_REG08(0xFC0480F4+((x)*0x4000))
1435#define MCF_INTC_L6IACK(x)         MCF_REG08(0xFC0480F8+((x)*0x4000))
1436#define MCF_INTC_L7IACK(x)         MCF_REG08(0xFC0480FC+((x)*0x4000))
1437
1438/* Bit definitions and macros for MCF_INTC_IPRH */
1439#define MCF_INTC_IPRH_INT32        (0x00000001)
1440#define MCF_INTC_IPRH_INT33        (0x00000002)
1441#define MCF_INTC_IPRH_INT34        (0x00000004)
1442#define MCF_INTC_IPRH_INT35        (0x00000008)
1443#define MCF_INTC_IPRH_INT36        (0x00000010)
1444#define MCF_INTC_IPRH_INT37        (0x00000020)
1445#define MCF_INTC_IPRH_INT38        (0x00000040)
1446#define MCF_INTC_IPRH_INT39        (0x00000080)
1447#define MCF_INTC_IPRH_INT40        (0x00000100)
1448#define MCF_INTC_IPRH_INT41        (0x00000200)
1449#define MCF_INTC_IPRH_INT42        (0x00000400)
1450#define MCF_INTC_IPRH_INT43        (0x00000800)
1451#define MCF_INTC_IPRH_INT44        (0x00001000)
1452#define MCF_INTC_IPRH_INT45        (0x00002000)
1453#define MCF_INTC_IPRH_INT46        (0x00004000)
1454#define MCF_INTC_IPRH_INT47        (0x00008000)
1455#define MCF_INTC_IPRH_INT48        (0x00010000)
1456#define MCF_INTC_IPRH_INT49        (0x00020000)
1457#define MCF_INTC_IPRH_INT50        (0x00040000)
1458#define MCF_INTC_IPRH_INT51        (0x00080000)
1459#define MCF_INTC_IPRH_INT52        (0x00100000)
1460#define MCF_INTC_IPRH_INT53        (0x00200000)
1461#define MCF_INTC_IPRH_INT54        (0x00400000)
1462#define MCF_INTC_IPRH_INT55        (0x00800000)
1463#define MCF_INTC_IPRH_INT56        (0x01000000)
1464#define MCF_INTC_IPRH_INT57        (0x02000000)
1465#define MCF_INTC_IPRH_INT58        (0x04000000)
1466#define MCF_INTC_IPRH_INT59        (0x08000000)
1467#define MCF_INTC_IPRH_INT60        (0x10000000)
1468#define MCF_INTC_IPRH_INT61        (0x20000000)
1469#define MCF_INTC_IPRH_INT62        (0x40000000)
1470#define MCF_INTC_IPRH_INT63        (0x80000000)
1471
1472/* Bit definitions and macros for MCF_INTC_IPRL */
1473#define MCF_INTC_IPRL_INT0         (0x00000001)
1474#define MCF_INTC_IPRL_INT1         (0x00000002)
1475#define MCF_INTC_IPRL_INT2         (0x00000004)
1476#define MCF_INTC_IPRL_INT3         (0x00000008)
1477#define MCF_INTC_IPRL_INT4         (0x00000010)
1478#define MCF_INTC_IPRL_INT5         (0x00000020)
1479#define MCF_INTC_IPRL_INT6         (0x00000040)
1480#define MCF_INTC_IPRL_INT7         (0x00000080)
1481#define MCF_INTC_IPRL_INT8         (0x00000100)
1482#define MCF_INTC_IPRL_INT9         (0x00000200)
1483#define MCF_INTC_IPRL_INT10        (0x00000400)
1484#define MCF_INTC_IPRL_INT11        (0x00000800)
1485#define MCF_INTC_IPRL_INT12        (0x00001000)
1486#define MCF_INTC_IPRL_INT13        (0x00002000)
1487#define MCF_INTC_IPRL_INT14        (0x00004000)
1488#define MCF_INTC_IPRL_INT15        (0x00008000)
1489#define MCF_INTC_IPRL_INT16        (0x00010000)
1490#define MCF_INTC_IPRL_INT17        (0x00020000)
1491#define MCF_INTC_IPRL_INT18        (0x00040000)
1492#define MCF_INTC_IPRL_INT19        (0x00080000)
1493#define MCF_INTC_IPRL_INT20        (0x00100000)
1494#define MCF_INTC_IPRL_INT21        (0x00200000)
1495#define MCF_INTC_IPRL_INT22        (0x00400000)
1496#define MCF_INTC_IPRL_INT23        (0x00800000)
1497#define MCF_INTC_IPRL_INT24        (0x01000000)
1498#define MCF_INTC_IPRL_INT25        (0x02000000)
1499#define MCF_INTC_IPRL_INT26        (0x04000000)
1500#define MCF_INTC_IPRL_INT27        (0x08000000)
1501#define MCF_INTC_IPRL_INT28        (0x10000000)
1502#define MCF_INTC_IPRL_INT29        (0x20000000)
1503#define MCF_INTC_IPRL_INT30        (0x40000000)
1504#define MCF_INTC_IPRL_INT31        (0x80000000)
1505
1506/* Bit definitions and macros for MCF_INTC_IMRH */
1507#define MCF_INTC_IMRH_INT_MASK32   (0x00000001)
1508#define MCF_INTC_IMRH_INT_MASK33   (0x00000002)
1509#define MCF_INTC_IMRH_INT_MASK34   (0x00000004)
1510#define MCF_INTC_IMRH_INT_MASK35   (0x00000008)
1511#define MCF_INTC_IMRH_INT_MASK36   (0x00000010)
1512#define MCF_INTC_IMRH_INT_MASK37   (0x00000020)
1513#define MCF_INTC_IMRH_INT_MASK38   (0x00000040)
1514#define MCF_INTC_IMRH_INT_MASK39   (0x00000080)
1515#define MCF_INTC_IMRH_INT_MASK40   (0x00000100)
1516#define MCF_INTC_IMRH_INT_MASK41   (0x00000200)
1517#define MCF_INTC_IMRH_INT_MASK42   (0x00000400)
1518#define MCF_INTC_IMRH_INT_MASK43   (0x00000800)
1519#define MCF_INTC_IMRH_INT_MASK44   (0x00001000)
1520#define MCF_INTC_IMRH_INT_MASK45   (0x00002000)
1521#define MCF_INTC_IMRH_INT_MASK46   (0x00004000)
1522#define MCF_INTC_IMRH_INT_MASK47   (0x00008000)
1523#define MCF_INTC_IMRH_INT_MASK48   (0x00010000)
1524#define MCF_INTC_IMRH_INT_MASK49   (0x00020000)
1525#define MCF_INTC_IMRH_INT_MASK50   (0x00040000)
1526#define MCF_INTC_IMRH_INT_MASK51   (0x00080000)
1527#define MCF_INTC_IMRH_INT_MASK52   (0x00100000)
1528#define MCF_INTC_IMRH_INT_MASK53   (0x00200000)
1529#define MCF_INTC_IMRH_INT_MASK54   (0x00400000)
1530#define MCF_INTC_IMRH_INT_MASK55   (0x00800000)
1531#define MCF_INTC_IMRH_INT_MASK56   (0x01000000)
1532#define MCF_INTC_IMRH_INT_MASK57   (0x02000000)
1533#define MCF_INTC_IMRH_INT_MASK58   (0x04000000)
1534#define MCF_INTC_IMRH_INT_MASK59   (0x08000000)
1535#define MCF_INTC_IMRH_INT_MASK60   (0x10000000)
1536#define MCF_INTC_IMRH_INT_MASK61   (0x20000000)
1537#define MCF_INTC_IMRH_INT_MASK62   (0x40000000)
1538#define MCF_INTC_IMRH_INT_MASK63   (0x80000000)
1539
1540/* Bit definitions and macros for MCF_INTC_IMRL */
1541#define MCF_INTC_IMRL_INT_MASK0    (0x00000001)
1542#define MCF_INTC_IMRL_INT_MASK1    (0x00000002)
1543#define MCF_INTC_IMRL_INT_MASK2    (0x00000004)
1544#define MCF_INTC_IMRL_INT_MASK3    (0x00000008)
1545#define MCF_INTC_IMRL_INT_MASK4    (0x00000010)
1546#define MCF_INTC_IMRL_INT_MASK5    (0x00000020)
1547#define MCF_INTC_IMRL_INT_MASK6    (0x00000040)
1548#define MCF_INTC_IMRL_INT_MASK7    (0x00000080)
1549#define MCF_INTC_IMRL_INT_MASK8    (0x00000100)
1550#define MCF_INTC_IMRL_INT_MASK9    (0x00000200)
1551#define MCF_INTC_IMRL_INT_MASK10   (0x00000400)
1552#define MCF_INTC_IMRL_INT_MASK11   (0x00000800)
1553#define MCF_INTC_IMRL_INT_MASK12   (0x00001000)
1554#define MCF_INTC_IMRL_INT_MASK13   (0x00002000)
1555#define MCF_INTC_IMRL_INT_MASK14   (0x00004000)
1556#define MCF_INTC_IMRL_INT_MASK15   (0x00008000)
1557#define MCF_INTC_IMRL_INT_MASK16   (0x00010000)
1558#define MCF_INTC_IMRL_INT_MASK17   (0x00020000)
1559#define MCF_INTC_IMRL_INT_MASK18   (0x00040000)
1560#define MCF_INTC_IMRL_INT_MASK19   (0x00080000)
1561#define MCF_INTC_IMRL_INT_MASK20   (0x00100000)
1562#define MCF_INTC_IMRL_INT_MASK21   (0x00200000)
1563#define MCF_INTC_IMRL_INT_MASK22   (0x00400000)
1564#define MCF_INTC_IMRL_INT_MASK23   (0x00800000)
1565#define MCF_INTC_IMRL_INT_MASK24   (0x01000000)
1566#define MCF_INTC_IMRL_INT_MASK25   (0x02000000)
1567#define MCF_INTC_IMRL_INT_MASK26   (0x04000000)
1568#define MCF_INTC_IMRL_INT_MASK27   (0x08000000)
1569#define MCF_INTC_IMRL_INT_MASK28   (0x10000000)
1570#define MCF_INTC_IMRL_INT_MASK29   (0x20000000)
1571#define MCF_INTC_IMRL_INT_MASK30   (0x40000000)
1572#define MCF_INTC_IMRL_INT_MASK31   (0x80000000)
1573
1574/* Bit definitions and macros for MCF_INTC_INTFRCH */
1575#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
1576#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
1577#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
1578#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
1579#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
1580#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
1581#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
1582#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
1583#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
1584#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
1585#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
1586#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
1587#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
1588#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
1589#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
1590#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
1591#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
1592#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
1593#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
1594#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
1595#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
1596#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
1597#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
1598#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
1599#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
1600#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
1601#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
1602#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
1603#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
1604#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
1605#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
1606#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
1607
1608/* Bit definitions and macros for MCF_INTC_INTFRCL */
1609#define MCF_INTC_INTFRCL_INTFRC0   (0x00000001)
1610#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
1611#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
1612#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
1613#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
1614#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
1615#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
1616#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
1617#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
1618#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
1619#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
1620#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
1621#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
1622#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
1623#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
1624#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
1625#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
1626#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
1627#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
1628#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
1629#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
1630#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
1631#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
1632#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
1633#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
1634#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
1635#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
1636#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
1637#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
1638#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
1639#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
1640#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
1641
1642/* Bit definitions and macros for MCF_INTC_ICONFIG */
1643#define MCF_INTC_ICONFIG_EMASK     (0x0020)
1644#define MCF_INTC_ICONFIG_ELVLPRI1  (0x0200)
1645#define MCF_INTC_ICONFIG_ELVLPRI2  (0x0400)
1646#define MCF_INTC_ICONFIG_ELVLPRI3  (0x0800)
1647#define MCF_INTC_ICONFIG_ELVLPRI4  (0x1000)
1648#define MCF_INTC_ICONFIG_ELVLPRI5  (0x2000)
1649#define MCF_INTC_ICONFIG_ELVLPRI6  (0x4000)
1650#define MCF_INTC_ICONFIG_ELVLPRI7  (0x8000)
1651
1652/* Bit definitions and macros for MCF_INTC_SIMR */
1653#define MCF_INTC_SIMR_SIMR(x)      (((x)&0x7F)<<0)
1654
1655/* Bit definitions and macros for MCF_INTC_CIMR */
1656#define MCF_INTC_CIMR_CIMR(x)      (((x)&0x7F)<<0)
1657
1658/* Bit definitions and macros for MCF_INTC_CLMASK */
1659#define MCF_INTC_CLMASK_CLMASK(x)  (((x)&0x0F)<<0)
1660
1661/* Bit definitions and macros for MCF_INTC_SLMASK */
1662#define MCF_INTC_SLMASK_SLMASK(x)  (((x)&0x0F)<<0)
1663
1664/* Bit definitions and macros for MCF_INTC_ICR */
1665#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<0)
1666
1667/* Bit definitions and macros for MCF_INTC_SWIACK */
1668#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
1669
1670/* Bit definitions and macros for MCF_INTC_LIACK */
1671#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
1672
1673/********************************************************************/
1674/*********************************************************************
1675*
1676* LCD Controller (LCDC)
1677*
1678*********************************************************************/
1679
1680/* Register read/write macros */
1681#define MCF_LCDC_LSSAR                  MCF_REG32(0xFC0AC000)
1682#define MCF_LCDC_LSR                    MCF_REG32(0xFC0AC004)
1683#define MCF_LCDC_LVPWR                  MCF_REG32(0xFC0AC008)
1684#define MCF_LCDC_LCPR                   MCF_REG32(0xFC0AC00C)
1685#define MCF_LCDC_LCWHBR                 MCF_REG32(0xFC0AC010)
1686#define MCF_LCDC_LCCMR                  MCF_REG32(0xFC0AC014)
1687#define MCF_LCDC_LPCR                   MCF_REG32(0xFC0AC018)
1688#define MCF_LCDC_LHCR                   MCF_REG32(0xFC0AC01C)
1689#define MCF_LCDC_LVCR                   MCF_REG32(0xFC0AC020)
1690#define MCF_LCDC_LPOR                   MCF_REG32(0xFC0AC024)
1691#define MCF_LCDC_LSCR                   MCF_REG32(0xFC0AC028)
1692#define MCF_LCDC_LPCCR                  MCF_REG32(0xFC0AC02C)
1693#define MCF_LCDC_LDCR                   MCF_REG32(0xFC0AC030)
1694#define MCF_LCDC_LRMCR                  MCF_REG32(0xFC0AC034)
1695#define MCF_LCDC_LICR                   MCF_REG32(0xFC0AC038)
1696#define MCF_LCDC_LIER                   MCF_REG32(0xFC0AC03C)
1697#define MCF_LCDC_LISR                   MCF_REG32(0xFC0AC040)
1698#define MCF_LCDC_LGWSAR                 MCF_REG32(0xFC0AC050)
1699#define MCF_LCDC_LGWSR                  MCF_REG32(0xFC0AC054)
1700#define MCF_LCDC_LGWVPWR                MCF_REG32(0xFC0AC058)
1701#define MCF_LCDC_LGWPOR                 MCF_REG32(0xFC0AC05C)
1702#define MCF_LCDC_LGWPR                  MCF_REG32(0xFC0AC060)
1703#define MCF_LCDC_LGWCR                  MCF_REG32(0xFC0AC064)
1704#define MCF_LCDC_LGWDCR                 MCF_REG32(0xFC0AC068)
1705#define MCF_LCDC_BPLUT_BASE             MCF_REG32(0xFC0AC800)
1706#define MCF_LCDC_GWLUT_BASE             MCF_REG32(0xFC0ACC00)
1707
1708/* Bit definitions and macros for MCF_LCDC_LSSAR */
1709#define MCF_LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
1710
1711/* Bit definitions and macros for MCF_LCDC_LSR */
1712#define MCF_LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
1713#define MCF_LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
1714
1715/* Bit definitions and macros for MCF_LCDC_LVPWR */
1716#define MCF_LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
1717
1718/* Bit definitions and macros for MCF_LCDC_LCPR */
1719#define MCF_LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
1720#define MCF_LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
1721#define MCF_LCDC_LCPR_OP                (0x10000000)
1722#define MCF_LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
1723#define MCF_LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
1724#define MCF_LCDC_LCPR_CC_OR             (0x40000000)
1725#define MCF_LCDC_LCPR_CC_XOR            (0x80000000)
1726#define MCF_LCDC_LCPR_CC_AND            (0xC0000000)
1727#define MCF_LCDC_LCPR_OP_ON             (0x10000000)
1728#define MCF_LCDC_LCPR_OP_OFF            (0x00000000)
1729
1730/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1731#define MCF_LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
1732#define MCF_LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
1733#define MCF_LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
1734#define MCF_LCDC_LCWHBR_BK_EN           (0x80000000)
1735#define MCF_LCDC_LCWHBR_BK_EN_ON        (0x80000000)
1736#define MCF_LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
1737
1738/* Bit definitions and macros for MCF_LCDC_LCCMR */
1739#define MCF_LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
1740#define MCF_LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
1741#define MCF_LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
1742
1743/* Bit definitions and macros for MCF_LCDC_LPCR */
1744#define MCF_LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
1745#define MCF_LCDC_LPCR_SHARP             (0x00000040)
1746#define MCF_LCDC_LPCR_SCLKSEL           (0x00000080)
1747#define MCF_LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
1748#define MCF_LCDC_LPCR_ACDSEL            (0x00008000)
1749#define MCF_LCDC_LPCR_REV_VS            (0x00010000)
1750#define MCF_LCDC_LPCR_SWAP_SEL          (0x00020000)
1751#define MCF_LCDC_LPCR_ENDSEL            (0x00040000)
1752#define MCF_LCDC_LPCR_SCLKIDLE          (0x00080000)
1753#define MCF_LCDC_LPCR_OEPOL             (0x00100000)
1754#define MCF_LCDC_LPCR_CLKPOL            (0x00200000)
1755#define MCF_LCDC_LPCR_LPPOL             (0x00400000)
1756#define MCF_LCDC_LPCR_FLM               (0x00800000)
1757#define MCF_LCDC_LPCR_PIXPOL            (0x01000000)
1758#define MCF_LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
1759#define MCF_LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
1760#define MCF_LCDC_LPCR_COLOR             (0x40000000)
1761#define MCF_LCDC_LPCR_TFT               (0x80000000)
1762#define MCF_LCDC_LPCR_MODE_MONOCGROME   (0x00000000)
1763#define MCF_LCDC_LPCR_MODE_CSTN         (0x40000000)
1764#define MCF_LCDC_LPCR_MODE_TFT          (0xC0000000)
1765#define MCF_LCDC_LPCR_PBSIZ_1           (0x00000000)
1766#define MCF_LCDC_LPCR_PBSIZ_2           (0x10000000)
1767#define MCF_LCDC_LPCR_PBSIZ_4           (0x20000000)
1768#define MCF_LCDC_LPCR_PBSIZ_8           (0x30000000)
1769#define MCF_LCDC_LPCR_BPIX_1bpp         (0x00000000)
1770#define MCF_LCDC_LPCR_BPIX_2bpp         (0x02000000)
1771#define MCF_LCDC_LPCR_BPIX_4bpp         (0x04000000)
1772#define MCF_LCDC_LPCR_BPIX_8bpp         (0x06000000)
1773#define MCF_LCDC_LPCR_BPIX_12bpp        (0x08000000)
1774#define MCF_LCDC_LPCR_BPIX_16bpp        (0x0A000000)
1775#define MCF_LCDC_LPCR_BPIX_18bpp        (0x0C000000)
1776
1777#define MCF_LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30)
1778
1779/* Bit definitions and macros for MCF_LCDC_LHCR */
1780#define MCF_LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
1781#define MCF_LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
1782#define MCF_LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
1783
1784/* Bit definitions and macros for MCF_LCDC_LVCR */
1785#define MCF_LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
1786#define MCF_LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
1787#define MCF_LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
1788
1789/* Bit definitions and macros for MCF_LCDC_LPOR */
1790#define MCF_LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
1791
1792/* Bit definitions and macros for MCF_LCDC_LPCCR */
1793#define MCF_LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
1794#define MCF_LCDC_LPCCR_CC_EN            (0x00000100)
1795#define MCF_LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
1796#define MCF_LCDC_LPCCR_LDMSK            (0x00008000)
1797#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
1798#define MCF_LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
1799#define MCF_LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
1800#define MCF_LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
1801
1802/* Bit definitions and macros for MCF_LCDC_LDCR */
1803#define MCF_LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
1804#define MCF_LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
1805#define MCF_LCDC_LDCR_BURST             (0x80000000)
1806
1807/* Bit definitions and macros for MCF_LCDC_LRMCR */
1808#define MCF_LCDC_LRMCR_SEL_REF          (0x00000001)
1809
1810/* Bit definitions and macros for MCF_LCDC_LICR */
1811#define MCF_LCDC_LICR_INTCON            (0x00000001)
1812#define MCF_LCDC_LICR_INTSYN            (0x00000004)
1813#define MCF_LCDC_LICR_GW_INT_CON        (0x00000010)
1814
1815/* Bit definitions and macros for MCF_LCDC_LIER */
1816#define MCF_LCDC_LIER_BOF_EN            (0x00000001)
1817#define MCF_LCDC_LIER_EOF_EN            (0x00000002)
1818#define MCF_LCDC_LIER_ERR_RES_EN        (0x00000004)
1819#define MCF_LCDC_LIER_UDR_ERR_EN        (0x00000008)
1820#define MCF_LCDC_LIER_GW_BOF_EN         (0x00000010)
1821#define MCF_LCDC_LIER_GW_EOF_EN         (0x00000020)
1822#define MCF_LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
1823#define MCF_LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
1824
1825/* Bit definitions and macros for MCF_LCDC_LISR */
1826#define MCF_LCDC_LISR_BOF               (0x00000001)
1827#define MCF_LCDC_LISR_EOF               (0x00000002)
1828#define MCF_LCDC_LISR_ERR_RES           (0x00000004)
1829#define MCF_LCDC_LISR_UDR_ERR           (0x00000008)
1830#define MCF_LCDC_LISR_GW_BOF            (0x00000010)
1831#define MCF_LCDC_LISR_GW_EOF            (0x00000020)
1832#define MCF_LCDC_LISR_GW_ERR_RES        (0x00000040)
1833#define MCF_LCDC_LISR_GW_UDR_ERR        (0x00000080)
1834
1835/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1836#define MCF_LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
1837
1838/* Bit definitions and macros for MCF_LCDC_LGWSR */
1839#define MCF_LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
1840#define MCF_LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
1841
1842/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1843#define MCF_LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
1844
1845/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1846#define MCF_LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
1847
1848/* Bit definitions and macros for MCF_LCDC_LGWPR */
1849#define MCF_LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
1850#define MCF_LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
1851
1852/* Bit definitions and macros for MCF_LCDC_LGWCR */
1853#define MCF_LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
1854#define MCF_LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
1855#define MCF_LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
1856#define MCF_LCDC_LGWCR_GW_RVS           (0x00200000)
1857#define MCF_LCDC_LGWCR_GWE              (0x00400000)
1858#define MCF_LCDC_LGWCR_GWCKE            (0x00800000)
1859#define MCF_LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
1860
1861/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1862#define MCF_LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
1863#define MCF_LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
1864#define MCF_LCDC_LGWDCR_GWBT            (0x80000000)
1865
1866/* Bit definitions and macros for MCF_LCDC_LSCR */
1867#define MCF_LCDC_LSCR_PS_RISE_DELAY(x)    (((x)&0x0000003F)<<26)
1868#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x)   (((x)&0x000000FF)<<16)
1869#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1870#define MCF_LCDC_LSCR_GRAY_2(x)  		  (((x)&0x0000000F)<<4)
1871#define MCF_LCDC_LSCR_GRAY_1(x)  		  (((x)&0x0000000F)<<0)
1872
1873/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1874#define MCF_LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
1875
1876/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1877#define MCF_LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
1878
1879/*********************************************************************
1880 *
1881 * Phase Locked Loop (PLL)
1882 *
1883 *********************************************************************/
1884
1885/* Register read/write macros */
1886#define MCF_PLL_PODR              MCF_REG08(0xFC0C0000)
1887#define MCF_PLL_PLLCR             MCF_REG08(0xFC0C0004)
1888#define MCF_PLL_PMDR              MCF_REG08(0xFC0C0008)
1889#define MCF_PLL_PFDR              MCF_REG08(0xFC0C000C)
1890
1891/* Bit definitions and macros for MCF_PLL_PODR */
1892#define MCF_PLL_PODR_BUSDIV(x)    (((x)&0x0F)<<0)
1893#define MCF_PLL_PODR_CPUDIV(x)    (((x)&0x0F)<<4)
1894
1895/* Bit definitions and macros for MCF_PLL_PLLCR */
1896#define MCF_PLL_PLLCR_DITHDEV(x)  (((x)&0x07)<<0)
1897#define MCF_PLL_PLLCR_DITHEN      (0x80)
1898
1899/* Bit definitions and macros for MCF_PLL_PMDR */
1900#define MCF_PLL_PMDR_MODDIV(x)    (((x)&0xFF)<<0)
1901
1902/* Bit definitions and macros for MCF_PLL_PFDR */
1903#define MCF_PLL_PFDR_MFD(x)       (((x)&0xFF)<<0)
1904
1905/*********************************************************************
1906 *
1907 * System Control Module Registers (SCM)
1908 *
1909 *********************************************************************/
1910
1911/* Register read/write macros */
1912#define MCF_SCM_MPR			MCF_REG32(0xFC000000)
1913#define MCF_SCM_PACRA			MCF_REG32(0xFC000020)
1914#define MCF_SCM_PACRB			MCF_REG32(0xFC000024)
1915#define MCF_SCM_PACRC			MCF_REG32(0xFC000028)
1916#define MCF_SCM_PACRD			MCF_REG32(0xFC00002C)
1917#define MCF_SCM_PACRE			MCF_REG32(0xFC000040)
1918#define MCF_SCM_PACRF			MCF_REG32(0xFC000044)
1919
1920#define MCF_SCM_BCR			MCF_REG32(0xFC040024)
1921
1922/*********************************************************************
1923 *
1924 * SDRAM Controller (SDRAMC)
1925 *
1926 *********************************************************************/
1927
1928/* Register read/write macros */
1929#define MCF_SDRAMC_SDMR			MCF_REG32(0xFC0B8000)
1930#define MCF_SDRAMC_SDCR			MCF_REG32(0xFC0B8004)
1931#define MCF_SDRAMC_SDCFG1		MCF_REG32(0xFC0B8008)
1932#define MCF_SDRAMC_SDCFG2		MCF_REG32(0xFC0B800C)
1933#define MCF_SDRAMC_LIMP_FIX		MCF_REG32(0xFC0B8080)
1934#define MCF_SDRAMC_SDDS			MCF_REG32(0xFC0B8100)
1935#define MCF_SDRAMC_SDCS0		MCF_REG32(0xFC0B8110)
1936#define MCF_SDRAMC_SDCS1		MCF_REG32(0xFC0B8114)
1937#define MCF_SDRAMC_SDCS2		MCF_REG32(0xFC0B8118)
1938#define MCF_SDRAMC_SDCS3		MCF_REG32(0xFC0B811C)
1939#define MCF_SDRAMC_SDCS(x)		MCF_REG32(0xFC0B8110+((x)*0x004))
1940
1941/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1942#define MCF_SDRAMC_SDMR_CMD		(0x00010000)
1943#define MCF_SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)
1944#define MCF_SDRAMC_SDMR_BNKAD(x)	(((x)&0x00000003)<<30)
1945#define MCF_SDRAMC_SDMR_BNKAD_LMR	(0x00000000)
1946#define MCF_SDRAMC_SDMR_BNKAD_LEMR	(0x40000000)
1947
1948/* Bit definitions and macros for MCF_SDRAMC_SDCR */
1949#define MCF_SDRAMC_SDCR_IPALL		(0x00000002)
1950#define MCF_SDRAMC_SDCR_IREF		(0x00000004)
1951#define MCF_SDRAMC_SDCR_DQS_OE(x)	(((x)&0x0000000F)<<8)
1952#define MCF_SDRAMC_SDCR_PS(x)		(((x)&0x00000003)<<12)
1953#define MCF_SDRAMC_SDCR_RCNT(x)		(((x)&0x0000003F)<<16)
1954#define MCF_SDRAMC_SDCR_OE_RULE		(0x00400000)
1955#define MCF_SDRAMC_SDCR_MUX(x)		(((x)&0x00000003)<<24)
1956#define MCF_SDRAMC_SDCR_REF		(0x10000000)
1957#define MCF_SDRAMC_SDCR_DDR		(0x20000000)
1958#define MCF_SDRAMC_SDCR_CKE		(0x40000000)
1959#define MCF_SDRAMC_SDCR_MODE_EN		(0x80000000)
1960#define MCF_SDRAMC_SDCR_PS_16		(0x00002000)
1961#define MCF_SDRAMC_SDCR_PS_32		(0x00000000)
1962
1963/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
1964#define MCF_SDRAMC_SDCFG1_WTLAT(x)	(((x)&0x00000007)<<4)
1965#define MCF_SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)
1966#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)
1967#define MCF_SDRAMC_SDCFG1_ACT2RW(x)	(((x)&0x00000007)<<16)
1968#define MCF_SDRAMC_SDCFG1_RDLAT(x)	(((x)&0x0000000F)<<20)
1969#define MCF_SDRAMC_SDCFG1_SWT2RD(x)	(((x)&0x00000007)<<24)
1970#define MCF_SDRAMC_SDCFG1_SRD2RW(x)	(((x)&0x0000000F)<<28)
1971
1972/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
1973#define MCF_SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)
1974#define MCF_SDRAMC_SDCFG2_BRD2WT(x)	(((x)&0x0000000F)<<20)
1975#define MCF_SDRAMC_SDCFG2_BWT2RW(x)	(((x)&0x0000000F)<<24)
1976#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)	(((x)&0x0000000F)<<28)
1977
1978#define MCF_SDRAMC_REFRESH		(0x40000000)
1979
1980/* Bit definitions and macros for MCF_SDRAMC_SDDS */
1981#define MCF_SDRAMC_SDDS_SB_D(x)		(((x)&0x00000003)<<0)
1982#define MCF_SDRAMC_SDDS_SB_S(x)		(((x)&0x00000003)<<2)
1983#define MCF_SDRAMC_SDDS_SB_A(x)		(((x)&0x00000003)<<4)
1984#define MCF_SDRAMC_SDDS_SB_C(x)		(((x)&0x00000003)<<6)
1985#define MCF_SDRAMC_SDDS_SB_E(x)		(((x)&0x00000003)<<8)
1986
1987/* Bit definitions and macros for MCF_SDRAMC_SDCS */
1988#define MCF_SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F)<<0)
1989#define MCF_SDRAMC_SDCS_BASE(x)		(((x)&0x00000FFF)<<20)
1990#define MCF_SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
1991#define MCF_SDRAMC_SDCS_CSSZ_DIABLE	(0x00000000)
1992#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE	(0x00000013)
1993#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE	(0x00000014)
1994#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE	(0x00000015)
1995#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE	(0x00000016)
1996#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
1997#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
1998#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
1999#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
2000#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
2001#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
2002#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE	(0x0000001D)
2003#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE	(0x0000001E)
2004#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE	(0x0000001F)
2005
2006/*********************************************************************
2007 *
2008 *      FlexCAN module registers
2009 *
2010 *********************************************************************/
2011#define MCF_FLEXCAN_BASEADDR(x)		(0xFC020000+(x)*0x0800)
2012#define MCF_FLEXCAN_CANMCR(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2013#define MCF_FLEXCAN_CANCTRL(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2014#define MCF_FLEXCAN_TIMER(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2015#define MCF_FLEXCAN_RXGMASK(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2016#define MCF_FLEXCAN_RX14MASK(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2017#define MCF_FLEXCAN_RX15MASK(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2018#define MCF_FLEXCAN_ERRCNT(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2019#define MCF_FLEXCAN_ERRSTAT(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2020#define MCF_FLEXCAN_IMASK(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2021#define MCF_FLEXCAN_IFLAG(x)		MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2022
2023#define MCF_FLEXCAN_MB_CNT(x,y)		MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2024#define MCF_FLEXCAN_MB_ID(x,y)		MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2025#define MCF_FLEXCAN_MB_DB(x,y,z)	MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2026
2027/*
2028 *      FlexCAN Module Configuration Register
2029 */
2030#define CANMCR_MDIS		(0x80000000)
2031#define CANMCR_FRZ		(0x40000000)
2032#define CANMCR_HALT		(0x10000000)
2033#define CANMCR_SOFTRST		(0x02000000)
2034#define CANMCR_FRZACK		(0x01000000)
2035#define CANMCR_SUPV		(0x00800000)
2036#define CANMCR_MAXMB(x)         ((x)&0x0F)
2037
2038/*
2039 *      FlexCAN Control Register
2040 */
2041#define CANCTRL_PRESDIV(x)      (((x)&0xFF)<<24)
2042#define CANCTRL_RJW(x)          (((x)&0x03)<<22)
2043#define CANCTRL_PSEG1(x)        (((x)&0x07)<<19)
2044#define CANCTRL_PSEG2(x)        (((x)&0x07)<<16)
2045#define CANCTRL_BOFFMSK         (0x00008000)
2046#define CANCTRL_ERRMSK	        (0x00004000)
2047#define CANCTRL_CLKSRC		(0x00002000)
2048#define CANCTRL_LPB	        (0x00001000)
2049#define CANCTRL_SAMP	        (0x00000080)
2050#define CANCTRL_BOFFREC         (0x00000040)
2051#define CANCTRL_TSYNC           (0x00000020)
2052#define CANCTRL_LBUF            (0x00000010)
2053#define CANCTRL_LOM             (0x00000008)
2054#define CANCTRL_PROPSEG(x)      ((x)&0x07)
2055
2056/*
2057 *      FlexCAN Error Counter Register
2058 */
2059#define ERRCNT_RXECTR(x)        (((x)&0xFF)<<8)
2060#define ERRCNT_TXECTR(x)        ((x)&0xFF)
2061
2062/*
2063 *      FlexCAN Error and Status Register
2064 */
2065#define ERRSTAT_BITERR(x)       (((x)&0x03)<<14)
2066#define ERRSTAT_ACKERR           (0x00002000)
2067#define ERRSTAT_CRCERR           (0x00001000)
2068#define ERRSTAT_FRMERR           (0x00000800)
2069#define ERRSTAT_STFERR           (0x00000400)
2070#define ERRSTAT_TXWRN            (0x00000200)
2071#define ERRSTAT_RXWRN            (0x00000100)
2072#define ERRSTAT_IDLE             (0x00000080)
2073#define ERRSTAT_TXRX             (0x00000040)
2074#define ERRSTAT_FLTCONF(x)       (((x)&0x03)<<4)
2075#define ERRSTAT_BOFFINT          (0x00000004)
2076#define ERRSTAT_ERRINT           (0x00000002)
2077
2078/*
2079 *      Interrupt Mask Register
2080 */
2081#define IMASK_BUF15M		(0x8000)
2082#define IMASK_BUF14M		(0x4000)
2083#define IMASK_BUF13M		(0x2000)
2084#define IMASK_BUF12M		(0x1000)
2085#define IMASK_BUF11M		(0x0800)
2086#define IMASK_BUF10M		(0x0400)
2087#define IMASK_BUF9M		(0x0200)
2088#define IMASK_BUF8M		(0x0100)
2089#define IMASK_BUF7M		(0x0080)
2090#define IMASK_BUF6M		(0x0040)
2091#define IMASK_BUF5M		(0x0020)
2092#define IMASK_BUF4M		(0x0010)
2093#define IMASK_BUF3M		(0x0008)
2094#define IMASK_BUF2M		(0x0004)
2095#define IMASK_BUF1M		(0x0002)
2096#define IMASK_BUF0M		(0x0001)
2097#define IMASK_BUFnM(x)		(0x1<<(x))
2098#define IMASK_BUFF_ENABLE_ALL	(0x1111)
2099#define IMASK_BUFF_DISABLE_ALL	(0x0000)
2100
2101/*
2102 *      Interrupt Flag Register
2103 */
2104#define IFLAG_BUF15M		(0x8000)
2105#define IFLAG_BUF14M		(0x4000)
2106#define IFLAG_BUF13M		(0x2000)
2107#define IFLAG_BUF12M		(0x1000)
2108#define IFLAG_BUF11M		(0x0800)
2109#define IFLAG_BUF10M		(0x0400)
2110#define IFLAG_BUF9M		(0x0200)
2111#define IFLAG_BUF8M		(0x0100)
2112#define IFLAG_BUF7M		(0x0080)
2113#define IFLAG_BUF6M		(0x0040)
2114#define IFLAG_BUF5M		(0x0020)
2115#define IFLAG_BUF4M		(0x0010)
2116#define IFLAG_BUF3M		(0x0008)
2117#define IFLAG_BUF2M		(0x0004)
2118#define IFLAG_BUF1M		(0x0002)
2119#define IFLAG_BUF0M		(0x0001)
2120#define IFLAG_BUFF_SET_ALL	(0xFFFF)
2121#define IFLAG_BUFF_CLEAR_ALL	(0x0000)
2122#define IFLAG_BUFnM(x)		(0x1<<(x))
2123
2124/*
2125 *      Message Buffers
2126 */
2127#define MB_CNT_CODE(x)		(((x)&0x0F)<<24)
2128#define MB_CNT_SRR		(0x00400000)
2129#define MB_CNT_IDE		(0x00200000)
2130#define MB_CNT_RTR		(0x00100000)
2131#define MB_CNT_LENGTH(x)	(((x)&0x0F)<<16)
2132#define MB_CNT_TIMESTAMP(x)	((x)&0xFFFF)
2133#define MB_ID_STD(x)		(((x)&0x07FF)<<18)
2134#define MB_ID_EXT(x)		((x)&0x3FFFF)
2135
2136/*********************************************************************
2137 *
2138 * Edge Port Module (EPORT)
2139 *
2140 *********************************************************************/
2141
2142/* Register read/write macros */
2143#define MCF_EPORT_EPPAR                MCF_REG16(0xFC094000)
2144#define MCF_EPORT_EPDDR                MCF_REG08(0xFC094002)
2145#define MCF_EPORT_EPIER                MCF_REG08(0xFC094003)
2146#define MCF_EPORT_EPDR                 MCF_REG08(0xFC094004)
2147#define MCF_EPORT_EPPDR                MCF_REG08(0xFC094005)
2148#define MCF_EPORT_EPFR                 MCF_REG08(0xFC094006)
2149
2150/* Bit definitions and macros for MCF_EPORT_EPPAR */
2151#define MCF_EPORT_EPPAR_EPPA1(x)       (((x)&0x0003)<<2)
2152#define MCF_EPORT_EPPAR_EPPA2(x)       (((x)&0x0003)<<4)
2153#define MCF_EPORT_EPPAR_EPPA3(x)       (((x)&0x0003)<<6)
2154#define MCF_EPORT_EPPAR_EPPA4(x)       (((x)&0x0003)<<8)
2155#define MCF_EPORT_EPPAR_EPPA5(x)       (((x)&0x0003)<<10)
2156#define MCF_EPORT_EPPAR_EPPA6(x)       (((x)&0x0003)<<12)
2157#define MCF_EPORT_EPPAR_EPPA7(x)       (((x)&0x0003)<<14)
2158#define MCF_EPORT_EPPAR_LEVEL          (0)
2159#define MCF_EPORT_EPPAR_RISING         (1)
2160#define MCF_EPORT_EPPAR_FALLING        (2)
2161#define MCF_EPORT_EPPAR_BOTH           (3)
2162#define MCF_EPORT_EPPAR_EPPA7_LEVEL    (0x0000)
2163#define MCF_EPORT_EPPAR_EPPA7_RISING   (0x4000)
2164#define MCF_EPORT_EPPAR_EPPA7_FALLING  (0x8000)
2165#define MCF_EPORT_EPPAR_EPPA7_BOTH     (0xC000)
2166#define MCF_EPORT_EPPAR_EPPA6_LEVEL    (0x0000)
2167#define MCF_EPORT_EPPAR_EPPA6_RISING   (0x1000)
2168#define MCF_EPORT_EPPAR_EPPA6_FALLING  (0x2000)
2169#define MCF_EPORT_EPPAR_EPPA6_BOTH     (0x3000)
2170#define MCF_EPORT_EPPAR_EPPA5_LEVEL    (0x0000)
2171#define MCF_EPORT_EPPAR_EPPA5_RISING   (0x0400)
2172#define MCF_EPORT_EPPAR_EPPA5_FALLING  (0x0800)
2173#define MCF_EPORT_EPPAR_EPPA5_BOTH     (0x0C00)
2174#define MCF_EPORT_EPPAR_EPPA4_LEVEL    (0x0000)
2175#define MCF_EPORT_EPPAR_EPPA4_RISING   (0x0100)
2176#define MCF_EPORT_EPPAR_EPPA4_FALLING  (0x0200)
2177#define MCF_EPORT_EPPAR_EPPA4_BOTH     (0x0300)
2178#define MCF_EPORT_EPPAR_EPPA3_LEVEL    (0x0000)
2179#define MCF_EPORT_EPPAR_EPPA3_RISING   (0x0040)
2180#define MCF_EPORT_EPPAR_EPPA3_FALLING  (0x0080)
2181#define MCF_EPORT_EPPAR_EPPA3_BOTH     (0x00C0)
2182#define MCF_EPORT_EPPAR_EPPA2_LEVEL    (0x0000)
2183#define MCF_EPORT_EPPAR_EPPA2_RISING   (0x0010)
2184#define MCF_EPORT_EPPAR_EPPA2_FALLING  (0x0020)
2185#define MCF_EPORT_EPPAR_EPPA2_BOTH     (0x0030)
2186#define MCF_EPORT_EPPAR_EPPA1_LEVEL    (0x0000)
2187#define MCF_EPORT_EPPAR_EPPA1_RISING   (0x0004)
2188#define MCF_EPORT_EPPAR_EPPA1_FALLING  (0x0008)
2189#define MCF_EPORT_EPPAR_EPPA1_BOTH     (0x000C)
2190
2191/* Bit definitions and macros for MCF_EPORT_EPDDR */
2192#define MCF_EPORT_EPDDR_EPDD1          (0x02)
2193#define MCF_EPORT_EPDDR_EPDD2          (0x04)
2194#define MCF_EPORT_EPDDR_EPDD3          (0x08)
2195#define MCF_EPORT_EPDDR_EPDD4          (0x10)
2196#define MCF_EPORT_EPDDR_EPDD5          (0x20)
2197#define MCF_EPORT_EPDDR_EPDD6          (0x40)
2198#define MCF_EPORT_EPDDR_EPDD7          (0x80)
2199
2200/* Bit definitions and macros for MCF_EPORT_EPIER */
2201#define MCF_EPORT_EPIER_EPIE1          (0x02)
2202#define MCF_EPORT_EPIER_EPIE2          (0x04)
2203#define MCF_EPORT_EPIER_EPIE3          (0x08)
2204#define MCF_EPORT_EPIER_EPIE4          (0x10)
2205#define MCF_EPORT_EPIER_EPIE5          (0x20)
2206#define MCF_EPORT_EPIER_EPIE6          (0x40)
2207#define MCF_EPORT_EPIER_EPIE7          (0x80)
2208
2209/* Bit definitions and macros for MCF_EPORT_EPDR */
2210#define MCF_EPORT_EPDR_EPD1            (0x02)
2211#define MCF_EPORT_EPDR_EPD2            (0x04)
2212#define MCF_EPORT_EPDR_EPD3            (0x08)
2213#define MCF_EPORT_EPDR_EPD4            (0x10)
2214#define MCF_EPORT_EPDR_EPD5            (0x20)
2215#define MCF_EPORT_EPDR_EPD6            (0x40)
2216#define MCF_EPORT_EPDR_EPD7            (0x80)
2217
2218/* Bit definitions and macros for MCF_EPORT_EPPDR */
2219#define MCF_EPORT_EPPDR_EPPD1          (0x02)
2220#define MCF_EPORT_EPPDR_EPPD2          (0x04)
2221#define MCF_EPORT_EPPDR_EPPD3          (0x08)
2222#define MCF_EPORT_EPPDR_EPPD4          (0x10)
2223#define MCF_EPORT_EPPDR_EPPD5          (0x20)
2224#define MCF_EPORT_EPPDR_EPPD6          (0x40)
2225#define MCF_EPORT_EPPDR_EPPD7          (0x80)
2226
2227/* Bit definitions and macros for MCF_EPORT_EPFR */
2228#define MCF_EPORT_EPFR_EPF1            (0x02)
2229#define MCF_EPORT_EPFR_EPF2            (0x04)
2230#define MCF_EPORT_EPFR_EPF3            (0x08)
2231#define MCF_EPORT_EPFR_EPF4            (0x10)
2232#define MCF_EPORT_EPFR_EPF5            (0x20)
2233#define MCF_EPORT_EPFR_EPF6            (0x40)
2234#define MCF_EPORT_EPFR_EPF7            (0x80)
2235
2236/********************************************************************/
2237#endif	/* m532xsim_h */
2238