1/****************************************************************************/
2
3/*
4 *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
5 *
6 *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
7 */
8
9/****************************************************************************/
10#ifndef m520xsim_h
11#define m520xsim_h
12/****************************************************************************/
13
14
15/*
16 *  Define the 5282 SIM register set addresses.
17 */
18#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
19#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
20#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
21#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
22#define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
23#define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
24#define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
25#define MCFINTC_ICR0        0x40        /* Base ICR register */
26
27#define MCFINT_VECBASE      64
28#define MCFINT_UART0        26          /* Interrupt number for UART0 */
29#define MCFINT_UART1        27          /* Interrupt number for UART1 */
30#define MCFINT_UART2        28          /* Interrupt number for UART2 */
31#define MCFINT_QSPI         31          /* Interrupt number for QSPI */
32#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
33
34/*
35 *  SDRAM configuration registers.
36 */
37#define MCFSIM_SDMR         0x000a8000	/* SDRAM Mode/Extended Mode Register */
38#define MCFSIM_SDCR         0x000a8004	/* SDRAM Control Register */
39#define MCFSIM_SDCFG1       0x000a8008	/* SDRAM Configuration Register 1 */
40#define MCFSIM_SDCFG2       0x000a800c	/* SDRAM Configuration Register 2 */
41#define MCFSIM_SDCS0        0x000a8110	/* SDRAM Chip Select 0 Configuration */
42#define MCFSIM_SDCS1        0x000a8114	/* SDRAM Chip Select 1 Configuration */
43
44
45#define MCF_GPIO_PAR_UART                   (0xA4036)
46#define MCF_GPIO_PAR_FECI2C                 (0xA4033)
47#define MCF_GPIO_PAR_FEC                    (0xA4038)
48
49#define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
50#define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
51
52#define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
53#define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
54
55#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
56#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
57
58#define ICR_INTRCONF		0x05
59#define MCFPIT_IMR		MCFINTC_IMRL
60#define MCFPIT_IMR_IBIT		(1 << MCFINT_PIT1)
61
62/****************************************************************************/
63#endif  /* m520xsim_h */
64