1#ifndef __iop_sw_cfg_defs_h 2#define __iop_sw_cfg_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:10:19 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r 11 * id: $Id: iop_sw_cfg_defs.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16/* Main access macros */ 17#ifndef REG_RD 18#define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21#endif 22 23#ifndef REG_WR 24#define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27#endif 28 29#ifndef REG_RD_VECT 30#define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34#endif 35 36#ifndef REG_WR_VECT 37#define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41#endif 42 43#ifndef REG_RD_INT 44#define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46#endif 47 48#ifndef REG_WR_INT 49#define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51#endif 52 53#ifndef REG_RD_INT_VECT 54#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57#endif 58 59#ifndef REG_WR_INT_VECT 60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63#endif 64 65#ifndef REG_TYPE_CONV 66#define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68#endif 69 70#ifndef reg_page_size 71#define reg_page_size 8192 72#endif 73 74#ifndef REG_ADDR 75#define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77#endif 78 79#ifndef REG_ADDR_VECT 80#define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83#endif 84 85/* C-code for register scope iop_sw_cfg */ 86 87/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ 88typedef struct { 89 unsigned int cfg : 2; 90 unsigned int dummy1 : 30; 91} reg_iop_sw_cfg_rw_crc_par0_owner; 92#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 93#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 94 95/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ 96typedef struct { 97 unsigned int cfg : 2; 98 unsigned int dummy1 : 30; 99} reg_iop_sw_cfg_rw_crc_par1_owner; 100#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 101#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 102 103/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ 104typedef struct { 105 unsigned int cfg : 2; 106 unsigned int dummy1 : 30; 107} reg_iop_sw_cfg_rw_dmc_in0_owner; 108#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 109#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 110 111/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ 112typedef struct { 113 unsigned int cfg : 2; 114 unsigned int dummy1 : 30; 115} reg_iop_sw_cfg_rw_dmc_in1_owner; 116#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 117#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 118 119/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ 120typedef struct { 121 unsigned int cfg : 2; 122 unsigned int dummy1 : 30; 123} reg_iop_sw_cfg_rw_dmc_out0_owner; 124#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 125#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 126 127/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ 128typedef struct { 129 unsigned int cfg : 2; 130 unsigned int dummy1 : 30; 131} reg_iop_sw_cfg_rw_dmc_out1_owner; 132#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 133#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 134 135/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ 136typedef struct { 137 unsigned int cfg : 2; 138 unsigned int dummy1 : 30; 139} reg_iop_sw_cfg_rw_fifo_in0_owner; 140#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 141#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 142 143/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ 144typedef struct { 145 unsigned int cfg : 2; 146 unsigned int dummy1 : 30; 147} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; 148#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 149#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 150 151/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ 152typedef struct { 153 unsigned int cfg : 2; 154 unsigned int dummy1 : 30; 155} reg_iop_sw_cfg_rw_fifo_in1_owner; 156#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 157#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 158 159/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ 160typedef struct { 161 unsigned int cfg : 2; 162 unsigned int dummy1 : 30; 163} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; 164#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 165#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 166 167/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ 168typedef struct { 169 unsigned int cfg : 2; 170 unsigned int dummy1 : 30; 171} reg_iop_sw_cfg_rw_fifo_out0_owner; 172#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 173#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 174 175/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ 176typedef struct { 177 unsigned int cfg : 2; 178 unsigned int dummy1 : 30; 179} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; 180#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 181#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 182 183/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ 184typedef struct { 185 unsigned int cfg : 2; 186 unsigned int dummy1 : 30; 187} reg_iop_sw_cfg_rw_fifo_out1_owner; 188#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 189#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 190 191/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ 192typedef struct { 193 unsigned int cfg : 2; 194 unsigned int dummy1 : 30; 195} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; 196#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 197#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 198 199/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ 200typedef struct { 201 unsigned int cfg : 2; 202 unsigned int dummy1 : 30; 203} reg_iop_sw_cfg_rw_sap_in_owner; 204#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 205#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 206 207/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ 208typedef struct { 209 unsigned int cfg : 2; 210 unsigned int dummy1 : 30; 211} reg_iop_sw_cfg_rw_sap_out_owner; 212#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 213#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 214 215/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ 216typedef struct { 217 unsigned int cfg : 2; 218 unsigned int dummy1 : 30; 219} reg_iop_sw_cfg_rw_scrc_in0_owner; 220#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 221#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 222 223/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ 224typedef struct { 225 unsigned int cfg : 2; 226 unsigned int dummy1 : 30; 227} reg_iop_sw_cfg_rw_scrc_in1_owner; 228#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 229#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 230 231/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ 232typedef struct { 233 unsigned int cfg : 2; 234 unsigned int dummy1 : 30; 235} reg_iop_sw_cfg_rw_scrc_out0_owner; 236#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 237#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 238 239/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ 240typedef struct { 241 unsigned int cfg : 2; 242 unsigned int dummy1 : 30; 243} reg_iop_sw_cfg_rw_scrc_out1_owner; 244#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 245#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 246 247/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ 248typedef struct { 249 unsigned int cfg : 2; 250 unsigned int dummy1 : 30; 251} reg_iop_sw_cfg_rw_spu0_owner; 252#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 253#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 254 255/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ 256typedef struct { 257 unsigned int cfg : 2; 258 unsigned int dummy1 : 30; 259} reg_iop_sw_cfg_rw_spu1_owner; 260#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 261#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 262 263/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ 264typedef struct { 265 unsigned int cfg : 2; 266 unsigned int dummy1 : 30; 267} reg_iop_sw_cfg_rw_timer_grp0_owner; 268#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 269#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 270 271/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ 272typedef struct { 273 unsigned int cfg : 2; 274 unsigned int dummy1 : 30; 275} reg_iop_sw_cfg_rw_timer_grp1_owner; 276#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 277#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 278 279/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ 280typedef struct { 281 unsigned int cfg : 2; 282 unsigned int dummy1 : 30; 283} reg_iop_sw_cfg_rw_timer_grp2_owner; 284#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 285#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 286 287/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ 288typedef struct { 289 unsigned int cfg : 2; 290 unsigned int dummy1 : 30; 291} reg_iop_sw_cfg_rw_timer_grp3_owner; 292#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 293#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 294 295/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ 296typedef struct { 297 unsigned int cfg : 2; 298 unsigned int dummy1 : 30; 299} reg_iop_sw_cfg_rw_trigger_grp0_owner; 300#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 301#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 302 303/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ 304typedef struct { 305 unsigned int cfg : 2; 306 unsigned int dummy1 : 30; 307} reg_iop_sw_cfg_rw_trigger_grp1_owner; 308#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 309#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 310 311/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ 312typedef struct { 313 unsigned int cfg : 2; 314 unsigned int dummy1 : 30; 315} reg_iop_sw_cfg_rw_trigger_grp2_owner; 316#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 317#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 318 319/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ 320typedef struct { 321 unsigned int cfg : 2; 322 unsigned int dummy1 : 30; 323} reg_iop_sw_cfg_rw_trigger_grp3_owner; 324#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 325#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 326 327/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ 328typedef struct { 329 unsigned int cfg : 2; 330 unsigned int dummy1 : 30; 331} reg_iop_sw_cfg_rw_trigger_grp4_owner; 332#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 333#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 334 335/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ 336typedef struct { 337 unsigned int cfg : 2; 338 unsigned int dummy1 : 30; 339} reg_iop_sw_cfg_rw_trigger_grp5_owner; 340#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 341#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 342 343/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ 344typedef struct { 345 unsigned int cfg : 2; 346 unsigned int dummy1 : 30; 347} reg_iop_sw_cfg_rw_trigger_grp6_owner; 348#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 349#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 350 351/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ 352typedef struct { 353 unsigned int cfg : 2; 354 unsigned int dummy1 : 30; 355} reg_iop_sw_cfg_rw_trigger_grp7_owner; 356#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 357#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 358 359/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ 360typedef struct { 361 unsigned int byte0 : 8; 362 unsigned int byte1 : 8; 363 unsigned int byte2 : 8; 364 unsigned int byte3 : 8; 365} reg_iop_sw_cfg_rw_bus0_mask; 366#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 367#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 368 369/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ 370typedef struct { 371 unsigned int byte0 : 1; 372 unsigned int byte1 : 1; 373 unsigned int byte2 : 1; 374 unsigned int byte3 : 1; 375 unsigned int dummy1 : 28; 376} reg_iop_sw_cfg_rw_bus0_oe_mask; 377#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 378#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 379 380/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ 381typedef struct { 382 unsigned int byte0 : 8; 383 unsigned int byte1 : 8; 384 unsigned int byte2 : 8; 385 unsigned int byte3 : 8; 386} reg_iop_sw_cfg_rw_bus1_mask; 387#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 388#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 389 390/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ 391typedef struct { 392 unsigned int byte0 : 1; 393 unsigned int byte1 : 1; 394 unsigned int byte2 : 1; 395 unsigned int byte3 : 1; 396 unsigned int dummy1 : 28; 397} reg_iop_sw_cfg_rw_bus1_oe_mask; 398#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 399#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 400 401/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ 402typedef struct { 403 unsigned int val : 32; 404} reg_iop_sw_cfg_rw_gio_mask; 405#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 406#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 407 408/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ 409typedef struct { 410 unsigned int val : 32; 411} reg_iop_sw_cfg_rw_gio_oe_mask; 412#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 413#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 414 415/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ 416typedef struct { 417 unsigned int bus0_byte0 : 2; 418 unsigned int bus0_byte1 : 2; 419 unsigned int bus0_byte2 : 2; 420 unsigned int bus0_byte3 : 2; 421 unsigned int bus1_byte0 : 2; 422 unsigned int bus1_byte1 : 2; 423 unsigned int bus1_byte2 : 2; 424 unsigned int bus1_byte3 : 2; 425 unsigned int gio3_0 : 2; 426 unsigned int gio7_4 : 2; 427 unsigned int gio11_8 : 2; 428 unsigned int gio15_12 : 2; 429 unsigned int gio19_16 : 2; 430 unsigned int gio23_20 : 2; 431 unsigned int gio27_24 : 2; 432 unsigned int gio31_28 : 2; 433} reg_iop_sw_cfg_rw_pinmapping; 434#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 435#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 436 437/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ 438typedef struct { 439 unsigned int bus0_lo : 3; 440 unsigned int bus0_hi : 3; 441 unsigned int bus0_lo_oe : 3; 442 unsigned int bus0_hi_oe : 3; 443 unsigned int bus1_lo : 3; 444 unsigned int bus1_hi : 3; 445 unsigned int bus1_lo_oe : 3; 446 unsigned int bus1_hi_oe : 3; 447 unsigned int dummy1 : 8; 448} reg_iop_sw_cfg_rw_bus_out_cfg; 449#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 450#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 451 452/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ 453typedef struct { 454 unsigned int gio0 : 4; 455 unsigned int gio0_oe : 2; 456 unsigned int gio1 : 4; 457 unsigned int gio1_oe : 2; 458 unsigned int gio2 : 4; 459 unsigned int gio2_oe : 2; 460 unsigned int gio3 : 4; 461 unsigned int gio3_oe : 2; 462 unsigned int dummy1 : 8; 463} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; 464#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 465#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 466 467/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ 468typedef struct { 469 unsigned int gio4 : 4; 470 unsigned int gio4_oe : 2; 471 unsigned int gio5 : 4; 472 unsigned int gio5_oe : 2; 473 unsigned int gio6 : 4; 474 unsigned int gio6_oe : 2; 475 unsigned int gio7 : 4; 476 unsigned int gio7_oe : 2; 477 unsigned int dummy1 : 8; 478} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; 479#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 480#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 481 482/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ 483typedef struct { 484 unsigned int gio8 : 4; 485 unsigned int gio8_oe : 2; 486 unsigned int gio9 : 4; 487 unsigned int gio9_oe : 2; 488 unsigned int gio10 : 4; 489 unsigned int gio10_oe : 2; 490 unsigned int gio11 : 4; 491 unsigned int gio11_oe : 2; 492 unsigned int dummy1 : 8; 493} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; 494#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 495#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 496 497/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ 498typedef struct { 499 unsigned int gio12 : 4; 500 unsigned int gio12_oe : 2; 501 unsigned int gio13 : 4; 502 unsigned int gio13_oe : 2; 503 unsigned int gio14 : 4; 504 unsigned int gio14_oe : 2; 505 unsigned int gio15 : 4; 506 unsigned int gio15_oe : 2; 507 unsigned int dummy1 : 8; 508} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; 509#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 510#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 511 512/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ 513typedef struct { 514 unsigned int gio16 : 4; 515 unsigned int gio16_oe : 2; 516 unsigned int gio17 : 4; 517 unsigned int gio17_oe : 2; 518 unsigned int gio18 : 4; 519 unsigned int gio18_oe : 2; 520 unsigned int gio19 : 4; 521 unsigned int gio19_oe : 2; 522 unsigned int dummy1 : 8; 523} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; 524#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 525#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 526 527/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ 528typedef struct { 529 unsigned int gio20 : 4; 530 unsigned int gio20_oe : 2; 531 unsigned int gio21 : 4; 532 unsigned int gio21_oe : 2; 533 unsigned int gio22 : 4; 534 unsigned int gio22_oe : 2; 535 unsigned int gio23 : 4; 536 unsigned int gio23_oe : 2; 537 unsigned int dummy1 : 8; 538} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; 539#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 540#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 541 542/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ 543typedef struct { 544 unsigned int gio24 : 4; 545 unsigned int gio24_oe : 2; 546 unsigned int gio25 : 4; 547 unsigned int gio25_oe : 2; 548 unsigned int gio26 : 4; 549 unsigned int gio26_oe : 2; 550 unsigned int gio27 : 4; 551 unsigned int gio27_oe : 2; 552 unsigned int dummy1 : 8; 553} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; 554#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 555#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 556 557/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ 558typedef struct { 559 unsigned int gio28 : 4; 560 unsigned int gio28_oe : 2; 561 unsigned int gio29 : 4; 562 unsigned int gio29_oe : 2; 563 unsigned int gio30 : 4; 564 unsigned int gio30_oe : 2; 565 unsigned int gio31 : 4; 566 unsigned int gio31_oe : 2; 567 unsigned int dummy1 : 8; 568} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; 569#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 570#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 571 572/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ 573typedef struct { 574 unsigned int bus0_in : 2; 575 unsigned int bus1_in : 2; 576 unsigned int dummy1 : 28; 577} reg_iop_sw_cfg_rw_spu0_cfg; 578#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 579#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 580 581/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ 582typedef struct { 583 unsigned int bus0_in : 2; 584 unsigned int bus1_in : 2; 585 unsigned int dummy1 : 28; 586} reg_iop_sw_cfg_rw_spu1_cfg; 587#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 588#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 589 590/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ 591typedef struct { 592 unsigned int ext_clk : 3; 593 unsigned int tmr0_en : 1; 594 unsigned int tmr1_en : 1; 595 unsigned int tmr2_en : 1; 596 unsigned int tmr3_en : 1; 597 unsigned int tmr0_dis : 1; 598 unsigned int tmr1_dis : 1; 599 unsigned int tmr2_dis : 1; 600 unsigned int tmr3_dis : 1; 601 unsigned int dummy1 : 21; 602} reg_iop_sw_cfg_rw_timer_grp0_cfg; 603#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 604#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 605 606/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ 607typedef struct { 608 unsigned int ext_clk : 3; 609 unsigned int tmr0_en : 1; 610 unsigned int tmr1_en : 1; 611 unsigned int tmr2_en : 1; 612 unsigned int tmr3_en : 1; 613 unsigned int tmr0_dis : 1; 614 unsigned int tmr1_dis : 1; 615 unsigned int tmr2_dis : 1; 616 unsigned int tmr3_dis : 1; 617 unsigned int dummy1 : 21; 618} reg_iop_sw_cfg_rw_timer_grp1_cfg; 619#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 620#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 621 622/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ 623typedef struct { 624 unsigned int ext_clk : 3; 625 unsigned int tmr0_en : 1; 626 unsigned int tmr1_en : 1; 627 unsigned int tmr2_en : 1; 628 unsigned int tmr3_en : 1; 629 unsigned int tmr0_dis : 1; 630 unsigned int tmr1_dis : 1; 631 unsigned int tmr2_dis : 1; 632 unsigned int tmr3_dis : 1; 633 unsigned int dummy1 : 21; 634} reg_iop_sw_cfg_rw_timer_grp2_cfg; 635#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 636#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 637 638/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ 639typedef struct { 640 unsigned int ext_clk : 3; 641 unsigned int tmr0_en : 1; 642 unsigned int tmr1_en : 1; 643 unsigned int tmr2_en : 1; 644 unsigned int tmr3_en : 1; 645 unsigned int tmr0_dis : 1; 646 unsigned int tmr1_dis : 1; 647 unsigned int tmr2_dis : 1; 648 unsigned int tmr3_dis : 1; 649 unsigned int dummy1 : 21; 650} reg_iop_sw_cfg_rw_timer_grp3_cfg; 651#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 652#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 653 654/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ 655typedef struct { 656 unsigned int grp0_dis : 1; 657 unsigned int grp0_en : 1; 658 unsigned int grp1_dis : 1; 659 unsigned int grp1_en : 1; 660 unsigned int grp2_dis : 1; 661 unsigned int grp2_en : 1; 662 unsigned int grp3_dis : 1; 663 unsigned int grp3_en : 1; 664 unsigned int grp4_dis : 1; 665 unsigned int grp4_en : 1; 666 unsigned int grp5_dis : 1; 667 unsigned int grp5_en : 1; 668 unsigned int grp6_dis : 1; 669 unsigned int grp6_en : 1; 670 unsigned int grp7_dis : 1; 671 unsigned int grp7_en : 1; 672 unsigned int dummy1 : 16; 673} reg_iop_sw_cfg_rw_trigger_grps_cfg; 674#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 675#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 676 677/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ 678typedef struct { 679 unsigned int dmc0_usr : 1; 680 unsigned int out_strb : 5; 681 unsigned int in_src : 3; 682 unsigned int in_size : 3; 683 unsigned int in_last : 2; 684 unsigned int in_strb : 4; 685 unsigned int out_src : 1; 686 unsigned int dummy1 : 13; 687} reg_iop_sw_cfg_rw_pdp0_cfg; 688#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 689#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 690 691/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ 692typedef struct { 693 unsigned int dmc1_usr : 1; 694 unsigned int out_strb : 5; 695 unsigned int in_src : 3; 696 unsigned int in_size : 3; 697 unsigned int in_last : 2; 698 unsigned int in_strb : 4; 699 unsigned int out_src : 1; 700 unsigned int dummy1 : 13; 701} reg_iop_sw_cfg_rw_pdp1_cfg; 702#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 703#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 704 705/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ 706typedef struct { 707 unsigned int sdp_out0_strb : 3; 708 unsigned int sdp_out1_strb : 3; 709 unsigned int sdp_in0_data : 3; 710 unsigned int sdp_in0_last : 2; 711 unsigned int sdp_in0_strb : 3; 712 unsigned int sdp_in1_data : 3; 713 unsigned int sdp_in1_last : 2; 714 unsigned int sdp_in1_strb : 3; 715 unsigned int dummy1 : 10; 716} reg_iop_sw_cfg_rw_sdp_cfg; 717#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 718#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 719 720 721/* Constants */ 722enum { 723 regk_iop_sw_cfg_a = 0x00000001, 724 regk_iop_sw_cfg_b = 0x00000002, 725 regk_iop_sw_cfg_bus0 = 0x00000000, 726 regk_iop_sw_cfg_bus0_rot16 = 0x00000004, 727 regk_iop_sw_cfg_bus0_rot24 = 0x00000006, 728 regk_iop_sw_cfg_bus0_rot8 = 0x00000002, 729 regk_iop_sw_cfg_bus1 = 0x00000001, 730 regk_iop_sw_cfg_bus1_rot16 = 0x00000005, 731 regk_iop_sw_cfg_bus1_rot24 = 0x00000007, 732 regk_iop_sw_cfg_bus1_rot8 = 0x00000003, 733 regk_iop_sw_cfg_clk12 = 0x00000000, 734 regk_iop_sw_cfg_cpu = 0x00000000, 735 regk_iop_sw_cfg_dmc0 = 0x00000000, 736 regk_iop_sw_cfg_dmc1 = 0x00000001, 737 regk_iop_sw_cfg_gated_clk0 = 0x00000010, 738 regk_iop_sw_cfg_gated_clk1 = 0x00000011, 739 regk_iop_sw_cfg_gated_clk2 = 0x00000012, 740 regk_iop_sw_cfg_gated_clk3 = 0x00000013, 741 regk_iop_sw_cfg_gio0 = 0x00000004, 742 regk_iop_sw_cfg_gio1 = 0x00000001, 743 regk_iop_sw_cfg_gio2 = 0x00000005, 744 regk_iop_sw_cfg_gio3 = 0x00000002, 745 regk_iop_sw_cfg_gio4 = 0x00000006, 746 regk_iop_sw_cfg_gio5 = 0x00000003, 747 regk_iop_sw_cfg_gio6 = 0x00000007, 748 regk_iop_sw_cfg_gio7 = 0x00000004, 749 regk_iop_sw_cfg_gio_in0 = 0x00000000, 750 regk_iop_sw_cfg_gio_in1 = 0x00000001, 751 regk_iop_sw_cfg_gio_in10 = 0x00000002, 752 regk_iop_sw_cfg_gio_in11 = 0x00000003, 753 regk_iop_sw_cfg_gio_in14 = 0x00000004, 754 regk_iop_sw_cfg_gio_in15 = 0x00000005, 755 regk_iop_sw_cfg_gio_in18 = 0x00000002, 756 regk_iop_sw_cfg_gio_in19 = 0x00000003, 757 regk_iop_sw_cfg_gio_in20 = 0x00000004, 758 regk_iop_sw_cfg_gio_in21 = 0x00000005, 759 regk_iop_sw_cfg_gio_in26 = 0x00000006, 760 regk_iop_sw_cfg_gio_in27 = 0x00000007, 761 regk_iop_sw_cfg_gio_in28 = 0x00000006, 762 regk_iop_sw_cfg_gio_in29 = 0x00000007, 763 regk_iop_sw_cfg_gio_in4 = 0x00000000, 764 regk_iop_sw_cfg_gio_in5 = 0x00000001, 765 regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, 766 regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, 767 regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, 768 regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, 769 regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, 770 regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, 771 regk_iop_sw_cfg_mpu = 0x00000001, 772 regk_iop_sw_cfg_none = 0x00000000, 773 regk_iop_sw_cfg_par0 = 0x00000000, 774 regk_iop_sw_cfg_par1 = 0x00000001, 775 regk_iop_sw_cfg_pdp_out0 = 0x00000002, 776 regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, 777 regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, 778 regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, 779 regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, 780 regk_iop_sw_cfg_pdp_out1 = 0x00000003, 781 regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, 782 regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, 783 regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, 784 regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, 785 regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, 786 regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, 787 regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, 788 regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, 789 regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, 790 regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, 791 regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, 792 regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, 793 regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, 794 regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, 795 regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, 796 regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, 797 regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, 798 regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, 799 regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, 800 regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, 801 regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, 802 regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, 803 regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, 804 regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, 805 regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, 806 regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, 807 regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, 808 regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, 809 regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, 810 regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, 811 regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, 812 regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, 813 regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, 814 regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, 815 regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, 816 regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, 817 regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, 818 regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, 819 regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, 820 regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, 821 regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, 822 regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, 823 regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, 824 regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, 825 regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, 826 regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, 827 regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, 828 regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, 829 regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, 830 regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, 831 regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, 832 regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, 833 regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, 834 regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, 835 regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, 836 regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, 837 regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, 838 regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, 839 regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, 840 regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, 841 regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, 842 regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, 843 regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, 844 regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, 845 regk_iop_sw_cfg_sdp_out0 = 0x00000008, 846 regk_iop_sw_cfg_sdp_out1 = 0x00000009, 847 regk_iop_sw_cfg_size16 = 0x00000002, 848 regk_iop_sw_cfg_size24 = 0x00000003, 849 regk_iop_sw_cfg_size32 = 0x00000004, 850 regk_iop_sw_cfg_size8 = 0x00000001, 851 regk_iop_sw_cfg_spu0 = 0x00000002, 852 regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, 853 regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, 854 regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, 855 regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, 856 regk_iop_sw_cfg_spu0_g0 = 0x0000000e, 857 regk_iop_sw_cfg_spu0_g1 = 0x0000000e, 858 regk_iop_sw_cfg_spu0_g2 = 0x0000000e, 859 regk_iop_sw_cfg_spu0_g3 = 0x0000000e, 860 regk_iop_sw_cfg_spu0_g4 = 0x0000000e, 861 regk_iop_sw_cfg_spu0_g5 = 0x0000000e, 862 regk_iop_sw_cfg_spu0_g6 = 0x0000000e, 863 regk_iop_sw_cfg_spu0_g7 = 0x0000000e, 864 regk_iop_sw_cfg_spu0_gio0 = 0x00000000, 865 regk_iop_sw_cfg_spu0_gio1 = 0x00000001, 866 regk_iop_sw_cfg_spu0_gio2 = 0x00000000, 867 regk_iop_sw_cfg_spu0_gio5 = 0x00000005, 868 regk_iop_sw_cfg_spu0_gio6 = 0x00000006, 869 regk_iop_sw_cfg_spu0_gio7 = 0x00000007, 870 regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, 871 regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, 872 regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, 873 regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, 874 regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, 875 regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, 876 regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, 877 regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, 878 regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, 879 regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, 880 regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, 881 regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, 882 regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, 883 regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, 884 regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, 885 regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, 886 regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, 887 regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, 888 regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, 889 regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, 890 regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, 891 regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, 892 regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, 893 regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, 894 regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, 895 regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, 896 regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, 897 regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, 898 regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, 899 regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, 900 regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, 901 regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, 902 regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, 903 regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, 904 regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, 905 regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, 906 regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, 907 regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, 908 regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, 909 regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, 910 regk_iop_sw_cfg_spu1 = 0x00000003, 911 regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, 912 regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, 913 regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, 914 regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, 915 regk_iop_sw_cfg_spu1_g0 = 0x0000000f, 916 regk_iop_sw_cfg_spu1_g1 = 0x0000000f, 917 regk_iop_sw_cfg_spu1_g2 = 0x0000000f, 918 regk_iop_sw_cfg_spu1_g3 = 0x0000000f, 919 regk_iop_sw_cfg_spu1_g4 = 0x0000000f, 920 regk_iop_sw_cfg_spu1_g5 = 0x0000000f, 921 regk_iop_sw_cfg_spu1_g6 = 0x0000000f, 922 regk_iop_sw_cfg_spu1_g7 = 0x0000000f, 923 regk_iop_sw_cfg_spu1_gio0 = 0x00000002, 924 regk_iop_sw_cfg_spu1_gio1 = 0x00000003, 925 regk_iop_sw_cfg_spu1_gio2 = 0x00000002, 926 regk_iop_sw_cfg_spu1_gio5 = 0x00000005, 927 regk_iop_sw_cfg_spu1_gio6 = 0x00000006, 928 regk_iop_sw_cfg_spu1_gio7 = 0x00000007, 929 regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, 930 regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, 931 regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, 932 regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, 933 regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, 934 regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, 935 regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, 936 regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, 937 regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, 938 regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, 939 regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, 940 regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, 941 regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, 942 regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, 943 regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, 944 regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, 945 regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, 946 regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, 947 regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, 948 regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, 949 regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, 950 regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, 951 regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, 952 regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, 953 regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, 954 regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, 955 regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, 956 regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, 957 regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, 958 regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, 959 regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, 960 regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, 961 regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, 962 regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, 963 regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, 964 regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, 965 regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, 966 regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, 967 regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, 968 regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, 969 regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, 970 regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, 971 regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, 972 regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, 973 regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, 974 regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, 975 regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, 976 regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, 977 regk_iop_sw_cfg_timer_grp0 = 0x00000000, 978 regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, 979 regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, 980 regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, 981 regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, 982 regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, 983 regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, 984 regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, 985 regk_iop_sw_cfg_timer_grp1 = 0x00000000, 986 regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, 987 regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, 988 regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, 989 regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, 990 regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, 991 regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, 992 regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, 993 regk_iop_sw_cfg_timer_grp2 = 0x00000000, 994 regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, 995 regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, 996 regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, 997 regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, 998 regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, 999 regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, 1000 regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, 1001 regk_iop_sw_cfg_timer_grp3 = 0x00000000, 1002 regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, 1003 regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, 1004 regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, 1005 regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, 1006 regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, 1007 regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, 1008 regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, 1009 regk_iop_sw_cfg_trig0_0 = 0x00000000, 1010 regk_iop_sw_cfg_trig0_1 = 0x00000000, 1011 regk_iop_sw_cfg_trig0_2 = 0x00000000, 1012 regk_iop_sw_cfg_trig0_3 = 0x00000000, 1013 regk_iop_sw_cfg_trig1_0 = 0x00000000, 1014 regk_iop_sw_cfg_trig1_1 = 0x00000000, 1015 regk_iop_sw_cfg_trig1_2 = 0x00000000, 1016 regk_iop_sw_cfg_trig1_3 = 0x00000000, 1017 regk_iop_sw_cfg_trig2_0 = 0x00000000, 1018 regk_iop_sw_cfg_trig2_1 = 0x00000000, 1019 regk_iop_sw_cfg_trig2_2 = 0x00000000, 1020 regk_iop_sw_cfg_trig2_3 = 0x00000000, 1021 regk_iop_sw_cfg_trig3_0 = 0x00000000, 1022 regk_iop_sw_cfg_trig3_1 = 0x00000000, 1023 regk_iop_sw_cfg_trig3_2 = 0x00000000, 1024 regk_iop_sw_cfg_trig3_3 = 0x00000000, 1025 regk_iop_sw_cfg_trig4_0 = 0x00000001, 1026 regk_iop_sw_cfg_trig4_1 = 0x00000001, 1027 regk_iop_sw_cfg_trig4_2 = 0x00000001, 1028 regk_iop_sw_cfg_trig4_3 = 0x00000001, 1029 regk_iop_sw_cfg_trig5_0 = 0x00000001, 1030 regk_iop_sw_cfg_trig5_1 = 0x00000001, 1031 regk_iop_sw_cfg_trig5_2 = 0x00000001, 1032 regk_iop_sw_cfg_trig5_3 = 0x00000001, 1033 regk_iop_sw_cfg_trig6_0 = 0x00000001, 1034 regk_iop_sw_cfg_trig6_1 = 0x00000001, 1035 regk_iop_sw_cfg_trig6_2 = 0x00000001, 1036 regk_iop_sw_cfg_trig6_3 = 0x00000001, 1037 regk_iop_sw_cfg_trig7_0 = 0x00000001, 1038 regk_iop_sw_cfg_trig7_1 = 0x00000001, 1039 regk_iop_sw_cfg_trig7_2 = 0x00000001, 1040 regk_iop_sw_cfg_trig7_3 = 0x00000001 1041}; 1042#endif /* __iop_sw_cfg_defs_h */ 1043