1#ifndef __iop_sw_cpu_defs_asm_h 2#define __iop_sw_cpu_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:10:19 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r 11 * id: $Id: iop_sw_cpu_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ 57#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 58#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 59#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 60#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 61#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 62#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 63#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 64#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 65#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 66#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 67#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 68#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 69#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 70#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 71 72/* Register rw_mc_data, scope iop_sw_cpu, type rw */ 73#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 74#define reg_iop_sw_cpu_rw_mc_data___val___width 32 75#define reg_iop_sw_cpu_rw_mc_data_offset 4 76 77/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ 78#define reg_iop_sw_cpu_rw_mc_addr_offset 8 79 80/* Register rs_mc_data, scope iop_sw_cpu, type rs */ 81#define reg_iop_sw_cpu_rs_mc_data_offset 12 82 83/* Register r_mc_data, scope iop_sw_cpu, type r */ 84#define reg_iop_sw_cpu_r_mc_data_offset 16 85 86/* Register r_mc_stat, scope iop_sw_cpu, type r */ 87#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 88#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 89#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 90#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 91#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 92#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 93#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 94#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 95#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 96#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 97#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 98#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 99#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 100#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 101#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 102#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 103#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 104#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 105#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 106#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 107#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 108#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 109#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 110#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 111#define reg_iop_sw_cpu_r_mc_stat_offset 20 112 113/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ 114#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 115#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 116#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 117#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 118#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 119#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 120#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 121#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 122#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 123 124/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ 125#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 126#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 127#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 128#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 129#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 130#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 131#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 132#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 133#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 134 135/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ 136#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 137#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 138#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 139#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 140#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 141#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 142#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 143#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 144#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 145#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 146#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 147#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 148#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 149 150/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ 151#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 152#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 153#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 154#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 155#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 156#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 157#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 158#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 159#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 160#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 161#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 162#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 163#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 164 165/* Register r_bus0_in, scope iop_sw_cpu, type r */ 166#define reg_iop_sw_cpu_r_bus0_in_offset 40 167 168/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ 169#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 170#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 171#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 172#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 173#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 174#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 175#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 176#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 177#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 178 179/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ 180#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 181#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 182#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 183#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 184#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 185#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 186#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 187#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 188#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 189 190/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ 191#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 192#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 193#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 194#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 195#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 196#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 197#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 198#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 199#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 200#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 201#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 202#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 203#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 204 205/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ 206#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 207#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 208#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 209#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 210#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 211#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 212#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 213#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 214#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 215#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 216#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 217#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 218#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 219 220/* Register r_bus1_in, scope iop_sw_cpu, type r */ 221#define reg_iop_sw_cpu_r_bus1_in_offset 60 222 223/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ 224#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 225#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 226#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 227 228/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ 229#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 230#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 231#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 232 233/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ 234#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 235#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 236#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 237 238/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ 239#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 240#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 241#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 242 243/* Register r_gio_in, scope iop_sw_cpu, type r */ 244#define reg_iop_sw_cpu_r_gio_in_offset 80 245 246/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ 247#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 248#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 249#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 250#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 251#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 252#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 253#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 254#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 255#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 256#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 257#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 258#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 259#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 260#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 261#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 262#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 263#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 264#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 265#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 266#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 267#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 268#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 269#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 270#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 271#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 272#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 273#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 274#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 275#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 276#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 277#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 278#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 279#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 280#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 281#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 282#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 283#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 284#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 285#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 286#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 287#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 288#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 289#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 290#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 291#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 292#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 293#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 294#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 295#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 296#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 297#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 298#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 299#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 300#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 301#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 302#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 303#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 304#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 305#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 306#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 307#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 308#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 309#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 310#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 311#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 312#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 313#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 314#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 315#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 316#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 317#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 318#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 319#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 320#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 321#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 322#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 323#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 324#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 325#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 326#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 327#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 328#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 329#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 330#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 331#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 332#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 333#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 334#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 335#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 336#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 337#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 338#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 339#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 340#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 341#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 342#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 343#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 344 345/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ 346#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 347#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 348#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 349#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 350#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 351#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 352#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 353#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 354#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 355#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 356#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 357#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 358#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 359#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 360#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 361#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 362#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 363#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 364#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 365#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 366#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 367#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 368#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 369#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 370#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 371#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 372#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 373#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 374#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 375#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 376#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 377#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 378#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 379#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 380#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 381#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 382#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 383#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 384#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 385#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 386#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 387#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 388#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 389#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 390#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 391#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 392#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 393#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 394#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 395#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 396#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 397#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 398#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 399#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 400#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 401#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 402#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 403#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 404#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 405#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 406#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 407#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 408#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 409#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 410#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 411#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 412#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 413#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 414#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 415#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 416#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 417#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 418#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 419#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 420#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 421#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 422#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 423#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 424#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 425#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 426#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 427#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 428#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 429#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 430#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 431#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 432#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 433#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 434#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 435#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 436#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 437#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 438#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 439#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 440#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 441#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 442#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 443 444/* Register r_intr0, scope iop_sw_cpu, type r */ 445#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 446#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 447#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 448#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 449#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 450#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 451#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 452#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 453#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 454#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 455#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 456#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 457#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 458#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 459#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 460#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 461#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 462#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 463#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 464#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 465#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 466#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 467#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 468#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 469#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 470#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 471#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 472#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 473#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 474#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 475#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 476#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 477#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 478#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 479#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 480#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 481#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 482#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 483#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 484#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 485#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 486#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 487#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 488#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 489#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 490#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 491#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 492#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 493#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 494#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 495#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 496#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 497#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 498#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 499#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 500#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 501#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 502#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 503#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 504#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 505#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 506#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 507#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 508#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 509#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 510#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 511#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 512#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 513#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 514#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 515#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 516#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 517#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 518#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 519#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 520#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 521#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 522#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 523#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 524#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 525#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 526#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 527#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 528#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 529#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 530#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 531#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 532#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 533#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 534#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 535#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 536#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 537#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 538#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 539#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 540#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 541#define reg_iop_sw_cpu_r_intr0_offset 92 542 543/* Register r_masked_intr0, scope iop_sw_cpu, type r */ 544#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 545#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 546#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 547#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 548#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 549#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 550#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 551#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 552#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 553#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 554#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 555#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 556#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 557#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 558#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 559#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 560#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 561#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 562#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 563#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 564#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 565#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 566#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 567#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 568#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 569#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 570#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 571#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 572#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 573#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 574#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 575#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 576#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 577#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 578#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 579#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 580#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 581#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 582#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 583#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 584#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 585#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 586#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 587#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 588#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 589#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 590#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 591#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 592#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 593#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 594#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 595#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 596#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 597#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 598#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 599#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 600#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 601#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 602#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 603#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 604#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 605#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 606#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 607#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 608#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 609#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 610#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 611#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 612#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 613#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 614#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 615#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 616#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 617#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 618#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 619#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 620#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 621#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 622#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 623#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 624#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 625#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 626#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 627#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 628#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 629#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 630#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 631#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 632#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 633#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 634#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 635#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 636#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 637#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 638#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 639#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 640#define reg_iop_sw_cpu_r_masked_intr0_offset 96 641 642/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ 643#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 644#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 645#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 646#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 647#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 648#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 649#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 650#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 651#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 652#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 653#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 654#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 655#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 656#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 657#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 658#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 659#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 660#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 661#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 662#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 663#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 664#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 665#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 666#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 667#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 668#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 669#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 670#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 671#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 672#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 673#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 674#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 675#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 676#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 677#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 678#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 679#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 680#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 681#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 682#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 683#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 684#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 685#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 686#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 687#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 688#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 689#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 690#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 691#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 692#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 693#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 694#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 695#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 696#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 697#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 698#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 699#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 700#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 701#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 702#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 703#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 704#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 705#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 706#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 707#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 708#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 709#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 710#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 711#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 712#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 713#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 714#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 715#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 716#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 717#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 718#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 719#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 720#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 721#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 722#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 723#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 724#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 725#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 726#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 727#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 728#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 729#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 730#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 731#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 732#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 733#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 734#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 735#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 736#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 737#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 738#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 739#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 740 741/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ 742#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 743#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 744#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 745#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 746#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 747#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 748#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 749#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 750#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 751#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 752#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 753#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 754#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 755#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 756#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 757#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 758#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 759#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 760#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 761#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 762#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 763#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 764#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 765#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 766#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 767#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 768#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 769#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 770#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 771#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 772#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 773#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 774#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 775#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 776#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 777#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 778#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 779#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 780#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 781#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 782#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 783#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 784#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 785#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 786#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 787#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 788#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 789#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 790#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 791#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 792#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 793#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 794#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 795#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 796#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 797#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 798#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 799#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 800#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 801#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 802#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 803#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 804#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 805#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 806#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 807#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 808#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 809#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 810#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 811#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 812#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 813#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 814#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 815#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 816#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 817#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 818#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 819#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 820#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 821#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 822#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 823#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 824#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 825#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 826#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 827#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 828#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 829#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 830#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 831#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 832#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 833#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 834#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 835#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 836#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 837#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 838#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 839 840/* Register r_intr1, scope iop_sw_cpu, type r */ 841#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 842#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 843#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 844#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 845#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 846#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 847#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 848#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 849#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 850#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 851#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 852#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 853#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 854#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 855#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 856#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 857#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 858#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 859#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 860#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 861#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 862#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 863#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 864#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 865#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 866#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 867#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 868#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 869#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 870#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 871#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 872#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 873#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 874#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 875#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 876#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 877#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 878#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 879#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 880#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 881#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 882#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 883#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 884#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 885#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 886#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 887#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 888#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 889#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 890#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 891#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 892#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 893#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 894#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 895#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 896#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 897#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 898#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 899#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 900#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 901#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 902#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 903#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 904#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 905#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 906#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 907#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 908#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 909#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 910#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 911#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 912#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 913#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 914#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 915#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 916#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 917#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 918#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 919#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 920#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 921#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 922#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 923#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 924#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 925#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 926#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 927#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 928#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 929#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 930#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 931#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 932#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 933#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 934#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 935#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 936#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 937#define reg_iop_sw_cpu_r_intr1_offset 108 938 939/* Register r_masked_intr1, scope iop_sw_cpu, type r */ 940#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 941#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 942#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 943#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 944#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 945#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 946#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 947#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 948#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 949#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 950#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 951#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 952#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 953#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 954#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 955#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 956#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 957#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 958#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 959#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 960#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 961#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 962#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 963#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 964#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 965#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 966#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 967#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 968#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 969#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 970#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 971#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 972#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 973#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 974#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 975#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 976#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 977#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 978#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 979#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 980#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 981#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 982#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 983#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 984#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 985#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 986#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 987#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 988#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 989#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 990#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 991#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 992#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 993#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 994#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 995#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 996#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 997#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 998#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 999#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 1000#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 1001#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 1002#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 1003#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 1004#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 1005#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 1006#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 1007#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 1008#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 1009#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 1010#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 1011#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 1012#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 1013#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 1014#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 1015#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 1016#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 1017#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 1018#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 1019#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 1020#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 1021#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 1022#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 1023#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 1024#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 1025#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 1026#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 1027#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 1028#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 1029#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 1030#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 1031#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 1032#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 1033#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 1034#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 1035#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 1036#define reg_iop_sw_cpu_r_masked_intr1_offset 112 1037 1038/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ 1039#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 1040#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 1041#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 1042#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 1043#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 1044#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 1045#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 1046#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 1047#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 1048#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 1049#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 1050#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 1051#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 1052#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 1053#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 1054#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 1055#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 1056#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 1057#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 1058#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 1059#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 1060#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 1061#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 1062#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 1063#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 1064#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 1065#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 1066#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 1067#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 1068#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 1069#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 1070#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 1071#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 1072#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 1073#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 1074#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 1075#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 1076#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 1077#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 1078#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 1079#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 1080#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 1081#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 1082#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 1083#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 1084#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 1085#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 1086#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 1087#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 1088#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 1089#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 1090#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 1091#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 1092#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 1093#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 1094#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 1095#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 1096#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 1097#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 1098#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 1099#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 1100#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 1101#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 1102#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 1103#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 1104#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 1105#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 1106#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 1107#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 1108#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 1109#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 1110#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 1111#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 1112#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 1113#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 1114#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 1115#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 1116#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 1117#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 1118#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 1119#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 1120#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 1121#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 1122#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 1123#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 1124#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 1125#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 1126#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 1127#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 1128#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 1129#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 1130#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 1131#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 1132#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 1133#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 1134#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 1135#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 1136 1137/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ 1138#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 1139#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 1140#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 1141#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 1142#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 1143#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 1144#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 1145#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 1146#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 1147#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 1148#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 1149#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 1150#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 1151#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 1152#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 1153#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 1154#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 1155#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 1156#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 1157#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 1158#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 1159#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 1160#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 1161#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 1162#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 1163#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 1164#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 1165#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 1166#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 1167#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 1168#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 1169#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 1170#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 1171#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 1172#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 1173#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 1174#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 1175#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 1176#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 1177#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 1178#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 1179#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 1180#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 1181#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 1182#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 1183#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 1184#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 1185#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 1186#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 1187 1188/* Register r_intr2, scope iop_sw_cpu, type r */ 1189#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 1190#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 1191#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 1192#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 1193#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 1194#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 1195#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 1196#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 1197#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 1198#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 1199#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 1200#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 1201#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 1202#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 1203#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 1204#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 1205#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 1206#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 1207#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 1208#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 1209#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 1210#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 1211#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 1212#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 1213#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 1214#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 1215#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 1216#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 1217#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 1218#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 1219#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 1220#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 1221#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 1222#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 1223#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 1224#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 1225#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 1226#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 1227#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 1228#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 1229#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 1230#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 1231#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 1232#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 1233#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 1234#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 1235#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 1236#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 1237#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 1238#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 1239#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 1240#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 1241#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 1242#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 1243#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 1244#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 1245#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 1246#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 1247#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 1248#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 1249#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 1250#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 1251#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 1252#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 1253#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 1254#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 1255#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 1256#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 1257#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 1258#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 1259#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 1260#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 1261#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 1262#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 1263#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 1264#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 1265#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 1266#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 1267#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 1268#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 1269#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 1270#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 1271#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 1272#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 1273#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 1274#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 1275#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 1276#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 1277#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 1278#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 1279#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 1280#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 1281#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 1282#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 1283#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 1284#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 1285#define reg_iop_sw_cpu_r_intr2_offset 124 1286 1287/* Register r_masked_intr2, scope iop_sw_cpu, type r */ 1288#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 1289#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 1290#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 1291#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 1292#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 1293#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 1294#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 1295#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 1296#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 1297#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 1298#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 1299#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 1300#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 1301#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 1302#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 1303#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 1304#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 1305#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 1306#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 1307#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 1308#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 1309#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 1310#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 1311#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 1312#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 1313#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 1314#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 1315#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 1316#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 1317#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 1318#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 1319#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 1320#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 1321#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 1322#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 1323#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 1324#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 1325#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 1326#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 1327#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 1328#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 1329#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 1330#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 1331#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 1332#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 1333#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 1334#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 1335#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 1336#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 1337#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 1338#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 1339#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 1340#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 1341#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 1342#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 1343#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 1344#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 1345#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 1346#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 1347#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 1348#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 1349#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 1350#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 1351#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 1352#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 1353#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 1354#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 1355#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 1356#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 1357#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 1358#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 1359#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 1360#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 1361#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 1362#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 1363#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 1364#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 1365#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 1366#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 1367#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 1368#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 1369#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 1370#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 1371#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 1372#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 1373#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 1374#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 1375#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 1376#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 1377#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 1378#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 1379#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 1380#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 1381#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 1382#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 1383#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 1384#define reg_iop_sw_cpu_r_masked_intr2_offset 128 1385 1386/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ 1387#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 1388#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 1389#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 1390#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 1391#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 1392#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 1393#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 1394#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 1395#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 1396#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 1397#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 1398#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 1399#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 1400#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 1401#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 1402#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 1403#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 1404#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 1405#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 1406#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 1407#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 1408#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 1409#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 1410#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 1411#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 1412#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 1413#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 1414#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 1415#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 1416#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 1417#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 1418#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 1419#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 1420#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 1421#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 1422#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 1423#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 1424#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 1425#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 1426#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 1427#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 1428#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 1429#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 1430#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 1431#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 1432#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 1433#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 1434#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 1435#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 1436#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 1437#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 1438#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 1439#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 1440#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 1441#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 1442#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 1443#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 1444#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 1445#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 1446#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 1447#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 1448#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 1449#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 1450#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 1451#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 1452#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 1453#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 1454#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 1455#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 1456#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 1457#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 1458#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 1459#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 1460#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 1461#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 1462#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 1463#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 1464#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 1465#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 1466#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 1467#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 1468#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 1469#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 1470#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 1471#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 1472#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 1473#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 1474#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 1475#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 1476#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 1477#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 1478#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 1479#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 1480#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 1481#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 1482#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 1483#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 1484 1485/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ 1486#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 1487#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 1488#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 1489#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 1490#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 1491#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 1492#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 1493#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 1494#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 1495#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 1496#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 1497#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 1498#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 1499#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 1500#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 1501#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 1502#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 1503#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 1504#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 1505#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 1506#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 1507#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 1508#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 1509#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 1510#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 1511#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 1512#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 1513#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 1514#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 1515#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 1516#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 1517#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 1518#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 1519#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 1520#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 1521#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 1522#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 1523#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 1524#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 1525#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 1526#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 1527#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 1528#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 1529#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 1530#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 1531#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 1532#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 1533#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 1534#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 1535 1536/* Register r_intr3, scope iop_sw_cpu, type r */ 1537#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 1538#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 1539#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 1540#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 1541#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 1542#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 1543#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 1544#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 1545#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 1546#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 1547#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 1548#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 1549#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 1550#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 1551#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 1552#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 1553#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 1554#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 1555#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 1556#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 1557#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 1558#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 1559#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 1560#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 1561#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 1562#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 1563#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 1564#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 1565#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 1566#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 1567#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 1568#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 1569#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 1570#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 1571#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 1572#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 1573#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 1574#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 1575#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 1576#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 1577#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 1578#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 1579#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 1580#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 1581#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 1582#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 1583#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 1584#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 1585#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 1586#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 1587#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 1588#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 1589#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 1590#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 1591#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 1592#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 1593#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 1594#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 1595#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 1596#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 1597#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 1598#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 1599#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 1600#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 1601#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 1602#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 1603#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 1604#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 1605#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 1606#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 1607#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 1608#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 1609#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 1610#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 1611#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 1612#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 1613#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 1614#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 1615#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 1616#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 1617#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 1618#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 1619#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 1620#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 1621#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 1622#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 1623#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 1624#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 1625#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 1626#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 1627#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 1628#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 1629#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 1630#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 1631#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 1632#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 1633#define reg_iop_sw_cpu_r_intr3_offset 140 1634 1635/* Register r_masked_intr3, scope iop_sw_cpu, type r */ 1636#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 1637#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 1638#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 1639#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 1640#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 1641#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 1642#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 1643#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 1644#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 1645#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 1646#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 1647#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 1648#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 1649#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 1650#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 1651#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 1652#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 1653#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 1654#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 1655#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 1656#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 1657#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 1658#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 1659#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 1660#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 1661#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 1662#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 1663#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 1664#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 1665#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 1666#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 1667#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 1668#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 1669#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 1670#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 1671#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 1672#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 1673#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 1674#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 1675#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 1676#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 1677#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 1678#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 1679#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 1680#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 1681#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 1682#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 1683#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 1684#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 1685#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 1686#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 1687#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 1688#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 1689#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 1690#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 1691#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 1692#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 1693#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 1694#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 1695#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 1696#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 1697#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 1698#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 1699#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 1700#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 1701#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 1702#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 1703#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 1704#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 1705#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 1706#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 1707#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 1708#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 1709#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 1710#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 1711#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 1712#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 1713#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 1714#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 1715#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 1716#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 1717#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 1718#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 1719#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 1720#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 1721#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 1722#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 1723#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 1724#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 1725#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 1726#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 1727#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 1728#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 1729#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 1730#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 1731#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 1732#define reg_iop_sw_cpu_r_masked_intr3_offset 144 1733 1734 1735/* Constants */ 1736#define regk_iop_sw_cpu_copy 0x00000000 1737#define regk_iop_sw_cpu_no 0x00000000 1738#define regk_iop_sw_cpu_rd 0x00000002 1739#define regk_iop_sw_cpu_reg_copy 0x00000001 1740#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 1741#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 1742#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 1743#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 1744#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 1745#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 1746#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 1747#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 1748#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 1749#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 1750#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 1751#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 1752#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 1753#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 1754#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 1755#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 1756#define regk_iop_sw_cpu_wr 0x00000003 1757#define regk_iop_sw_cpu_yes 0x00000001 1758#endif /* __iop_sw_cpu_defs_asm_h */ 1759