1#ifndef __config_defs_asm_h 2#define __config_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../rtl/config_regs.r 7 * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp 8 * last modfied: Thu Mar 4 12:34:39 2004 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r 11 * id: $Id: config_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register r_bootsel, scope config, type r */ 57#define reg_config_r_bootsel___boot_mode___lsb 0 58#define reg_config_r_bootsel___boot_mode___width 3 59#define reg_config_r_bootsel___full_duplex___lsb 3 60#define reg_config_r_bootsel___full_duplex___width 1 61#define reg_config_r_bootsel___full_duplex___bit 3 62#define reg_config_r_bootsel___user___lsb 4 63#define reg_config_r_bootsel___user___width 1 64#define reg_config_r_bootsel___user___bit 4 65#define reg_config_r_bootsel___pll___lsb 5 66#define reg_config_r_bootsel___pll___width 1 67#define reg_config_r_bootsel___pll___bit 5 68#define reg_config_r_bootsel___flash_bw___lsb 6 69#define reg_config_r_bootsel___flash_bw___width 1 70#define reg_config_r_bootsel___flash_bw___bit 6 71#define reg_config_r_bootsel_offset 0 72 73/* Register rw_clk_ctrl, scope config, type rw */ 74#define reg_config_rw_clk_ctrl___pll___lsb 0 75#define reg_config_rw_clk_ctrl___pll___width 1 76#define reg_config_rw_clk_ctrl___pll___bit 0 77#define reg_config_rw_clk_ctrl___cpu___lsb 1 78#define reg_config_rw_clk_ctrl___cpu___width 1 79#define reg_config_rw_clk_ctrl___cpu___bit 1 80#define reg_config_rw_clk_ctrl___iop___lsb 2 81#define reg_config_rw_clk_ctrl___iop___width 1 82#define reg_config_rw_clk_ctrl___iop___bit 2 83#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 84#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 85#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 86#define reg_config_rw_clk_ctrl___dma23___lsb 4 87#define reg_config_rw_clk_ctrl___dma23___width 1 88#define reg_config_rw_clk_ctrl___dma23___bit 4 89#define reg_config_rw_clk_ctrl___dma45___lsb 5 90#define reg_config_rw_clk_ctrl___dma45___width 1 91#define reg_config_rw_clk_ctrl___dma45___bit 5 92#define reg_config_rw_clk_ctrl___dma67___lsb 6 93#define reg_config_rw_clk_ctrl___dma67___width 1 94#define reg_config_rw_clk_ctrl___dma67___bit 6 95#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 96#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 97#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 98#define reg_config_rw_clk_ctrl___bif___lsb 8 99#define reg_config_rw_clk_ctrl___bif___width 1 100#define reg_config_rw_clk_ctrl___bif___bit 8 101#define reg_config_rw_clk_ctrl___fix_io___lsb 9 102#define reg_config_rw_clk_ctrl___fix_io___width 1 103#define reg_config_rw_clk_ctrl___fix_io___bit 9 104#define reg_config_rw_clk_ctrl_offset 4 105 106/* Register rw_pad_ctrl, scope config, type rw */ 107#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 108#define reg_config_rw_pad_ctrl___usb_susp___width 1 109#define reg_config_rw_pad_ctrl___usb_susp___bit 0 110#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 111#define reg_config_rw_pad_ctrl___phyrst_n___width 1 112#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 113#define reg_config_rw_pad_ctrl_offset 8 114 115 116/* Constants */ 117#define regk_config_bw16 0x00000000 118#define regk_config_bw32 0x00000001 119#define regk_config_master 0x00000005 120#define regk_config_nand 0x00000003 121#define regk_config_net_rx 0x00000001 122#define regk_config_net_tx_rx 0x00000002 123#define regk_config_no 0x00000000 124#define regk_config_none 0x00000007 125#define regk_config_nor 0x00000000 126#define regk_config_rw_clk_ctrl_default 0x00000002 127#define regk_config_rw_pad_ctrl_default 0x00000000 128#define regk_config_ser 0x00000004 129#define regk_config_slave 0x00000006 130#define regk_config_yes 0x00000001 131#endif /* __config_defs_asm_h */ 132