1#ifndef _ASM_ARCH_CRIS_DMA_H
2#define _ASM_ARCH_CRIS_DMA_H
3
4/* Defines for using and allocating dma channels. */
5
6#define MAX_DMA_CHANNELS	10
7
8#define NETWORK_ETH0_TX_DMA_NBR 0	/* Ethernet 0 out. */
9#define NETWORK_ETH0 RX_DMA_NBR 1	/* Ethernet 0 in. */
10
11#define IO_PROC_DMA0_TX_DMA_NBR 2	/* IO processor DMA0 out. */
12#define IO_PROC_DMA0_RX_DMA_NBR 3	/* IO processor DMA0 in. */
13
14#define ATA_TX_DMA_NBR 2		/* ATA interface out. */
15#define ATA_RX_DMA_NBR 3		/* ATA interface in. */
16
17#define ASYNC_SER2_TX_DMA_NBR 2		/* Asynchronous serial port 2 out. */
18#define ASYNC_SER2_RX_DMA_NBR 3		/* Asynchronous serial port 2 in. */
19
20#define IO_PROC_DMA1_TX_DMA_NBR 4	/* IO processor DMA1 out. */
21#define IO_PROC_DMA1_RX_DMA_NBR 5	/* IO processor DMA1 in. */
22
23#define ASYNC_SER1_TX_DMA_NBR 4		/* Asynchronous serial port 1 out. */
24#define ASYNC_SER1_RX_DMA_NBR 5		/* Asynchronous serial port 1 in. */
25
26#define SYNC_SER0_TX_DMA_NBR 4		/* Synchronous serial port 0 out. */
27#define SYNC_SER0_RX_DMA_NBR 5		/* Synchronous serial port 0 in. */
28
29#define EXTDMA0_TX_DMA_NBR 6		/* External DMA 0 out. */
30#define EXTDMA1_RX_DMA_NBR 7		/* External DMA 1 in. */
31
32#define ASYNC_SER0_TX_DMA_NBR 6		/* Asynchronous serial port 0 out. */
33#define ASYNC_SER0_RX_DMA_NBR 7		/* Asynchronous serial port 0 in. */
34
35#define SYNC_SER1_TX_DMA_NBR 6		/* Synchronous serial port 1 out. */
36#define SYNC_SER1_RX_DMA_NBR 7		/* Synchronous serial port 1 in. */
37
38#define NETWORK_ETH1_TX_DMA_NBR 6	/* Ethernet 1 out. */
39#define NETWORK_ETH1_RX_DMA_NBR 7	/* Ethernet 1 in. */
40
41#define EXTDMA2_TX_DMA_NBR 8		/* External DMA 2 out. */
42#define EXTDMA3_RX_DMA_NBR 9		/* External DMA 3 in. */
43
44#define STRCOP_TX_DMA_NBR 8		/* Stream co-processor out. */
45#define STRCOP_RX_DMA_NBR 9		/* Stream co-processor in. */
46
47#define ASYNC_SER3_TX_DMA_NBR 8		/* Asynchronous serial port 3 out. */
48#define ASYNC_SER3_RX_DMA_NBR 9		/* Asynchronous serial port 3 in. */
49
50enum dma_owner
51{
52  dma_eth0,
53  dma_eth1,
54  dma_iop0,
55  dma_iop1,
56  dma_ser0,
57  dma_ser1,
58  dma_ser2,
59  dma_ser3,
60  dma_sser0,
61  dma_sser1,
62  dma_ata,
63  dma_strp,
64  dma_ext0,
65  dma_ext1,
66  dma_ext2,
67  dma_ext3
68};
69
70int crisv32_request_dma(unsigned int dmanr, const char * device_id,
71                        unsigned options, unsigned bandwidth, enum dma_owner owner);
72void crisv32_free_dma(unsigned int dmanr);
73
74/* Masks used by crisv32_request_dma options: */
75#define DMA_VERBOSE_ON_ERROR 1
76#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
77#define DMA_INT_MEM 4
78
79#endif /* _ASM_ARCH_CRIS_DMA_H */
80