1 2/* 3 * File: include/asm-blackfin/mach-bf561/anomaly.h 4 * Based on: 5 * Author: 6 * 7 * Created: 8 * Description: 9 * 10 * Rev: 11 * 12 * Modified: 13 * 14 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2, or (at your option) 19 * any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; see the file COPYING. 28 * If not, write to the Free Software Foundation, 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32/* This file shoule be up to date with: 33 * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List 34 */ 35 36#ifndef _MACH_ANOMALY_H_ 37#define _MACH_ANOMALY_H_ 38 39/* We do not support 0.1 or 0.4 silicon - sorry */ 40#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || \ 41 defined(CONFIG_BF_REV_0_4)) 42#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 43#endif 44 45/* Issues that are common to 0.5 and 0.3 silicon */ 46#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) 47#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 48 slot1 and store of a P register in slot 2 is not 49 supported */ 50#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not 51 updated at the same time. */ 52#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned 53 memory locations */ 54#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR 55 registers */ 56#define ANOMALY_05000127 /* Signbits instruction not functional under certain 57 conditions */ 58#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ 59#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out 60 upper bits */ 61#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ 62#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame 63 syncs */ 64#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz 65 and higher devices */ 66#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ 67#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ 68#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not 69 functional */ 70#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the 71 shadow of a conditional branch */ 72#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop 73 may cause bad instruction fetches */ 74#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 75 external SPORT TX and RX clocks */ 76#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ 77#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal 78 voltage regulator (VDDint) to increase */ 79#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal 80 voltage regulator (VDDint) to decrease */ 81#define ANOMALY_05000272 /* Certain data cache write through modes fail for 82 VDDint <=0.9V */ 83#define ANOMALY_05000274 /* Data cache write back to external synchronous memory 84 may be lost */ 85#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ 86#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC 87 registers are interrupted */ 88 89#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ 90 91#if defined(CONFIG_BF_REV_0_5) 92#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT 93 mode with external clock */ 94#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to 95 using IMDMA */ 96#endif 97 98#if defined(CONFIG_BF_REV_0_3) 99#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) 100 Mode with 0 Frame Syncs */ 101#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ 102#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through 103 cache data writes */ 104#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ 105#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ 106#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ 107#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an 108 accumulator saturation */ 109#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General 110 Purpose TX or RX modes */ 111#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration 112 registers */ 113#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with 114 External Frame Syncs */ 115#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ 116#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits 117 (not a meaningful mode) */ 118#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer 119 Placement in Memory */ 120#define ANOMALY_05000189 /* False Protection Exception */ 121#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs 122 when polarity setting is changed */ 123#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data 124 corruption */ 125#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding 126 memory read */ 127#define ANOMALY_05000199 /* DMA current address shows wrong value during carry 128 fix */ 129#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during 130 inactive channels in certain conditions */ 131#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG 132 situation */ 133#define ANOMALY_05000204 /* Incorrect data read with write-through cache and 134 allocate cache lines on reads only mode */ 135#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA 136 stopping */ 137#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ 138#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain 139 instructions */ 140#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ 141#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable 142 state */ 143#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and 144 Non-Cached On-Chip L2 Memory */ 145#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ 146#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect 147 data */ 148#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate 149 Differences in certain Conditions */ 150#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ 151#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in 152 multichannel mode */ 153#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to 154 hardware reset */ 155#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of 156 Control causes failures */ 157#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ 158#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel 159 (TDM) mode in certain conditions */ 160#define ANOMALY_05000251 /* Exception not generated for MMR accesses in 161 reserved region */ 162#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ 163#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 164 of the ICPLB Data registers differ */ 165#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ 166#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ 167#define ANOMALY_05000262 /* Stores to data cache may be lost */ 168#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB 169 exception */ 170#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second 171 to last instruction in hardware loop */ 172#define ANOMALY_05000276 /* Timing requirements change for External Frame 173 Sync PPI Modes with non-zero PPI_DELAY */ 174#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause 175 DMA system instability */ 176#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is 177 not restored */ 178#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed 179 in a particular stage */ 180#define ANOMALY_05000287 /* A read will receive incorrect data under certain 181 conditions */ 182#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ 183#endif 184 185#endif /* _MACH_ANOMALY_H_ */ 186