1/* 2 * Copyright (C) 2004-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8#ifndef __ASM_AVR32_PTRACE_H 9#define __ASM_AVR32_PTRACE_H 10 11#define PTRACE_GETREGS 12 12#define PTRACE_SETREGS 13 13 14/* 15 * Status Register bits 16 */ 17#define SR_H 0x40000000 18#define SR_R 0x20000000 19#define SR_J 0x10000000 20#define SR_DM 0x08000000 21#define SR_D 0x04000000 22#define MODE_NMI 0x01c00000 23#define MODE_EXCEPTION 0x01800000 24#define MODE_INT3 0x01400000 25#define MODE_INT2 0x01000000 26#define MODE_INT1 0x00c00000 27#define MODE_INT0 0x00800000 28#define MODE_SUPERVISOR 0x00400000 29#define MODE_USER 0x00000000 30#define MODE_MASK 0x01c00000 31#define SR_EM 0x00200000 32#define SR_I3M 0x00100000 33#define SR_I2M 0x00080000 34#define SR_I1M 0x00040000 35#define SR_I0M 0x00020000 36#define SR_GM 0x00010000 37 38#define SR_H_BIT 30 39#define SR_R_BIT 29 40#define SR_J_BIT 28 41#define SR_DM_BIT 27 42#define SR_D_BIT 26 43#define MODE_SHIFT 22 44#define SR_EM_BIT 21 45#define SR_I3M_BIT 20 46#define SR_I2M_BIT 19 47#define SR_I1M_BIT 18 48#define SR_I0M_BIT 17 49#define SR_GM_BIT 16 50 51/* The user-visible part */ 52#define SR_L 0x00000020 53#define SR_Q 0x00000010 54#define SR_V 0x00000008 55#define SR_N 0x00000004 56#define SR_Z 0x00000002 57#define SR_C 0x00000001 58 59#define SR_L_BIT 5 60#define SR_Q_BIT 4 61#define SR_V_BIT 3 62#define SR_N_BIT 2 63#define SR_Z_BIT 1 64#define SR_C_BIT 0 65 66/* 67 * The order is defined by the stmts instruction. r0 is stored first, 68 * so it gets the highest address. 69 * 70 * Registers 0-12 are general-purpose registers (r12 is normally used for 71 * the function return value). 72 * Register 13 is the stack pointer 73 * Register 14 is the link register 74 * Register 15 is the program counter (retrieved from the RAR sysreg) 75 */ 76#define FRAME_SIZE_FULL 72 77#define REG_R12_ORIG 68 78#define REG_R0 64 79#define REG_R1 60 80#define REG_R2 56 81#define REG_R3 52 82#define REG_R4 48 83#define REG_R5 44 84#define REG_R6 40 85#define REG_R7 36 86#define REG_R8 32 87#define REG_R9 28 88#define REG_R10 24 89#define REG_R11 20 90#define REG_R12 16 91#define REG_SP 12 92#define REG_LR 8 93 94#define FRAME_SIZE_MIN 8 95#define REG_PC 4 96#define REG_SR 0 97 98#ifndef __ASSEMBLY__ 99struct pt_regs { 100 /* These are always saved */ 101 unsigned long sr; 102 unsigned long pc; 103 104 /* These are sometimes saved */ 105 unsigned long lr; 106 unsigned long sp; 107 unsigned long r12; 108 unsigned long r11; 109 unsigned long r10; 110 unsigned long r9; 111 unsigned long r8; 112 unsigned long r7; 113 unsigned long r6; 114 unsigned long r5; 115 unsigned long r4; 116 unsigned long r3; 117 unsigned long r2; 118 unsigned long r1; 119 unsigned long r0; 120 121 /* Only saved on system call */ 122 unsigned long r12_orig; 123}; 124 125#ifdef __KERNEL__ 126# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) 127extern void show_regs (struct pt_regs *); 128 129static __inline__ int valid_user_regs(struct pt_regs *regs) 130{ 131 /* 132 * Some of the Java bits might be acceptable if/when we 133 * implement some support for that stuff... 134 */ 135 if ((regs->sr & 0xffff0000) == 0) 136 return 1; 137 138 /* 139 * Force status register flags to be sane and report this 140 * illegal behaviour... 141 */ 142 regs->sr &= 0x0000ffff; 143 return 0; 144} 145 146#define instruction_pointer(regs) ((regs)->pc) 147 148#define profile_pc(regs) instruction_pointer(regs) 149 150#endif /* __KERNEL__ */ 151 152#endif /* ! __ASSEMBLY__ */ 153 154#endif /* __ASM_AVR32_PTRACE_H */ 155