1/* linux/include/asm-arm/arch-s3c2410/regs-spi.h 2 * 3 * Copyright (c) 2004 Fetron GmbH 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * S3C2410 SPI register definition 10*/ 11 12#ifndef __ASM_ARCH_REGS_SPI_H 13#define __ASM_ARCH_REGS_SPI_H 14 15#define S3C2410_SPI1 (0x20) 16#define S3C2412_SPI1 (0x100) 17 18#define S3C2410_SPCON (0x00) 19 20#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ 21#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ 22#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ 23#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ 24#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select 25 0: slave, 1: master */ 26#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ 27#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ 28 29#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ 30#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ 31 32#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ 33 34 35#define S3C2410_SPSTA (0x04) 36 37#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ 38#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ 39#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ 40 41 42#define S3C2410_SPPIN (0x08) 43 44#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ 45#define S3C2410_SPPIN_RESERVED (1<<1) 46#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ 47#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ 48 49 50#define S3C2410_SPPRE (0x0C) 51#define S3C2410_SPTDAT (0x10) 52#define S3C2410_SPRDAT (0x14) 53 54#endif /* __ASM_ARCH_REGS_SPI_H */ 55