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  • only in /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-s3c2410/
1/* linux/include/asm-arm/arch-s3c2410/map.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 *	Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H
15
16/* we have a bit of a tight squeeze to fit all our registers from
17 * 0xF00000000 upwards, since we use all of the nGCS space in some
18 * capacity, and also need to fit the S3C2410 registers in as well...
19 *
20 * we try to ensure stuff like the IRQ registers are available for
21 * an single MOVS instruction (ie, only 8 bits of set data)
22 *
23 * Note, we are trying to remove some of these from the implementation
24 * as they are only useful to certain drivers...
25 */
26
27#ifndef __ASSEMBLY__
28#define S3C2410_ADDR(x)	  ((void __iomem __force *)0xF0000000 + (x))
29#else
30#define S3C2410_ADDR(x)	  (0xF0000000 + (x))
31#endif
32
33#define S3C2400_ADDR(x)	  S3C2410_ADDR(x)
34
35/* interrupt controller is the first thing we put in, to make
36 * the assembly code for the irq detection easier
37 */
38#define S3C24XX_VA_IRQ	   S3C2410_ADDR(0x00000000)
39#define S3C2400_PA_IRQ	   (0x14400000)
40#define S3C2410_PA_IRQ	   (0x4A000000)
41#define S3C24XX_SZ_IRQ	   SZ_1M
42
43/* memory controller registers */
44#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
45#define S3C2400_PA_MEMCTRL (0x14000000)
46#define S3C2410_PA_MEMCTRL (0x48000000)
47#define S3C24XX_SZ_MEMCTRL SZ_1M
48
49/* USB host controller */
50#define S3C2400_PA_USBHOST (0x14200000)
51#define S3C2410_PA_USBHOST (0x49000000)
52#define S3C24XX_SZ_USBHOST SZ_1M
53
54/* DMA controller */
55#define S3C2400_PA_DMA	   (0x14600000)
56#define S3C2410_PA_DMA	   (0x4B000000)
57#define S3C24XX_SZ_DMA	   SZ_1M
58
59/* Clock and Power management */
60#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
61#define S3C2400_PA_CLKPWR  (0x14800000)
62#define S3C2410_PA_CLKPWR  (0x4C000000)
63#define S3C24XX_SZ_CLKPWR  SZ_1M
64
65/* LCD controller */
66#define S3C24XX_VA_LCD	   S3C2410_ADDR(0x00300000)
67#define S3C2400_PA_LCD	   (0x14A00000)
68#define S3C2410_PA_LCD	   (0x4D000000)
69#define S3C24XX_SZ_LCD	   SZ_1M
70
71/* NAND flash controller */
72#define S3C2410_PA_NAND	   (0x4E000000)
73#define S3C24XX_SZ_NAND	   SZ_1M
74
75/* MMC controller - available on the S3C2400 */
76#define S3C2400_PA_MMC 	   (0x15A00000)
77#define S3C2400_SZ_MMC 	   SZ_1M
78
79/* UARTs */
80#define S3C24XX_VA_UART	   S3C2410_ADDR(0x00400000)
81#define S3C2400_PA_UART	   (0x15000000)
82#define S3C2410_PA_UART	   (0x50000000)
83#define S3C24XX_SZ_UART	   SZ_1M
84
85/* Timers */
86#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
87#define S3C2400_PA_TIMER   (0x15100000)
88#define S3C2410_PA_TIMER   (0x51000000)
89#define S3C24XX_SZ_TIMER   SZ_1M
90
91/* USB Device port */
92#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
93#define S3C2400_PA_USBDEV  (0x15200140)
94#define S3C2410_PA_USBDEV  (0x52000000)
95#define S3C24XX_SZ_USBDEV  SZ_1M
96
97/* Watchdog */
98#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
99#define S3C2400_PA_WATCHDOG (0x15300000)
100#define S3C2410_PA_WATCHDOG (0x53000000)
101#define S3C24XX_SZ_WATCHDOG SZ_1M
102
103/* IIC hardware controller */
104#define S3C2400_PA_IIC	   (0x15400000)
105#define S3C2410_PA_IIC	   (0x54000000)
106#define S3C24XX_SZ_IIC	   SZ_1M
107
108/* IIS controller */
109#define S3C2400_PA_IIS	   (0x15508000)
110#define S3C2410_PA_IIS	   (0x55000000)
111#define S3C24XX_SZ_IIS	   SZ_1M
112
113/* GPIO ports */
114
115/* the calculation for the VA of this must ensure that
116 * it is the same distance apart from the UART in the
117 * phsyical address space, as the initial mapping for the IO
118 * is done as a 1:1 maping. This puts it (currently) at
119 * 0xF6800000, which is not in the way of any current mapping
120 * by the base system.
121*/
122
123#define S3C2400_PA_GPIO	   (0x15600000)
124#define S3C2410_PA_GPIO	   (0x56000000)
125#define S3C24XX_VA_GPIO	   ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
126#define S3C24XX_SZ_GPIO	   SZ_1M
127
128/* RTC */
129#define S3C2400_PA_RTC	   (0x15700040)
130#define S3C2410_PA_RTC	   (0x57000000)
131#define S3C24XX_SZ_RTC	   SZ_1M
132
133/* ADC */
134#define S3C2400_PA_ADC	   (0x15800000)
135#define S3C2410_PA_ADC	   (0x58000000)
136#define S3C24XX_SZ_ADC	   SZ_1M
137
138/* SPI */
139#define S3C2400_PA_SPI	   (0x15900000)
140#define S3C2410_PA_SPI	   (0x59000000)
141#define S3C24XX_SZ_SPI	   SZ_1M
142
143/* SDI */
144#define S3C2410_PA_SDI	   (0x5A000000)
145#define S3C24XX_SZ_SDI	   SZ_1M
146
147/* CAMIF */
148#define S3C2440_PA_CAMIF   (0x4F000000)
149#define S3C2440_SZ_CAMIF   SZ_1M
150
151/* AC97 */
152
153#define S3C2440_PA_AC97	   (0x5B000000)
154#define S3C2440_SZ_AC97	   SZ_1M
155
156/* S3C2443 High-speed SD/MMC */
157#define S3C2443_PA_HSMMC   (0x4A800000)
158#define S3C2443_SZ_HSMMC   (256)
159
160/* ISA style IO, for each machine to sort out mappings for, if it
161 * implements it. We reserve two 16M regions for ISA.
162 */
163
164#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
165#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
166
167/* physical addresses of all the chip-select areas */
168
169#define S3C2410_CS0 (0x00000000)
170#define S3C2410_CS1 (0x08000000)
171#define S3C2410_CS2 (0x10000000)
172#define S3C2410_CS3 (0x18000000)
173#define S3C2410_CS4 (0x20000000)
174#define S3C2410_CS5 (0x28000000)
175#define S3C2410_CS6 (0x30000000)
176#define S3C2410_CS7 (0x38000000)
177
178#define S3C2410_SDRAM_PA    (S3C2410_CS6)
179
180#define S3C2400_CS0 (0x00000000)
181#define S3C2400_CS1 (0x02000000)
182#define S3C2400_CS2 (0x04000000)
183#define S3C2400_CS3 (0x06000000)
184#define S3C2400_CS4 (0x08000000)
185#define S3C2400_CS5 (0x0A000000)
186#define S3C2400_CS6 (0x0C000000)
187#define S3C2400_CS7 (0x0E000000)
188
189#define S3C2400_SDRAM_PA    (S3C2400_CS6)
190
191/* Use a single interface for common resources between S3C24XX cpus */
192
193#ifdef CONFIG_CPU_S3C2400
194#define S3C24XX_PA_IRQ      S3C2400_PA_IRQ
195#define S3C24XX_PA_MEMCTRL  S3C2400_PA_MEMCTRL
196#define S3C24XX_PA_USBHOST  S3C2400_PA_USBHOST
197#define S3C24XX_PA_DMA      S3C2400_PA_DMA
198#define S3C24XX_PA_CLKPWR   S3C2400_PA_CLKPWR
199#define S3C24XX_PA_LCD      S3C2400_PA_LCD
200#define S3C24XX_PA_UART     S3C2400_PA_UART
201#define S3C24XX_PA_TIMER    S3C2400_PA_TIMER
202#define S3C24XX_PA_USBDEV   S3C2400_PA_USBDEV
203#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
204#define S3C24XX_PA_IIC      S3C2400_PA_IIC
205#define S3C24XX_PA_IIS      S3C2400_PA_IIS
206#define S3C24XX_PA_GPIO     S3C2400_PA_GPIO
207#define S3C24XX_PA_RTC      S3C2400_PA_RTC
208#define S3C24XX_PA_ADC      S3C2400_PA_ADC
209#define S3C24XX_PA_SPI      S3C2400_PA_SPI
210#else
211#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
212#define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
213#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
214#define S3C24XX_PA_DMA      S3C2410_PA_DMA
215#define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
216#define S3C24XX_PA_LCD      S3C2410_PA_LCD
217#define S3C24XX_PA_UART     S3C2410_PA_UART
218#define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
219#define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
220#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
221#define S3C24XX_PA_IIC      S3C2410_PA_IIC
222#define S3C24XX_PA_IIS      S3C2410_PA_IIS
223#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
224#define S3C24XX_PA_RTC      S3C2410_PA_RTC
225#define S3C24XX_PA_ADC      S3C2410_PA_ADC
226#define S3C24XX_PA_SPI      S3C2410_PA_SPI
227#endif
228
229/* deal with the registers that move under the 2412/2413 */
230
231#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
232#ifndef __ASSEMBLY__
233extern void __iomem *s3c24xx_va_gpio2;
234#endif
235#ifdef CONFIG_CPU_S3C2412_ONLY
236#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
237#else
238#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
239#endif
240#else
241#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
242#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
243#endif
244
245#endif /* __ASM_ARCH_MAP_H */
246