1/* 2 * include/asm-arm/arch-pnx4008/timex.h 3 * 4 * PNX4008 timers header file 5 * 6 * Author: Dmitry Chigirev <source@mvista.com> 7 * 8 * 2005 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 */ 13 14#ifndef __PNX4008_TIMEX_H 15#define __PNX4008_TIMEX_H 16 17#include <asm/hardware.h> 18#include <asm/io.h> 19 20#define CLOCK_TICK_RATE 1000000 21 22#define TICKS2USECS(x) (x) 23 24/* MilliSecond Timer - Chapter 21 Page 202 */ 25 26#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0)) 27#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4)) 28#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8)) 29#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14)) 30#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18)) 31#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c)) 32 33/* High Speed Timer - Chpater 22, Page 205 */ 34 35#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0)) 36#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4)) 37#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8)) 38#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC)) 39#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10)) 40#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14)) 41#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18)) 42#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c)) 43#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20)) 44#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28)) 45#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C)) 46#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30)) 47 48/* IMPORTANT: both timers are UPCOUNTING */ 49 50/* xSTIM_MCTRL bit definitions */ 51#define MR0_INT 1 52#define RESET_COUNT0 (1<<1) 53#define STOP_COUNT0 (1<<2) 54#define MR1_INT (1<<3) 55#define RESET_COUNT1 (1<<4) 56#define STOP_COUNT1 (1<<5) 57#define MR2_INT (1<<6) 58#define RESET_COUNT2 (1<<7) 59#define STOP_COUNT2 (1<<8) 60 61/* xSTIM_CTRL bit definitions */ 62#define COUNT_ENAB 1 63#define RESET_COUNT (1<<1) 64#define DEBUG_EN (1<<2) 65 66/* xSTIM_INT bit definitions */ 67#define MATCH0_INT 1 68#define MATCH1_INT (1<<1) 69#define MATCH2_INT (1<<2) 70#define RTC_TICK0 (1<<4) 71#define RTC_TICK1 (1<<5) 72 73#endif 74