1/* 2 * linux/include/asm-arm/arch-omap/irqs.h 3 * 4 * Copyright (C) Greg Lonnon 2001 5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 22 * are different. 23 */ 24 25#ifndef __ASM_ARCH_OMAP15XX_IRQS_H 26#define __ASM_ARCH_OMAP15XX_IRQS_H 27 28/* 29 * IRQ numbers for interrupt handler 1 30 * 31 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 32 * 33 */ 34#define INT_CAMERA 1 35#define INT_FIQ 3 36#define INT_RTDX 6 37#define INT_DSP_MMU_ABORT 7 38#define INT_HOST 8 39#define INT_ABORT 9 40#define INT_BRIDGE_PRIV 13 41#define INT_GPIO_BANK1 14 42#define INT_UART3 15 43#define INT_TIMER3 16 44#define INT_DMA_CH0_6 19 45#define INT_DMA_CH1_7 20 46#define INT_DMA_CH2_8 21 47#define INT_DMA_CH3 22 48#define INT_DMA_CH4 23 49#define INT_DMA_CH5 24 50#define INT_DMA_LCD 25 51#define INT_TIMER1 26 52#define INT_WD_TIMER 27 53#define INT_BRIDGE_PUB 28 54#define INT_TIMER2 30 55#define INT_LCD_CTRL 31 56 57/* 58 * OMAP-1510 specific IRQ numbers for interrupt handler 1 59 */ 60#define INT_1510_IH2_IRQ 0 61#define INT_1510_RES2 2 62#define INT_1510_SPI_TX 4 63#define INT_1510_SPI_RX 5 64#define INT_1510_DSP_MAILBOX1 10 65#define INT_1510_DSP_MAILBOX2 11 66#define INT_1510_RES12 12 67#define INT_1510_LB_MMU 17 68#define INT_1510_RES18 18 69#define INT_1510_LOCAL_BUS 29 70 71/* 72 * OMAP-1610 specific IRQ numbers for interrupt handler 1 73 */ 74#define INT_1610_IH2_IRQ 0 75#define INT_1610_IH2_FIQ 2 76#define INT_1610_McBSP2_TX 4 77#define INT_1610_McBSP2_RX 5 78#define INT_1610_DSP_MAILBOX1 10 79#define INT_1610_DSP_MAILBOX2 11 80#define INT_1610_LCD_LINE 12 81#define INT_1610_GPTIMER1 17 82#define INT_1610_GPTIMER2 18 83#define INT_1610_SSR_FIFO_0 29 84 85/* 86 * OMAP-730 specific IRQ numbers for interrupt handler 1 87 */ 88#define INT_730_IH2_FIQ 0 89#define INT_730_IH2_IRQ 1 90#define INT_730_USB_NON_ISO 2 91#define INT_730_USB_ISO 3 92#define INT_730_ICR 4 93#define INT_730_EAC 5 94#define INT_730_GPIO_BANK1 6 95#define INT_730_GPIO_BANK2 7 96#define INT_730_GPIO_BANK3 8 97#define INT_730_McBSP2TX 10 98#define INT_730_McBSP2RX 11 99#define INT_730_McBSP2RX_OVF 12 100#define INT_730_LCD_LINE 14 101#define INT_730_GSM_PROTECT 15 102#define INT_730_TIMER3 16 103#define INT_730_GPIO_BANK5 17 104#define INT_730_GPIO_BANK6 18 105#define INT_730_SPGIO_WR 29 106 107/* 108 * IRQ numbers for interrupt handler 2 109 * 110 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 111 */ 112#define IH2_BASE 32 113 114#define INT_KEYBOARD (1 + IH2_BASE) 115#define INT_uWireTX (2 + IH2_BASE) 116#define INT_uWireRX (3 + IH2_BASE) 117#define INT_I2C (4 + IH2_BASE) 118#define INT_MPUIO (5 + IH2_BASE) 119#define INT_USB_HHC_1 (6 + IH2_BASE) 120#define INT_McBSP3TX (10 + IH2_BASE) 121#define INT_McBSP3RX (11 + IH2_BASE) 122#define INT_McBSP1TX (12 + IH2_BASE) 123#define INT_McBSP1RX (13 + IH2_BASE) 124#define INT_UART1 (14 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE) 128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_MMC (23 + IH2_BASE) 132#define INT_GAUGE_32K (24 + IH2_BASE) 133#define INT_RTC_TIMER (25 + IH2_BASE) 134#define INT_RTC_ALARM (26 + IH2_BASE) 135#define INT_MEM_STICK (27 + IH2_BASE) 136 137/* 138 * OMAP-1510 specific IRQ numbers for interrupt handler 2 139 */ 140#define INT_1510_DSP_MMU (28 + IH2_BASE) 141#define INT_1510_COM_SPI_RO (31 + IH2_BASE) 142 143/* 144 * OMAP-1610 specific IRQ numbers for interrupt handler 2 145 */ 146#define INT_1610_FAC (0 + IH2_BASE) 147#define INT_1610_USB_HHC_2 (7 + IH2_BASE) 148#define INT_1610_USB_OTG (8 + IH2_BASE) 149#define INT_1610_SoSSI (9 + IH2_BASE) 150#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) 151#define INT_1610_DSP_MMU (28 + IH2_BASE) 152#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) 153#define INT_1610_STI (32 + IH2_BASE) 154#define INT_1610_STI_WAKEUP (33 + IH2_BASE) 155#define INT_1610_GPTIMER3 (34 + IH2_BASE) 156#define INT_1610_GPTIMER4 (35 + IH2_BASE) 157#define INT_1610_GPTIMER5 (36 + IH2_BASE) 158#define INT_1610_GPTIMER6 (37 + IH2_BASE) 159#define INT_1610_GPTIMER7 (38 + IH2_BASE) 160#define INT_1610_GPTIMER8 (39 + IH2_BASE) 161#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) 162#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) 163#define INT_1610_MMC2 (42 + IH2_BASE) 164#define INT_1610_CF (43 + IH2_BASE) 165#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) 166#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) 167#define INT_1610_SPI (49 + IH2_BASE) 168#define INT_1610_DMA_CH6 (53 + IH2_BASE) 169#define INT_1610_DMA_CH7 (54 + IH2_BASE) 170#define INT_1610_DMA_CH8 (55 + IH2_BASE) 171#define INT_1610_DMA_CH9 (56 + IH2_BASE) 172#define INT_1610_DMA_CH10 (57 + IH2_BASE) 173#define INT_1610_DMA_CH11 (58 + IH2_BASE) 174#define INT_1610_DMA_CH12 (59 + IH2_BASE) 175#define INT_1610_DMA_CH13 (60 + IH2_BASE) 176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_NAND (63 + IH2_BASE) 179 180/* 181 * OMAP-730 specific IRQ numbers for interrupt handler 2 182 */ 183#define INT_730_HW_ERRORS (0 + IH2_BASE) 184#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) 185#define INT_730_CFCD (2 + IH2_BASE) 186#define INT_730_CFIREQ (3 + IH2_BASE) 187#define INT_730_I2C (4 + IH2_BASE) 188#define INT_730_PCC (5 + IH2_BASE) 189#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) 190#define INT_730_SPI_100K_1 (7 + IH2_BASE) 191#define INT_730_SYREN_SPI (8 + IH2_BASE) 192#define INT_730_VLYNQ (9 + IH2_BASE) 193#define INT_730_GPIO_BANK4 (10 + IH2_BASE) 194#define INT_730_McBSP1TX (11 + IH2_BASE) 195#define INT_730_McBSP1RX (12 + IH2_BASE) 196#define INT_730_McBSP1RX_OF (13 + IH2_BASE) 197#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) 198#define INT_730_UART_MODEM_1 (15 + IH2_BASE) 199#define INT_730_MCSI (16 + IH2_BASE) 200#define INT_730_uWireTX (17 + IH2_BASE) 201#define INT_730_uWireRX (18 + IH2_BASE) 202#define INT_730_SMC_CD (19 + IH2_BASE) 203#define INT_730_SMC_IREQ (20 + IH2_BASE) 204#define INT_730_HDQ_1WIRE (21 + IH2_BASE) 205#define INT_730_TIMER32K (22 + IH2_BASE) 206#define INT_730_MMC_SDIO (23 + IH2_BASE) 207#define INT_730_UPLD (24 + IH2_BASE) 208#define INT_730_USB_HHC_1 (27 + IH2_BASE) 209#define INT_730_USB_HHC_2 (28 + IH2_BASE) 210#define INT_730_USB_GENI (29 + IH2_BASE) 211#define INT_730_USB_OTG (30 + IH2_BASE) 212#define INT_730_CAMERA_IF (31 + IH2_BASE) 213#define INT_730_RNG (32 + IH2_BASE) 214#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) 215#define INT_730_DBB_RF_EN (34 + IH2_BASE) 216#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) 217#define INT_730_SHA1_MD5 (36 + IH2_BASE) 218#define INT_730_SPI_100K_2 (37 + IH2_BASE) 219#define INT_730_RNG_IDLE (38 + IH2_BASE) 220#define INT_730_MPUIO (39 + IH2_BASE) 221#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 222#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) 223#define INT_730_LLPC_OE_RISING (42 + IH2_BASE) 224#define INT_730_LLPC_VSYNC (43 + IH2_BASE) 225#define INT_730_WAKE_UP_REQ (46 + IH2_BASE) 226#define INT_730_DMA_CH6 (53 + IH2_BASE) 227#define INT_730_DMA_CH7 (54 + IH2_BASE) 228#define INT_730_DMA_CH8 (55 + IH2_BASE) 229#define INT_730_DMA_CH9 (56 + IH2_BASE) 230#define INT_730_DMA_CH10 (57 + IH2_BASE) 231#define INT_730_DMA_CH11 (58 + IH2_BASE) 232#define INT_730_DMA_CH12 (59 + IH2_BASE) 233#define INT_730_DMA_CH13 (60 + IH2_BASE) 234#define INT_730_DMA_CH14 (61 + IH2_BASE) 235#define INT_730_DMA_CH15 (62 + IH2_BASE) 236#define INT_730_NAND (63 + IH2_BASE) 237 238#define INT_24XX_SYS_NIRQ 7 239#define INT_24XX_SDMA_IRQ0 12 240#define INT_24XX_SDMA_IRQ1 13 241#define INT_24XX_SDMA_IRQ2 14 242#define INT_24XX_SDMA_IRQ3 15 243#define INT_24XX_CAM_IRQ 24 244#define INT_24XX_DSS_IRQ 25 245#define INT_24XX_MAIL_U0_MPU 26 246#define INT_24XX_DSP_UMA 27 247#define INT_24XX_DSP_MMU 28 248#define INT_24XX_GPIO_BANK1 29 249#define INT_24XX_GPIO_BANK2 30 250#define INT_24XX_GPIO_BANK3 31 251#define INT_24XX_GPIO_BANK4 32 252#define INT_24XX_GPIO_BANK5 33 253#define INT_24XX_MAIL_U3_MPU 34 254#define INT_24XX_GPTIMER1 37 255#define INT_24XX_GPTIMER2 38 256#define INT_24XX_GPTIMER3 39 257#define INT_24XX_GPTIMER4 40 258#define INT_24XX_GPTIMER5 41 259#define INT_24XX_GPTIMER6 42 260#define INT_24XX_GPTIMER7 43 261#define INT_24XX_GPTIMER8 44 262#define INT_24XX_GPTIMER9 45 263#define INT_24XX_GPTIMER10 46 264#define INT_24XX_GPTIMER11 47 265#define INT_24XX_GPTIMER12 48 266#define INT_24XX_MCBSP1_IRQ_TX 59 267#define INT_24XX_MCBSP1_IRQ_RX 60 268#define INT_24XX_MCBSP2_IRQ_TX 62 269#define INT_24XX_MCBSP2_IRQ_RX 63 270#define INT_24XX_UART1_IRQ 72 271#define INT_24XX_UART2_IRQ 73 272#define INT_24XX_UART3_IRQ 74 273#define INT_24XX_USB_IRQ_GEN 75 274#define INT_24XX_USB_IRQ_NISO 76 275#define INT_24XX_USB_IRQ_ISO 77 276#define INT_24XX_USB_IRQ_HGEN 78 277#define INT_24XX_USB_IRQ_HSOF 79 278#define INT_24XX_USB_IRQ_OTG 80 279#define INT_24XX_MMC_IRQ 83 280 281/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and 282 * 16 MPUIO lines */ 283#define OMAP_MAX_GPIO_LINES 192 284#define IH_GPIO_BASE (128 + IH2_BASE) 285#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 286#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) 287 288#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 289 290#ifndef __ASSEMBLY__ 291extern void omap_init_irq(void); 292#endif 293 294/* 295 * The definition of NR_IRQS is in board-specific header file, which is 296 * included via hardware.h 297 */ 298#include <asm/hardware.h> 299 300#ifndef NR_IRQS 301#define NR_IRQS IH_BOARD_BASE 302#endif 303 304#endif 305