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  • only in /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-ixp4xx/
1/*
2 * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3 *
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
7 * and machine-name.h.
8 *
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#ifndef _ASM_ARM_IXP4XX_H_
23#define _ASM_ARM_IXP4XX_H_
24
25/*
26 * IXP4xx Linux Memory Map:
27 *
28 * Phy		Size		Virt		Description
29 * =========================================================================
30 *
31 * 0x00000000	0x10000000(max)	PAGE_OFFSET	System RAM
32 *
33 * 0x48000000	0x04000000	ioremap'd	PCI Memory Space
34 *
35 * 0x50000000	0x10000000	ioremap'd	EXP BUS
36 *
37 * 0x6000000	0x00004000	ioremap'd	QMgr
38 *
39 * 0xC0000000	0x00001000	0xffbff000	PCI CFG
40 *
41 * 0xC4000000	0x00001000	0xffbfe000	EXP CFG
42 *
43 * 0xC8000000	0x00013000	0xffbeb000	On-Chip Peripherals
44 */
45
46/*
47 * Queue Manager
48 */
49#define IXP4XX_QMGR_BASE_PHYS		(0x60000000)
50#define IXP4XX_QMGR_REGION_SIZE		(0x00004000)
51
52/*
53 * Expansion BUS Configuration registers
54 */
55#define IXP4XX_EXP_CFG_BASE_PHYS	(0xC4000000)
56#define IXP4XX_EXP_CFG_BASE_VIRT	(0xFFBFE000)
57#define IXP4XX_EXP_CFG_REGION_SIZE	(0x00001000)
58
59/*
60 * PCI Config registers
61 */
62#define IXP4XX_PCI_CFG_BASE_PHYS	(0xC0000000)
63#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFF000)
64#define IXP4XX_PCI_CFG_REGION_SIZE	(0x00001000)
65
66/*
67 * Peripheral space
68 */
69#define IXP4XX_PERIPHERAL_BASE_PHYS	(0xC8000000)
70#define IXP4XX_PERIPHERAL_BASE_VIRT	(0xFFBEB000)
71#define IXP4XX_PERIPHERAL_REGION_SIZE	(0x00013000)
72
73/*
74 * Debug UART
75 *
76 * This is basically a remap of UART1 into a region that is section
77 * aligned so that it * can be used with the low-level debug code.
78 */
79#define	IXP4XX_DEBUG_UART_BASE_PHYS	(0xC8000000)
80#define	IXP4XX_DEBUG_UART_BASE_VIRT	(0xffb00000)
81#define	IXP4XX_DEBUG_UART_REGION_SIZE	(0x00001000)
82
83#define IXP4XX_EXP_CS0_OFFSET	0x00
84#define IXP4XX_EXP_CS1_OFFSET   0x04
85#define IXP4XX_EXP_CS2_OFFSET   0x08
86#define IXP4XX_EXP_CS3_OFFSET   0x0C
87#define IXP4XX_EXP_CS4_OFFSET   0x10
88#define IXP4XX_EXP_CS5_OFFSET   0x14
89#define IXP4XX_EXP_CS6_OFFSET   0x18
90#define IXP4XX_EXP_CS7_OFFSET   0x1C
91#define IXP4XX_EXP_CFG0_OFFSET	0x20
92#define IXP4XX_EXP_CFG1_OFFSET	0x24
93#define IXP4XX_EXP_CFG2_OFFSET	0x28
94#define IXP4XX_EXP_CFG3_OFFSET	0x2C
95
96/*
97 * Expansion Bus Controller registers.
98 */
99#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
100
101#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
102#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
103#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
104#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
105#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
106#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
107#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
108#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
109
110#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
111#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
112#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
113#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
114
115
116/*
117 * Peripheral Space Register Region Base Addresses
118 */
119#define IXP4XX_UART1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
120#define IXP4XX_UART2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
121#define IXP4XX_PMU_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
122#define IXP4XX_INTC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
123#define IXP4XX_GPIO_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
124#define IXP4XX_TIMER_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
125#define IXP4XX_NPEA_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
126#define IXP4XX_NPEB_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
127#define IXP4XX_NPEC_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
128#define IXP4XX_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
129#define IXP4XX_EthC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
130#define IXP4XX_USB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
131/* ixp46X only */
132#define IXP4XX_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
133#define IXP4XX_EthB1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
134#define IXP4XX_EthB2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
135#define IXP4XX_EthB3_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
136#define IXP4XX_TIMESYNC_BASE_PHYS	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
137#define IXP4XX_I2C_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
138#define IXP4XX_SSP_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
139
140
141#define IXP4XX_UART1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
142#define IXP4XX_UART2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
143#define IXP4XX_PMU_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
144#define IXP4XX_INTC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
145#define IXP4XX_GPIO_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
146#define IXP4XX_TIMER_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
147#define IXP4XX_NPEA_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
148#define IXP4XX_NPEB_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
149#define IXP4XX_NPEC_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
150#define IXP4XX_EthB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
151#define IXP4XX_EthC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
152#define IXP4XX_USB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
153/* ixp46X only */
154#define IXP4XX_EthA_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
155#define IXP4XX_EthB1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
156#define IXP4XX_EthB2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
157#define IXP4XX_EthB3_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
158#define IXP4XX_TIMESYNC_BASE_VIRT	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
159#define IXP4XX_I2C_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
160#define IXP4XX_SSP_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
161
162/*
163 * Constants to make it easy to access  Interrupt Controller registers
164 */
165#define IXP4XX_ICPR_OFFSET	0x00 /* Interrupt Status */
166#define IXP4XX_ICMR_OFFSET	0x04 /* Interrupt Enable */
167#define IXP4XX_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
168#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
169#define IXP4XX_ICFP_OFFSET	0x10 /* FIQ Status */
170#define IXP4XX_ICHR_OFFSET	0x14 /* Interrupt Priority */
171#define IXP4XX_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
172#define IXP4XX_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
173
174/*
175 * IXP465-only
176 */
177#define	IXP4XX_ICPR2_OFFSET	0x20 /* Interrupt Status 2 */
178#define	IXP4XX_ICMR2_OFFSET	0x24 /* Interrupt Enable 2 */
179#define	IXP4XX_ICLR2_OFFSET	0x28 /* Interrupt IRQ/FIQ Select 2 */
180#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
181#define IXP4XX_ICFP2_OFFSET	0x30 /* FIQ Status */
182#define IXP4XX_ICEEN_OFFSET	0x34 /* Error High Pri Enable */
183
184
185/*
186 * Interrupt Controller Register Definitions.
187 */
188
189#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
190
191#define IXP4XX_ICPR	IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
192#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
193#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
194#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
195#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
196#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
197#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
198#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
199#define IXP4XX_ICPR2	IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
200#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
201#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
202#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
203#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
204#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
205
206/*
207 * Constants to make it easy to access GPIO registers
208 */
209#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
210#define IXP4XX_GPIO_GPOER_OFFSET        0x04
211#define IXP4XX_GPIO_GPINR_OFFSET        0x08
212#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
213#define IXP4XX_GPIO_GPIT1R_OFFSET	0x10
214#define IXP4XX_GPIO_GPIT2R_OFFSET	0x14
215#define IXP4XX_GPIO_GPCLKR_OFFSET	0x18
216#define IXP4XX_GPIO_GPDBSELR_OFFSET	0x1C
217
218/*
219 * GPIO Register Definitions.
220 * [Only perform 32bit reads/writes]
221 */
222#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
223
224#define IXP4XX_GPIO_GPOUTR	IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
225#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
226#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
227#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
228#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
229#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
230#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
231#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
232
233/*
234 * GPIO register bit definitions
235 */
236
237/* Interrupt styles
238 */
239#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH	0x0
240#define IXP4XX_GPIO_STYLE_ACTIVE_LOW	0x1
241#define IXP4XX_GPIO_STYLE_RISING_EDGE	0x2
242#define IXP4XX_GPIO_STYLE_FALLING_EDGE	0x3
243#define IXP4XX_GPIO_STYLE_TRANSITIONAL	0x4
244
245/*
246 * Mask used to clear interrupt styles
247 */
248#define IXP4XX_GPIO_STYLE_CLEAR		0x7
249#define IXP4XX_GPIO_STYLE_SIZE		3
250
251/*
252 * Constants to make it easy to access Timer Control/Status registers
253 */
254#define IXP4XX_OSTS_OFFSET	0x00  /* Continious TimeStamp */
255#define IXP4XX_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
256#define IXP4XX_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
257#define IXP4XX_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
258#define IXP4XX_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
259#define IXP4XX_OSWT_OFFSET	0x14  /* Watchdog Timer */
260#define IXP4XX_OSWE_OFFSET	0x18  /* Watchdog Enable */
261#define IXP4XX_OSWK_OFFSET	0x1C  /* Watchdog Key */
262#define IXP4XX_OSST_OFFSET	0x20  /* Timer Status */
263
264/*
265 * Operating System Timer Register Definitions.
266 */
267
268#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
269
270#define IXP4XX_OSTS	IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
271#define IXP4XX_OST1	IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
272#define IXP4XX_OSRT1	IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
273#define IXP4XX_OST2	IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
274#define IXP4XX_OSRT2	IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
275#define IXP4XX_OSWT	IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
276#define IXP4XX_OSWE	IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
277#define IXP4XX_OSWK	IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
278#define IXP4XX_OSST	IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
279
280/*
281 * Timer register values and bit definitions
282 */
283#define IXP4XX_OST_ENABLE		0x00000001
284#define IXP4XX_OST_ONE_SHOT		0x00000002
285/* Low order bits of reload value ignored */
286#define IXP4XX_OST_RELOAD_MASK		0x00000003
287#define IXP4XX_OST_DISABLED		0x00000000
288#define IXP4XX_OSST_TIMER_1_PEND	0x00000001
289#define IXP4XX_OSST_TIMER_2_PEND	0x00000002
290#define IXP4XX_OSST_TIMER_TS_PEND	0x00000004
291#define IXP4XX_OSST_TIMER_WDOG_PEND	0x00000008
292#define IXP4XX_OSST_TIMER_WARM_RESET	0x00000010
293
294#define	IXP4XX_WDT_KEY			0x0000482E
295
296#define	IXP4XX_WDT_RESET_ENABLE		0x00000001
297#define	IXP4XX_WDT_IRQ_ENABLE		0x00000002
298#define	IXP4XX_WDT_COUNT_ENABLE		0x00000004
299
300
301/*
302 * Constants to make it easy to access PCI Control/Status registers
303 */
304#define PCI_NP_AD_OFFSET            0x00
305#define PCI_NP_CBE_OFFSET           0x04
306#define PCI_NP_WDATA_OFFSET         0x08
307#define PCI_NP_RDATA_OFFSET         0x0c
308#define PCI_CRP_AD_CBE_OFFSET       0x10
309#define PCI_CRP_WDATA_OFFSET        0x14
310#define PCI_CRP_RDATA_OFFSET        0x18
311#define PCI_CSR_OFFSET              0x1c
312#define PCI_ISR_OFFSET              0x20
313#define PCI_INTEN_OFFSET            0x24
314#define PCI_DMACTRL_OFFSET          0x28
315#define PCI_AHBMEMBASE_OFFSET       0x2c
316#define PCI_AHBIOBASE_OFFSET        0x30
317#define PCI_PCIMEMBASE_OFFSET       0x34
318#define PCI_AHBDOORBELL_OFFSET      0x38
319#define PCI_PCIDOORBELL_OFFSET      0x3C
320#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
321#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
322#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
323#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
324#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
325#define PCI_ATPDMA1_LENADDR_OFFSET	0x54
326
327/*
328 * PCI Control/Status Registers
329 */
330#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
331
332#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
333#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
334#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
335#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
336#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
337#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
338#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
339#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
340#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
341#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
342#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
343#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
344#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
345#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
346#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
347#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
348#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
349#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
350#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
351#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
352#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
353#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
354
355/*
356 * PCI register values and bit definitions
357 */
358
359/* CSR bit definitions */
360#define PCI_CSR_HOST    	0x00000001
361#define PCI_CSR_ARBEN   	0x00000002
362#define PCI_CSR_ADS     	0x00000004
363#define PCI_CSR_PDS     	0x00000008
364#define PCI_CSR_ABE     	0x00000010
365#define PCI_CSR_DBT     	0x00000020
366#define PCI_CSR_ASE     	0x00000100
367#define PCI_CSR_IC      	0x00008000
368
369/* ISR (Interrupt status) Register bit definitions */
370#define PCI_ISR_PSE     	0x00000001
371#define PCI_ISR_PFE     	0x00000002
372#define PCI_ISR_PPE     	0x00000004
373#define PCI_ISR_AHBE    	0x00000008
374#define PCI_ISR_APDC    	0x00000010
375#define PCI_ISR_PADC    	0x00000020
376#define PCI_ISR_ADB     	0x00000040
377#define PCI_ISR_PDB     	0x00000080
378
379/* INTEN (Interrupt Enable) Register bit definitions */
380#define PCI_INTEN_PSE   	0x00000001
381#define PCI_INTEN_PFE   	0x00000002
382#define PCI_INTEN_PPE   	0x00000004
383#define PCI_INTEN_AHBE  	0x00000008
384#define PCI_INTEN_APDC  	0x00000010
385#define PCI_INTEN_PADC  	0x00000020
386#define PCI_INTEN_ADB   	0x00000040
387#define PCI_INTEN_PDB   	0x00000080
388
389/*
390 * Shift value for byte enable on NP cmd/byte enable register
391 */
392#define IXP4XX_PCI_NP_CBE_BESL		4
393
394/*
395 * PCI commands supported by NP access unit
396 */
397#define NP_CMD_IOREAD			0x2
398#define NP_CMD_IOWRITE			0x3
399#define NP_CMD_CONFIGREAD		0xa
400#define NP_CMD_CONFIGWRITE		0xb
401#define NP_CMD_MEMREAD			0x6
402#define	NP_CMD_MEMWRITE			0x7
403
404/*
405 * Constants for CRP access into local config space
406 */
407#define CRP_AD_CBE_BESL         20
408#define CRP_AD_CBE_WRITE	0x00010000
409
410
411/*
412 * USB Device Controller
413 *
414 * These are used by the USB gadget driver, so they don't follow the
415 * IXP4XX_ naming convetions.
416 *
417 */
418# define IXP4XX_USB_REG(x)       (*((volatile u32 *)(x)))
419
420/* UDC Undocumented - Reserved1 */
421#define UDC_RES1	IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
422/* UDC Undocumented - Reserved2 */
423#define UDC_RES2	IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
424/* UDC Undocumented - Reserved3 */
425#define UDC_RES3	IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
426/* UDC Control Register */
427#define UDCCR		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
428/* UDC Endpoint 0 Control/Status Register */
429#define UDCCS0		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
430/* UDC Endpoint 1 (IN) Control/Status Register */
431#define UDCCS1		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
432/* UDC Endpoint 2 (OUT) Control/Status Register */
433#define UDCCS2		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
434/* UDC Endpoint 3 (IN) Control/Status Register */
435#define UDCCS3		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
436/* UDC Endpoint 4 (OUT) Control/Status Register */
437#define UDCCS4		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
438/* UDC Endpoint 5 (Interrupt) Control/Status Register */
439#define UDCCS5		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
440/* UDC Endpoint 6 (IN) Control/Status Register */
441#define UDCCS6		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
442/* UDC Endpoint 7 (OUT) Control/Status Register */
443#define UDCCS7		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
444/* UDC Endpoint 8 (IN) Control/Status Register */
445#define UDCCS8		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
446/* UDC Endpoint 9 (OUT) Control/Status Register */
447#define UDCCS9		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
448/* UDC Endpoint 10 (Interrupt) Control/Status Register */
449#define UDCCS10		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
450/* UDC Endpoint 11 (IN) Control/Status Register */
451#define UDCCS11		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
452/* UDC Endpoint 12 (OUT) Control/Status Register */
453#define UDCCS12		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
454/* UDC Endpoint 13 (IN) Control/Status Register */
455#define UDCCS13		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
456/* UDC Endpoint 14 (OUT) Control/Status Register */
457#define UDCCS14		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
458/* UDC Endpoint 15 (Interrupt) Control/Status Register */
459#define UDCCS15		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
460/* UDC Frame Number Register High */
461#define UFNRH		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
462/* UDC Frame Number Register Low */
463#define UFNRL		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
464/* UDC Byte Count Reg 2 */
465#define UBCR2		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
466/* UDC Byte Count Reg 4 */
467#define UBCR4		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
468/* UDC Byte Count Reg 7 */
469#define UBCR7		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
470/* UDC Byte Count Reg 9 */
471#define UBCR9		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
472/* UDC Byte Count Reg 12 */
473#define UBCR12		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
474/* UDC Byte Count Reg 14 */
475#define UBCR14		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
476/* UDC Endpoint 0 Data Register */
477#define UDDR0		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
478/* UDC Endpoint 1 Data Register */
479#define UDDR1		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
480/* UDC Endpoint 2 Data Register */
481#define UDDR2		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
482/* UDC Endpoint 3 Data Register */
483#define UDDR3		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
484/* UDC Endpoint 4 Data Register */
485#define UDDR4		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
486/* UDC Endpoint 5 Data Register */
487#define UDDR5		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
488/* UDC Endpoint 6 Data Register */
489#define UDDR6		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
490/* UDC Endpoint 7 Data Register */
491#define UDDR7		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
492/* UDC Endpoint 8 Data Register */
493#define UDDR8		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
494/* UDC Endpoint 9 Data Register */
495#define UDDR9		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
496/* UDC Endpoint 10 Data Register */
497#define UDDR10		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
498/* UDC Endpoint 11 Data Register */
499#define UDDR11		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
500/* UDC Endpoint 12 Data Register */
501#define UDDR12		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
502/* UDC Endpoint 13 Data Register */
503#define UDDR13		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
504/* UDC Endpoint 14 Data Register */
505#define UDDR14		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
506/* UDC Endpoint 15 Data Register */
507#define UDDR15		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
508/* UDC Interrupt Control Register 0 */
509#define UICR0		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
510/* UDC Interrupt Control Register 1 */
511#define UICR1		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
512/* UDC Status Interrupt Register 0 */
513#define USIR0		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
514/* UDC Status Interrupt Register 1 */
515#define USIR1		IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
516
517#define UDCCR_UDE	(1 << 0)	/* UDC enable */
518#define UDCCR_UDA	(1 << 1)	/* UDC active */
519#define UDCCR_RSM	(1 << 2)	/* Device resume */
520#define UDCCR_RESIR	(1 << 3)	/* Resume interrupt request */
521#define UDCCR_SUSIR	(1 << 4)	/* Suspend interrupt request */
522#define UDCCR_SRM	(1 << 5)	/* Suspend/resume interrupt mask */
523#define UDCCR_RSTIR	(1 << 6)	/* Reset interrupt request */
524#define UDCCR_REM	(1 << 7)	/* Reset interrupt mask */
525
526#define UDCCS0_OPR	(1 << 0)	/* OUT packet ready */
527#define UDCCS0_IPR	(1 << 1)	/* IN packet ready */
528#define UDCCS0_FTF	(1 << 2)	/* Flush Tx FIFO */
529#define UDCCS0_DRWF	(1 << 3)	/* Device remote wakeup feature */
530#define UDCCS0_SST	(1 << 4)	/* Sent stall */
531#define UDCCS0_FST	(1 << 5)	/* Force stall */
532#define UDCCS0_RNE	(1 << 6)	/* Receive FIFO no empty */
533#define UDCCS0_SA	(1 << 7)	/* Setup active */
534
535#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
536#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
537#define UDCCS_BI_FTF	(1 << 2)	/* Flush Tx FIFO */
538#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
539#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
540#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
541#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
542
543#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
544#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
545#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
546#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
547#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
548#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
549#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
550
551#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
552#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
553#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
554#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
555#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
556
557#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
558#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
559#define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
560#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
561#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
562#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
563
564#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
565#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
566#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
567#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
568#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
569#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
570#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
571
572#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
573#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
574#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
575#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
576#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
577#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
578#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
579#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
580
581#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
582#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
583#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
584#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
585#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
586#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
587#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
588#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
589
590#define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
591#define USIR0_IR1	(1 << 1)	/* Interrup request ep 1 */
592#define USIR0_IR2	(1 << 2)	/* Interrup request ep 2 */
593#define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
594#define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
595#define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
596#define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
597#define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
598
599#define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
600#define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
601#define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
602#define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
603#define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
604#define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
605#define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
606#define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
607
608#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
609
610#endif
611