1/*
2 * include/asm-arm/arch-at91/at91_lcdc.h
3 *
4 * LCD Controller (LCDC).
5 * Based on AT91SAM9261 datasheet revision E.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_LCDC_H
14#define AT91_LCDC_H
15
16#define AT91_LCDC_DMABADDR1	0x00		/* DMA Base Address Register 1 */
17#define AT91_LCDC_DMABADDR2	0x04		/* DMA Base Address Register 2 */
18#define AT91_LCDC_DMAFRMPT1	0x08		/* DMA Frame Pointer Register 1 */
19#define AT91_LCDC_DMAFRMPT2	0x0c		/* DMA Frame Pointer Register 2 */
20#define AT91_LCDC_DMAFRMADD1	0x10		/* DMA Frame Address Register 1 */
21#define AT91_LCDC_DMAFRMADD2	0x14		/* DMA Frame Address Register 2 */
22
23#define AT91_LCDC_DMAFRMCFG	0x18		/* DMA Frame Configuration Register */
24#define		AT91_LCDC_FRSIZE	(0x7fffff <<  0)	/* Frame Size */
25#define		AT91_LCDC_BLENGTH	(0x7f     << 24)	/* Burst Length */
26
27#define AT91_LCDC_DMACON	0x1c		/* DMA Control Register */
28#define		AT91_LCDC_DMAEN		(0x1 << 0)	/* DMA Enable */
29#define		AT91_LCDC_DMARST	(0x1 << 1)	/* DMA Reset */
30#define		AT91_LCDC_DMABUSY	(0x1 << 2)	/* DMA Busy */
31
32#define AT91_LCDC_LCDCON1	0x0800		/* LCD Control Register 1 */
33#define		AT91_LCDC_BYPASS	(1     <<  0)	/* Bypass lcd_dotck divider */
34#define		AT91_LCDC_CLKVAL	(0x1ff << 12)	/* Clock Divider */
35#define		AT91_LCDC_LINCNT	(0x7ff << 21)	/* Line Counter */
36
37#define AT91_LCDC_LCDCON2	0x0804		/* LCD Control Register 2 */
38#define		AT91_LCDC_DISTYPE	(3 << 0)	/* Display Type */
39#define			AT91_LCDC_DISTYPE_STNMONO	(0 << 0)
40#define			AT91_LCDC_DISTYPE_STNCOLOR	(1 << 0)
41#define			AT91_LCDC_DISTYPE_TFT		(2 << 0)
42#define		AT91_LCDC_SCANMOD	(1 << 2)	/* Scan Mode */
43#define			AT91_LCDC_SCANMOD_SINGLE	(0 << 2)
44#define			AT91_LCDC_SCANMOD_DUAL		(1 << 2)
45#define		AT91_LCDC_IFWIDTH	(3 << 3)	/*Interface Width */
46#define			AT91_LCDC_IFWIDTH_4		(0 << 3)
47#define			AT91_LCDC_IFWIDTH_8		(1 << 3)
48#define			AT91_LCDC_IFWIDTH_16		(2 << 3)
49#define		AT91_LCDC_PIXELSIZE	(7 << 5)	/* Bits per pixel */
50#define			AT91_LCDC_PIXELSIZE_1		(0 << 5)
51#define			AT91_LCDC_PIXELSIZE_2		(1 << 5)
52#define			AT91_LCDC_PIXELSIZE_4		(2 << 5)
53#define			AT91_LCDC_PIXELSIZE_8		(3 << 5)
54#define			AT91_LCDC_PIXELSIZE_16		(4 << 5)
55#define			AT91_LCDC_PIXELSIZE_24		(5 << 5)
56#define		AT91_LCDC_INVVD		(1 << 8)	/* LCD Data polarity */
57#define			AT91_LCDC_INVVD_NORMAL		(0 << 8)
58#define			AT91_LCDC_INVVD_INVERTED	(1 << 8)
59#define		AT91_LCDC_INVFRAME	(1 << 9 )	/* LCD VSync polarity */
60#define			AT91_LCDC_INVFRAME_NORMAL	(0 << 9)
61#define			AT91_LCDC_INVFRAME_INVERTED	(1 << 9)
62#define		AT91_LCDC_INVLINE	(1 << 10)	/* LCD HSync polarity */
63#define			AT91_LCDC_INVLINE_NORMAL	(0 << 10)
64#define			AT91_LCDC_INVLINE_INVERTED	(1 << 10)
65#define		AT91_LCDC_INVCLK	(1 << 11)	/* LCD dotclk polarity */
66#define			AT91_LCDC_INVCLK_NORMAL		(0 << 11)
67#define			AT91_LCDC_INVCLK_INVERTED	(1 << 11)
68#define		AT91_LCDC_INVDVAL	(1 << 12)	/* LCD dval polarity */
69#define			AT91_LCDC_INVDVAL_NORMAL	(0 << 12)
70#define			AT91_LCDC_INVDVAL_INVERTED	(1 << 12)
71#define		AT91_LCDC_CLKMOD	(1 << 15)	/* LCD dotclk mode */
72#define			AT91_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
73#define			AT91_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
74#define		AT91_LCDC_MEMOR		(1 << 31)	/* Memory Ordering Format */
75#define			AT91_LCDC_MEMOR_BIG		(0 << 31)
76#define			AT91_LCDC_MEMOR_LITTLE		(1 << 31)
77
78#define AT91_LCDC_TIM1		0x0808		/* LCD Timing Register 1 */
79#define		AT91_LCDC_VFP		(0xff <<  0)	/* Vertical Front Porch */
80#define		AT91_LCDC_VBP		(0xff <<  8)	/* Vertical Back Porch */
81#define		AT91_LCDC_VPW		(0x3f << 16)	/* Vertical Synchronization Pulse Width */
82#define		AT91_LCDC_VHDLY		(0xf  << 24)	/* Vertical to Horizontal Delay */
83
84#define AT91_LCDC_TIM2		0x080c		/* LCD Timing Register 2 */
85#define		AT91_LCDC_HBP		(0xff  <<  0)	/* Horizontal Back Porch */
86#define		AT91_LCDC_HPW		(0x3f  <<  8)	/* Horizontal Synchronization Pulse Width */
87#define		AT91_LCDC_HFP		(0x7ff << 21)	/* Horizontal Front Porch */
88
89#define AT91_LCDC_LCDFRMCFG	0x0810		/* LCD Frame Configuration Register */
90#define		AT91_LCDC_LINEVAL	(0x7ff <<  0)	/* Vertical Size of LCD Module */
91#define		AT91_LCDC_HOZVAL	(0x7ff << 21)	/* Horizontal Size of LCD Module */
92
93#define AT91_LCDC_FIFO		0x0814		/* LCD FIFO Register */
94#define		AT91_LCDC_FIFOTH	(0xffff)	/* FIFO Threshold */
95
96#define AT91_LCDC_DP1_2		0x081c		/* Dithering Pattern DP1_2 Register */
97#define AT91_LCDC_DP4_7		0x0820		/* Dithering Pattern DP4_7 Register */
98#define AT91_LCDC_DP3_5		0x0824		/* Dithering Pattern DP3_5 Register */
99#define AT91_LCDC_DP2_3		0x0828		/* Dithering Pattern DP2_3 Register */
100#define AT91_LCDC_DP5_7		0x082c		/* Dithering Pattern DP5_7 Register */
101#define AT91_LCDC_DP3_4		0x0830		/* Dithering Pattern DP3_4 Register */
102#define AT91_LCDC_DP4_5		0x0834		/* Dithering Pattern DP4_5 Register */
103#define AT91_LCDC_DP6_7		0x0838		/* Dithering Pattern DP6_7 Register */
104#define		AT91_LCDC_DP1_2_VAL	(0xff)
105#define		AT91_LCDC_DP4_7_VAL	(0xfffffff)
106#define		AT91_LCDC_DP3_5_VAL	(0xfffff)
107#define		AT91_LCDC_DP2_3_VAL	(0xfff)
108#define		AT91_LCDC_DP5_7_VAL	(0xfffffff)
109#define		AT91_LCDC_DP3_4_VAL	(0xffff)
110#define		AT91_LCDC_DP4_5_VAL	(0xfffff)
111#define		AT91_LCDC_DP6_7_VAL	(0xfffffff)
112
113#define AT91_LCDC_PWRCON	0x083c		/* Power Control Register */
114#define		AT91_LCDC_PWR		(1    <<  0)	/* LCD Module Power Control */
115#define		AT91_LCDC_GUARDT	(0x7f <<  1)	/* Delay in Frame Period */
116#define		AT91_LCDC_BUSY		(1    << 31)	/* LCD Busy */
117
118#define AT91_LCDC_CONTRAST_CTR	0x0840		/* Contrast Control Register */
119#define		AT91_LCDC_PS		(3 << 0)	/* Contrast Counter Prescaler */
120#define			AT91_LCDC_PS_DIV1		(0 << 0)
121#define			AT91_LCDC_PS_DIV2		(1 << 0)
122#define			AT91_LCDC_PS_DIV4		(2 << 0)
123#define			AT91_LCDC_PS_DIV8		(3 << 0)
124#define		AT91_LCDC_POL		(1 << 2)	/* Polarity of output Pulse */
125#define			AT91_LCDC_POL_NEGATIVE		(0 << 2)
126#define			AT91_LCDC_POL_POSITIVE		(1 << 2)
127#define		AT91_LCDC_ENA		(1 << 3)	/* PWM generator Control */
128#define			AT91_LCDC_ENA_PWMDISABLE	(0 << 3)
129#define			AT91_LCDC_ENA_PWMENABLE		(1 << 3)
130
131#define AT91_LCDC_CONTRAST_VAL	0x0844		/* Contrast Value Register */
132#define		AT91_LCDC_CVAL		(0xff)		/* PWM compare value */
133
134#define AT91_LCDC_IER		0x0848		/* Interrupt Enable Register */
135#define AT91_LCDC_IDR		0x084c		/* Interrupt Disable Register */
136#define AT91_LCDC_IMR		0x0850		/* Interrupt Mask Register */
137#define AT91_LCDC_ISR		0x0854		/* Interrupt Enable Register */
138#define AT91_LCDC_ICR		0x0858		/* Interrupt Clear Register */
139#define		AT91_LCDC_LNI		(1 << 0)	/* Line Interrupt */
140#define		AT91_LCDC_LSTLNI	(1 << 1)	/* Last Line Interrupt */
141#define		AT91_LCDC_EOFI		(1 << 2)	/* DMA End Of Frame Interrupt */
142#define		AT91_LCDC_UFLWI		(1 << 4)	/* FIFO Underflow Interrupt */
143#define		AT91_LCDC_OWRI		(1 << 5)	/* FIFO Overwrite Interrupt */
144#define		AT91_LCDC_MERI		(1 << 6)	/* DMA Memory Error Interrupt */
145
146#define AT91_LCDC_LUT_(n)	(0x0c00 + ((n)*4))	/* Palette Entry 0..255 */
147
148#endif
149